74HC368 PHILIPS

Document overview

  • PDF pages: 7

Technical content

Page 1

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FEATURES

  • Inverting outputs
  • Output capability: bus driver
  • ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT368 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

The 74HC/HCT368 are hex inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable inputs (1OE, 2OE). A HIGH on nOE causes the outputs to assume a high impedance OFF-state. The “368” is identical to the “367” but has inverting outputs.

SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC HCT
t / t PHL PLH propagation delay nA to nY C = 15 pF; V = 5 V L CC 9 11 ns
C I input capacitance 3.5 3.5 pF
C PD power dissipation capacitance per buffer notes 1 and 2 30 30 pF

Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC −1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

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PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION
1, 15 2, 4, 6, 10, 12, 14 3, 5, 7, 9, 11, 13 8 16 1OE, 2OE 1A to 6A 1Y to 6Y GND V CC output enable inputs (active LOW) data inputs data outputs ground (0 V) positive supply voltage
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Fig.2 Logic symbol.

Fig.1 Pin configuration.

Fig.3 IEC logic symbol.

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FUNCTION TABLE

Column 1 Column 2 Column 3
INPUTS OUTPUTS
nOE nA nY
L L H L H X H L Z
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Note 1. H = HIGH voltage level L = LOW voltage level X = don’t care Z = high impedance OFF-state

Fig.4 Functional diagram.

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Fig.5 Logic diagram.

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DC CHARACTERISTICS FOR 74HC

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver ICC category: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; tr = tf = 6 ns; CL = 50 pF

SYMBOL PARAMETER T (°C) amb UNIT TEST CONDITIONS
74HC V CC (V) WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t / t PHL PLH propagation delay nA to nY 30 11 9 95 19 16 120 24 20 145 29 25 ns 2.0 4.5 6.0 Fig.6
t / t PZH PZL 3-state output enable time nOE to nY 41 15 12 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 Fig.7
t / t PHZ PLZ 3-state output disable time nOE to nY 55 20 16 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 Fig.7
t / t THL TLH output transition time 14 5 4 60 12 10 75 15 13 90 18 15 ns 2.0 4.5 6.0 Fig.6

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DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver ICC category: MSI

Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.

INPUT UNIT LOAD COEFFICIENT
1OE 2OE nA 1.00 0.90 1.00

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; tr = tf = 6 ns; CL = 50 pF

SYMBOL PARAMETER T (°C) amb UNIT TEST CONDITIONS
74HCT V CC (V) WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t / t PHL PLH propagation delay nA to nY 13 24 30 36 ns 4.5 Fig.6
t / t PZH PZL 3-state output enable time nOE to nY 17 35 44 53 ns 4.5 Fig.7
t / t PHZ PLZ 3-state output disable time nOE to nY 20 35 44 53 ns 4.5 Fig.7
t / t THL TLH output transition time 5 12 15 18 ns 4.5 Fig.6

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