74HC2G126 PHILIPS

Document overview

  • PDF pages: 20

Technical content

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INTEGRATED CIRCUITS

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FEATURES

  • Wide operating voltage from 2.0 to 6.0 V
  • Symmetrical output impedance
  • High noise immunity
  • Low power dissipation
  • Balanced propagation delays
  • Very small 8 pins package
  • Output capability: bus driver
  • ESD protection: – HBM EIA/JESD22-A114-A exceeds 2000 V – MM EIA/JESD22-A115-A exceeds 200 V
  • Specified from −40 to +85 °C and −40 to +125 °C.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = rf ≤ 6.0 ns.

DESCRIPTION

The 74HC2G/HCT2G126 is a high-speed Si-gate CMOS device. The 74HC2G/HCT2G126 provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input pin (OE). A LOW at pin OE causes the output as assume a high-impedance OFF-state. The bus driver output currents are equal compared to the 74HC/HCT126.

SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC2G HCT2G
t /t PHL PLH propagation delay nA to nY C = 15 pF; V = 5 V L CC 10 12 ns
C I input capacitance 1 1 pF
C O output capacitance 1.5 1.5 pF
C PD power dissipation capacitance per buffer output enabled; notes 1 and 2 11 11 pF
output disabled; notes 1 and 2 1 1 pF

Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. For the 74HC2G126 the condition is VI = GND to VCC. For the 74HCT2G126 the condition is VI = GND to VCC − 1.5 V.

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FUNCTION TABLE

See note 1.

Column 1 Column 2 Column 3
INPUT OUTPUT
nOE nA nY
H L L
H H H
L X Z

Note 1. H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.

ORDERING INFORMATION

TYPE NUMBER TEMPERATURE RANGE PACKAGE
PINS PACKAGE MATERIAL CODE MARKING
74HC2G126DP −40 to +125 °C 8 TSSOP8 plastic SOT505-2 H26
74HCT2G126DP −40 to +125 °C 8 TSSOP8 plastic SOT505-2 T26
74HC2G126DC −40 to +125 °C 8 VSSOP8 plastic SOT765-1 H26
74HCT2G126DC −40 to +125 °C 8 VSSOP8 plastic SOT765-1 T26

PIN DESCRIPTION

PIN SYMBOL DESCRIPTION
1 1OE output enable input
2 1A data input
3 2Y data output
4 GND ground (0 V)
5 2A data input
6 1Y data output
7 2OE output enable input
8 V CC supply voltage

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RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER CONDITIONS 74HC2G126 74HCT2G126 UNIT
MIN. TYP. MAX. MIN. TYP. MAX.
V CC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
V I input voltage 0 − V CC 0 − V CC V
V O output voltage 0 − V CC 0 − V CC V
T amb operating ambient temperature see DC and AC characteristics per device −40 +25 +125 −40 +25 +125 °C
t, t r f input rise and fall times V = 2.0 V CC − − 1000 − − − ns
V = 4.5 V CC − 6.0 500 − 6.0 500 ns
V = 6.0 V CC − − 400 − − − ns

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V CC supply voltage −0.5 +7.0 V
I IK input diode current V < −0.5 V or V > V + 0.5 V; note 1 I I CC − ±20 mA
I OK output diode current V < −0.5 V or V > V + 0.5 V; note 1 O O CC − ±20 mA
I O output source or sink current −0.5 V < V < V + 0.5 V; note 1 O CC − 25 mA
I , I CC GND V or GND current CC note 1 − 50 mA
T stg storage temperature −65 +150 °C
P D power dissipation per package for temperature range from −40 to +125 °C; note 2 − 300 mW

Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. Above 110 °C the value of PD derates linearly with 8 mW/K.

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DC CHARACTERISTICS

Type 74HC2G126 At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNIT
OTHER V (V) CC
T = −40 to +85 °C amb
V IH HIGH-level input voltage 2.0 1.5 1.2 − V
4.5 3.15 2.4 − V
6.0 4.2 3.2 − V
V IL LOW-level input voltage 2.0 − 0.8 0.5 V
4.5 − 2.1 1.35 V
6.0 − 2.8 1.8 V
V OH HIGH-level output voltage V = V or V I IH IL I = −20 µA O I = −20 µA O I = −20 µA O I = −6.0 mA O I = −7.8 mA O 2.0 4.5 6.0 4.5 6.0 1.9 4.4 5.9 4.13 5.63 2.0 4.5 6.0 4.32 5.81 − − − − − V V V V V
V OL LOW-level output voltage V = V or V I IH IL I = 20 µA O I = 20 µA O I = 20 µA O I = 6.0 mA O I = 7.8 mA O 2.0 4.5 6.0 4.5 6.0 − − − − − 0 0 0 0.15 0.16 0.1 0.1 0.1 0.33 0.33 V V V V V
I LI input leakage current V = V or GND I CC 6.0 − − ±1.0 µA
I OZ 3-state output OFF current V = V or V IL; I IH V = V or GND O CC 6.0 − − ±.5.0 µA
I CC quiescent supply current V = V or GND; I CC I = 0 O 6.0 − − 10 µA

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SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNIT
OTHER V (V) CC
T = −40 to +125 °C amb
V IH HIGH-level input voltage 2.0 1.5 − − V
4.5 3.15 − − V
6.0 4.2 − − V
V IL LOW-level input voltage 2.0 − − 0.5 V
4.5 − − 1.35 V
6.0 − − 1.8 V
V OH HIGH-level output voltage V = V or V I IH IL I = −20 µA O I = −20 µA O I = −20 µA O I = −6.0 mA O I = −7.8 mA O 2.0 4.5 6.0 4.5 6.0 1.9 4.4 5.9 3.7 5.2 − − − − − − − − − − V V V V V
V OL LOW-level output voltage V = V or V I IH IL I = 20 µA O I = 20 µA O I = 20 µA O I = 6.0 mA O I = 7.8 mA O 2.0 4.5 6.0 4.5 6.0 − − − − − − − − − − 0.1 0.1 0.1 0.4 0.4 V V V V V
I LI input leakage current V = V or GND I CC 6.0 − − ±1.0 µA
I OZ 3-state output OFF current V = V or V IL; I IH V = V or GND O CC 6.0 − − ±10.4 µA
I CC quiescent supply current V = V or GND; I CC I = 0 O 6.0 − − 20 µA

Note 1. All typical values are measured at Tamb = 25°C.

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Type 74HCT2G126 At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNIT
OTHER V (V) CC
T = −40 to +85 °C amb
V IH HIGH-level input voltage 4.5 to 5.5 2.0 1.6 − V
V IL LOW-level input voltage 4.5 to 5.5 − 1.2 0.8 V
V OH HIGH-level output voltage V = V or V I IH IL I = −20 µA O I = −6.0 mA O 4.5 4.5 4.4 4.13 4.5 4.32 − − V V
V OL LOW-level output voltage V = V or V I IH IL I = 20 µA O I = 6.0 mA O 4.5 4.5 − − 0 0.15 0.1 0.33 V V
I LI input leakage current V = V or GND I CC 5.5 − − ±1.0 µA
I OZ 3-state output OFF current V = V or V IL; I IH V = V or GND O CC 5.5 − − ±5.0 µA
I CC quiescent supply current V = V or GND; I CC I = 0 O 5.5 − − 10 µA
∆I CC additional supply current per input V = V −2.1 V; I CC I = 0 O 4.5 to 5.5 − − 375 µA
T = −40 to +125 °C amb
V IH HIGH-level input voltage 4.5 to 5.5 2.0 − − V
V IL LOW-level input voltage 4.5 to 5.5 − − 0.8 V
V OH HIGH-level output voltage V = V or V I IH IL I = −20 µA O I = −6.0 mA O 4.5 4.5 4.4 3.7 − − − − V V
V OL LOW-level output voltage V = V or V I IH IL I = 20 µA O I = 6.0 mA O 4.5 4.5 − − − − 0.1 0.4 V V
I LI input leakage current V = V or GND I CC 5.5 − − ±1.0 µA
I OZ 3-state output OFF current V = V or V IL; I IH V = V or GND O CC 5.5 − − ±10.4 µA
I CC quiescent supply current V = V or GND; I CC I = 0 O 5.5 − − 20 µA
∆I CC additional supply current per input V = V −2.1 V; I CC I = 0 O 4.5 to 5.5 − − 410 µA

Note 1. All typical values are measured at Tamb = 25°C.

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AC CHARACTERISTICS

Type 74HC2G126 GND = 0 V; tr = tf ≤ 6.0 ns; CL = 50 pF.

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNIT
WAVEFORMS V (V) CC
T = −40 to +85 °C amb
t /t PHL PLH propagation delay nA to nY see Figs 5 and 7 2.0 − 35 115 ns
4.5 − 11 23 ns
6.0 − 8 20 ns
t /t PZH PZL 3-state output enable time nOE to nY see Figs 6 and 7 2.0 − 40 115 ns
4.5 − 11 23 ns
6.0 − 8 20 ns
t /t PHZ PLZ 3-state output disable time nOE to nY see Figs 6 and 7 2.0 − 25 125 ns
4.5 − 12 25 ns
6.0 − 10 21 ns
t /t THL TLH output transition time see Figs 5 and 7 2.0 − 18 75 ns
4.5 − 6 15 ns
6.0 − 5 13 ns
T = −40 to +125 °C amb
t /t PHL PLH propagation delay nA to nY see Figs 5 and 7 2.0 − − 135 ns
4.5 − − 27 ns
6.0 − − 23 ns
t /t PZH PZL 3-state output enable time nOE to nY see Figs 6 and 7 2.0 − − 135 ns
4.5 − − 27 ns
6.0 − − 23 ns
t /t PHZ PLZ 3-state output disable time nOE to nY see Figs 6 and 7 2.0 − − 150 ns
4.5 − − 30 ns
6.0 − − 26 ns
t /t THL TLH output transition time see Figs 5 and 7 2.0 − − 90 ns
4.5 − − 18 ns
6.0 − − 15 ns

Note 1. All typical values are measured at Tamb = 25°C.

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Type 74HCT2G126 GND = 0 V; tr = tf ≤ 6.0 ns; CL = 50 pF.

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNIT
WAVEFORMS V (V) CC
T = −40 to +85 °C amb
t /t PHL PLH propagation delay nA to nY see Figs 5 and 7 4.5 − 15 30 ns
t /t PZH PZL 3-state output enable time nOE to nY see Figs 6 and 7 4.5 − 11 31 ns
t /t PHZ PLZ 3-state output disable time nOE to nY see Figs 6 and 7 4.5 − 11 35 ns
t /t THL TLH output transition time see Figs 5 and 7 4.5 − 6 15 ns
T = −40 to +125 °C amb
t /t PHL PLH propagation delay nA to nY see Figs 5 and 7 4.5 − − 36 ns
t /t PZH PZL 3-state output enable time nOE to nY see Figs 6 and 7 4.5 − − 38 ns
t /t PHZ PLZ 3-state output disable time nOE to nY see Figs 6 and 7 4.5 − − 42 ns
t /t THL TLH output transition time see Figs 5 and 7 4.5 − − 18 ns

Note 1. All typical values are measured at Tamb = 25°C.

AC WAVEFORMS

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S1 VCC

handbook, full pagewidth

open

VCC

GND RL = 1000 Ω

VI

VO

PULSE

D.U.T.

GENERATOR

CL

RT

MNA232

Column 1 Column 2
TEST S 1
t /t PLH PHL open
t /t PLZ PZL V CC
t /t PHZ PZH GND

Definitions for test circuit: CL = Load capacitance including jig and probe capacitance (see “AC characteristics” for values). RL = Load resistance (see “AC characteristics” for values). RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.

Fig.7 Load circuitry for switching times.

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PACKAGE OUTLINES

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm

SOT505-2

D

E

A X

c

HE

v M A

y

Z

5

8

A2 A

(A3)

A1

pin 1 index

θ Lp L

1

4

detail X

w M

e bp

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ
mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.5 0.47 0.33 0.2 0.13 0.1 0.70 0.35 8° 0°

Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

02-01-16

SOT505-2

  • - -

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VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm

SOT765-1

D

E

A X

c

y

HE

v M A

Z

5

8

Q

A2 A A1

(A3)

pin 1 index

θ Lp L

1

4

detail X

e

w M bp

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ
mm 1 0.15 0 0.00 0 .85 .60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.40 0.15 0.21 0.19 0.2 0.13 0.1 0.4 0.1 8° 0°

Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

02-06-07

SOT765-1

MO-187

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SOLDERING

Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.

Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferably be kept:

  • below 220 °C for all the BGA packages and packages with a thickness ≥ 2.5mm and packages with a thickness <2.5 mm and a volume ≥350 mm3 so called thick/large packages
  • below 235 °C for packages with a thickness <2.5 mm and a volume <350 mm3 so called small/thin packages.

Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.

If wave soldering is used the following conditions must be observed for optimal results:

  • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.
  • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.

  • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.

Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.

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Suitability of surface mount IC packages for wave and reflow soldering methods

Column 1 Column 2 Column 3
PACKAGE(1) SOLDERING METHOD
WAVE REFLOW(2)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(4), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP not suitable not suitable(3) suitable not recommended(4)(5) not recommended(6) suitable suitable suitable suitable suitable

Notes 1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder

cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than

0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

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DATA SHEET STATUS

Column 1 Column 2 Column 3 Column 4
LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) DEFINITION
I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product.
III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).

Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

DEFINITIONS

Short-form specification  The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition  Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information  Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

DISCLAIMERS

Life support applications  These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes  Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production

(status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

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NOTES

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NOTES

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NOTES

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Philips Semiconductors – a worldwide company

Contact information

For additional information please visit http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.

SCA75

© Koninklijke Philips Electronics N.V. 2003

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

613508/01/pp20

Date of release: 2003 Mar 03

Document order number: 9397 750 10642

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