74HC193 PHILIPS

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Technical content

Product specification File under Integrated Circuits, IC06 December 1990 INTEGRATED CIRCUITS 74HC/HCT193 Presettable synchronous 4-bit binary up/down counter For a complete data sheet, please also download:

  • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
  • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
  • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

Philips Semiconductors Product specification Presettable synchronous 4-bit binary up/down counter 74HC/HCT193

FEATURES

  • Synchronous reversible 4-bit binary counting
  • Asynchronous parallel load
  • Asynchronous reset
  • Expandable without external logic
  • Output capability: standard
  • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT193 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT193 are 4-bit synchronous binary up/down counters. Separate up/down clocks, CP U and CP D respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CP U clock is pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed while CPU is held HIGH, the device will count down. Only one clock input can be held HIGH at any time, or erroneous operation will result. The device can be cleared at any time by the asynchronous master reset input (MR); it may also be loaded in parallel by activating the asynchronous parallel load input ( PL). The “193” contains four master-slave JK flip-flops with the necessary steering logic to provide the asynchronous reset, load, and synchronous count up and count down functions. Each flip-flop contains JK feedback from slave to master, such that a LOW-to-HIGH transition on the CP D input will decrease the count by one, while a similar transition on the CP U input will advance the count by one. One clock should be held HIGH while counting with the other, otherwise the circuit will either count by two’s or not at all, depending on the state of the first flip-flop, which cannot toggle as long as either clock input is LOW. Applications requiring reversible operation must make the reversing decision while the activating clock is HIGH to avoid erroneous counts. The terminal count up ( TC U ) and terminal count down (TC D ) outputs are normally HIGH. When the circuit has reached the maximum count state of 15, the next HIGH-to-LOW transition of CP U will causeTC U to go LOW. TC U will stay LOW until CPU goes HIGH again, duplicating the count up clock. Likewise, theTC D output will go LOW when the circuit is in the zero state and the CPD goes LOW. The terminal count outputs can be used as the clock input signals to the next higher order circuit in a multistage counter, since they duplicate the clock waveforms. Multistage counters will not be fully synchronous, since there is a slight delay time difference added for each stage that is added. The counter may be preset by the asynchronous parallel load capability of the circuit. Information present on the parallel data inputs (D 0 to D3) is loaded into the counter and appears on the outputs (Q0 to Q3) regardless of the conditions of the clock inputs when the parallel load PL) input is LOW. A HIGH level on the master reset (MR) input will disable the parallel load gates, override both clock inputs and set all outputs (Q 0 to Q3) LOW. If one of the clock inputs is LOW during and after a reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted as a legitimate signal and will be counted.

Philips Semiconductors Product specification Presettable synchronous 4-bit binary up/down counter 74HC/HCT193 QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf= 6 ns Notes 1. C PD is used to determine the dynamic power dissipation (PD inµW): PD = CPD × VCC 2 × fi+∑ (CL × VCC 2 × fo) where: fi= input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC 2 × fo) = sum of outputs C L = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI= GND to VCC For HCT the condition is VI= GND to VCC − 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC HCT tPHL / tPLH propagation delay CPD , CPU to Qn C L = 15 pF; VCC = 5 V 20 20 ns fmax maximum clock frequency 45 47 MHz C I input capacitance 3.5 3.5 pF C PD power dissipation capacitance per package notes 1 and 2 24 26 pF

Philips Semiconductors Product specification Presettable synchronous 4-bit binary up/down counter 74HC/HCT193 PIN DESCRIPTION Note 1. LOW-to-HIGH, edge triggered PIN NO. SYMBOL NAME AND FUNCTION 3, 2, 6, 7 Q 0 to Q3 flip-flop outputs 4C P D count down clock input(1) 5C P U count up clock input(1)

8 GND ground (0 V)

PL asynchronous parallel load input (active LOW)

12 TC U terminal count up (carry) output (active LOW)

13 TC D terminal count down (borrow) output (active LOW)

14 MR asynchronous master reset input (active HIGH)

15, 1, 10, 9 D 0 to D3 data inputs

16 V CC positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

Philips Semiconductors Product specification Presettable synchronous 4-bit binary up/down counter 74HC/HCT193 FUNCTION TABLE Notes 1. H = HIGH voltage level L = LOW voltage level X = don’t care ↑ = LOW-to-HIGH clock transition TC U =C PU at terminal count up (HHHH) 3. TC D =C PD at terminal count down (LLLL) OPERATING MODE INPUTS OUTPUTS MR PL CP U CP D D 0 D 1 D 2 D 3 Q 0 Q 1 Q 2 Q 3 TC U TC D reset (clear) H H X X X X L H X X X X X X X X L L L L L L L L H H L H parallel load L L L L L L L L X X L H L H X X L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H H H L H L H H H count up L H ↑ H X X X X count up H (2) H count down L H H ↑ X X X X count down H H (3) Fig.4 Functional diagram.

Philips Semiconductors Product specification Presettable synchronous 4-bit binary up/down counter 74HC/HCT193 Fig.5 Typical clear, load and count sequence. (1) Clear overrides load, data and count inputs. (2) When counting up the count down clock input (CPD ) must be HIGH, when counting down the count up clock input (CP U ) must be HIGH. Sequence Clear (reset outputs to zero); load (preset) to binary thirteen; count up to fourteen, fifteen, terminal count up, zero, one and two; count down to one, zero, terminal count down, fifteen, Fig.6 Logic diagram.

Philips Semiconductors Product specification Presettable synchronous 4-bit binary up/down counter 74HC/HCT193 DC CHARACTERISTICS FOR 74HC For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf= 6 ns; CL = 50 pF SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HC VCC (V) WAVEFORMS +25 −40 to+85 −40 to+125 tPHL / tPLH propagation delay CP U ,C PD to Qn 215 270 325 ns 2.0 4.5 6.0 Fig.7 t PHL / tPLH propagation delay CP U toTC U 125 155 190 ns 2.0 4.5 6.0 Fig.8 t PHL / tPLH propagation delay CP D toTC D 125 155 190 ns 2.0 4.5 6.0 Fig.8 t PHL / tPLH propagation delay PL to Qn 220 275 330 ns 2.0 4.5 6.0 Fig.9 t PHL propagation delay MR to Qn 200 250 300 ns 2.0 4.5 6.0 Fig.10 t PHL / tPLH propagation delay D n to Qn 210 265 315 ns 2.0 4.5 6.0 Fig.9 t PHL / tPLH propagation delay PL toTC U ,PL toTC D 290 365 435 ns 2.0 4.5 6.0 Fig.12 t PHL / tPLH propagation delay MR to TC U ,M Rt oTC D 285 355 430 ns 2.0 4.5 6.0 Fig.12 t PHL / tPLH propagation delay D n toTC U ,D n toTC D 290 365 435 ns 2.0 4.5 6.0 Fig.12 t THL / tTLH output transition time 19 110 ns 2.0 4.5 6.0 Fig.10 t W up, down clock pulse width HIGH or LOW 100 125 150 ns 2.0 4.5 6.0 Fig.7

Philips Semiconductors Product specification Presettable synchronous 4-bit binary up/down counter 74HC/HCT193 tW master reset pulse width HIGH 100 125 150 ns 2.0 4.5 6.0 Fig.10 t W parallel load pulse width LOW 100 125 150 ns 2.0 4.5 6.0 Fig.9 t rem removal time PL to CPU ,C PD ns 2.0 4.5 6.0 Fig.9 t rem removal time MR to CPU ,C PD ns 2.0 4.5 6.0 Fig.10 t su set-up time D n toPL 100 120 ns 2.0 4.5 6.0 Fig.11 note: CP U = CPD = HIGH th hold time D n toPL −14 ns 2.0 4.5 6.0 Fig.11 t h hold time CP U to CPD , CP D to CPU 100 120 ns 2.0 4.5 6.0 Fig.13 f max maximum up, down clock pulse frequency 4.0 13.5 3.2 2.6 MHz 2.0 4.5 6.0 Fig.7 SYMBOL PARAMETER T amb (°C) UNIT TEST CONDITIONS 74HC VCC (V) WAVEFORMS +25 −40 to+85 −40 to+125

Philips Semiconductors Product specification Presettable synchronous 4-bit binary up/down counter 74HC/HCT193 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (ΔICC ) for a unit load of 1 is given in the family specifications. To determineΔICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT D n CP U ,C PD PL MR 0.35 1.40 0.65 1.05

Philips Semiconductors Product specification Presettable synchronous 4-bit binary up/down counter 74HC/HCT193 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf= 6 ns; CL = 50 pF SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HCT VCC (V) WAVEFORMS +25 −40 to+85 −40 to+125 tPHL / tPLH propagation delay CP U ,C PD to Qn 23 43 54 65 ns 4.5 Fig.7 tPHL / tPLH propagation delay CP U toTC U 15 27 34 41 ns 4.5 Fig.8 tPHL / tPLH propagation delay CP D toTC D 15 27 34 41 ns 4.5 Fig.8 tPHL / tPLH propagation delay PL to Qn 26 46 58 69 ns 4.5 Fig.9 tPHL propagation delay MR to Qn 22 40 50 60 ns 4.5 Fig.10 tPHL / tPLH propagation delay D n to Qn 27 46 58 69 ns 4.5 Fig.9 tPHL / tPLH propagation delay PL toTC U ,PL toTC D 31 55 69 83 ns 4.5 Fig.12 tPHL / tPLH propagation delay MR to TC U , MR toTC D 29 55 69 83 ns 4.5 Fig.12 tPHL / tPLH propagation delay D n toTC U ,D n toTC D 32 58 73 87 ns 4.5 Fig.12 tTHL / tTLH output transition time 7 15 19 22 ns 4.5 Fig.10 tW up, down clock pulse width HIGH or LOW 25 11 31 38 ns 4.5 Fig.7 tW master reset pulse width HIGH 20 7 25 30 ns 4.5 Fig.10 tW parallel load pulse width LOW 20 8 25 30 ns 4.5 Fig.9 trem removal time PL to CPU ,C PD 10 2 13 15 ns 4.5 Fig.9 trem removal time MR to CPU ,C PD 10 0 13 15 ns 4.5 Fig.10 tsu set-up time D n toPL 16 8 20 24 ns 4.5 Fig.11 note: CP U =C PD = HIGH th hold time D n toPL 0 −6 0 0 ns 4.5 Fig.11 th hold time CP U to CPD ,C PD to CPU 16 7 20 24 ns 4.5 Fig.13 fmax maximum up, down clock pulse frequency 20 43 16 13 MHz 4.5 Fig.7

Philips Semiconductors Product specification Presettable synchronous 4-bit binary up/down counter 74HC/HCT193 AC WAVEFORMS Fig.7 Waveforms showing the clock (CPU , CPD ) to output (Qn) propagation delays, the clock pulse width, and the maximum clock pulse frequency. (1) HC : VM = 50%; VI= GND to VCC . HCT: VM = 1.3V; VI= GND to 3 V. Fig.8 Waveforms showing the clock (CPU ,C PD ) to terminal count output (TC U ,TC D ) propagation delays. (1) HC : VM = 50%; VI= GND to VCC . HCT: VM = 1.3V; VI= GND to 3 V. Fig.9 Waveforms showing the parallel load input (PL) and data (Dn) to Qn output propagation delays and PL removal time to clock input (CPU ,C PD ). (1) HC : VM = 50%; VI= GND to VCC . HCT: VM = 1.3V; VI= GND to 3 V.

Philips Semiconductors Product specification Presettable synchronous 4-bit binary up/down counter 74HC/HCT193 Fig.10 Waveforms showing the master reset input (MR) pulse width, MR to Qn propagation delays, MR to CPU , CP D removal time and output transition times. (1) HC : VM = 50%; VI= GND to VCC . HCT: VM = 1.3V; VI= GND to 3 V. Fig.11 Waveforms showing the data input (Dn) to parallel load input (PL) set-up and hold times. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : V M = 50%; VI= GND to VCC . HCT: VM = 1.3V; VI= GND to 3 V. Fig.12 Waveforms showing the data input (Dn), parallel load input (PL) and the master reset input (MR) to the terminal count outputs (TC U ,TC D ) propagation delays. (1) HC : VM = 50%; VI= GND to VCC . HCT: VM = 1.3V; VI= GND to 3 V. Fig.13 Waveforms showing the CPU to CPD or CPD to CPU hold times. (1) HC : VM = 50%; VI= GND to VCC . HCT: VM = 1.3V; VI= GND to 3 V.

Philips Semiconductors Product specification Presettable synchronous 4-bit binary up/down counter 74HC/HCT193

APPLICATION INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. Fig.14 Cascaded up/down counter with parallel load.