74HCT190D

74HC190 PHILIPS

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Technical content

Product specification File under Integrated Circuits, IC06 December 1990 INTEGRATED CIRCUITS 74HC/HCT190 Presettable synchronous BCD decade up/down counter For a complete data sheet, please also download:

• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

Philips Semiconductors Product specification Presettable synchronous BCD decade up/down counter 74HC/HCT190

FEATURES

• Synchronous reversible counting
• Asynchronous parallel load
• Count enable control for synchronous expansion
• Single up/down control input
• Output capability: standard
• ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT190 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT190 are asynchronously presettable up/down BCD decade counters. They contain four master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operation. Asynchronous parallel load capability permits the counter to be preset to any desired number. Information present on the parallel data inputs (D 0 to D3) is loaded into the counter and appears on the outputs when the parallel load (PL) input is LOW. As indicated in the function table, this operation overrides the counting function. Counting is inhibited by a HIGH level on the count enable CE) input. WhenCE is LOW internal state changes are initiated synchronously by the LOW-to-HIGH transition of the clock input. The up/down ( U/D) input signal determines the direction of counting as indicated in the function table. The CE input may go LOW when the clock is in either state, however, the LOW-to-HIGHCE transition must occur only when the clock is HIGH. Also, theU/D input should be changed only when eitherCE or CP is HIGH. Overflow/underflow indications are provided by two types of outputs, the terminal count (TC) and ripple clock (RC). The TC output is normally LOW and goes HIGH when a circuit reaches zero in the count-down mode or reaches “9” in the count-up-mode. The TC output will remain HIGH until a state change occurs, either by counting or presetting, or until U/D is changed. Do not use the TC output as a clock signal because it is subject to decoding spikes. The TC signal is used internally to enable the RC output. When TC is HIGH andCE is LOW, theRC output follows the clock pulse (CP). This feature simplifies the design of multistage counters as shown in Figs 5 and 6. In Fig.5, each RC output is used as the clock input to the next higher stage. It is only necessary to inhibit the first stage to prevent counting in all stages, since a HIGH on CE inhibits theRC output pulse as indicated in the function table. The timing skew between state changes in the first and last stages is represented by the cumulative delay of the clock as it ripples through the preceding stages. This can be a disadvantage of this configuration in some applications. Fig.6 shows a method of causing state changes to occur simultaneously in all stages. The RC outputs propagate the carry/borrow signals in ripple fashion and all clock inputs are driven in parallel. In this configuration the duration of the clock LOW state must be long enough to allow the negative-going edge of the carry/borrow signal to ripple through to the last stage before the clock goes HIGH. Since the RC output of any package goes HIGH shortly after its CP input goes HIGH there is no such restriction on the HIGH-state duration of the clock. In Fig.7, the configuration shown avoids ripple delays and their associated restrictions. Combining the TC signals from all the preceding stages forms the CE input for a given stage. An enable must be included in each carry gate in order to inhibit counting. The TC output of a given stage it not affected by its own CE signal therefore the simple inhibit scheme of Figs 5 and 6 does not apply.

Philips Semiconductors Product specification Presettable synchronous BCD decade up/down counter 74HC/HCT190 QUICK REFERENCE DATA GND = 0 V; Tamb =2 5°C; tr =tf= 6 ns Notes 1. C PD is used to determine the dynamic power dissipation (PD inµW): PD =C PD × VCC 2 × fi+ ∑ (CL × VCC 2 ×fo) where: fi= input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC 2 × fo) = sum of outputs C L = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI= GND to VCC For HCT the condition is VI= GND to VCC − 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC HCT tPHL / tPLH propagation delay CP to Qn C L = 15 pF; VCC = 5 V 2 22 4n s fmax maximum clock frequency 28 30 MHz C I input capacitance 3.5 3.5 pF C PD power dissipation capacitance per flip-flop notes 1 and 2 36 38 pF

Philips Semiconductors Product specification Presettable synchronous BCD decade up/down counter 74HC/HCT190 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 3, 2, 6, 7 Q 0 to Q3 flip-flop outputs

4 CE count enable input (active LOW)

5 U/D up/down input

8 GND ground (0 V)

PL parallel load input (active LOW)

12 TC terminal count output

RC ripple clock output (active LOW)

14 CP clock input (LOW-to-HIGH, edge-triggered)

15, 1, 10, 9 D 0 to D3 data inputs

16 V CC positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

Philips Semiconductors Product specification Presettable synchronous BCD decade up/down counter 74HC/HCT190 FUNCTION TABLE TC AND RC FUNCTION TABLE Notes 1. H = HIGH voltage level L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition X = don’t care ↑ = LOW-to-HIGH CP transition = one LOW level pulse = TC goes LOW on a LOW-to-HIGH CP transition OPERATING MODE INPUTS OUTPUTS PL U/D CE CP D n Q n parallel load L L X X X X X X L H L H count up H L I ↑ X count up count down H H I ↑ X count down hold (do nothing) H X H X X no change INPUTS TERMINAL COUNT STATE OUTPUTS U/D CE CP Q 0 Q 1 Q 2 Q 3 TC RC HHX H X X H L H LHX H X XH H H LL H X XH LHX L L L L L H HHX L L L L H H HL L L L L Fig.4 Functional diagram.

Philips Semiconductors Product specification Presettable synchronous BCD decade up/down counter 74HC/HCT190 Fig.5 N-stage ripple counter using ripple clock. Fig.6 Synchronous n-stage counter using ripple carry/borrow. Fig.7 Synchronous n-stage counter with parallel gated carry/borrow.

Philips Semiconductors Product specification Presettable synchronous BCD decade up/down counter 74HC/HCT190 Fig.8 Typical load, count and inhibit sequence. Sequence Load (present) to BCD seven; count up to eight, nine, zero, one and two; inhibit; count down to one, zero, nine, eight and seven. Fig.9 Logic diagram.

Philips Semiconductors Product specification Presettable synchronous BCD decade up/down counter 74HC/HCT190 DC CHARACTERISTICS FOR 74HC For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr =tf= 6 ns; CL = 50 pF SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HC VCC (V) WAVEFORMS +25 −40 TO +85 −40 TO +125 tPHL / tPLH propagation delay CP to Qn 220 275 330 ns 2.0 4.5 6.0 Fig.10 t PHL / tPLH propagation delay CP to TC 255 320 385 ns 2.0 4.5 6.0 Fig.10 t PHL / tPLH propagation delay CP toRC 150 190 225 ns 2.0 4.5 6.0 Fig.11 t PHL / tPLH propagation delay CE toRC 130 165 195 ns 2.0 4.5 6.0 Fig.11 t PHL / tPLH propagation delay D n to Qn 220 275 330 ns 2.0 4.5 6.0 Fig.12 t PHL / tPLH propagation delay PL to Qn 220 275 330 ns 2.0 4.5 6.0 Fig.13 t PHL / tPLH propagation delay U/D to TC 190 240 285 ns 2.0 4.5 6.0 Fig.14 t PHL / tPLH propagation delay U/D toRC 210 265 315 ns 2.0 4.5 6.0 Fig.14 t THL / tTLH output transition time 19 110 ns 2.0 4.5 6.0 Fig.15 t W clock pulse width HIGH or LOW 155 195 235 ns 2.0 4.5 6.0 Fig.10 t W parallel load pulse width LOW 100 125 150 ns 2.0 4.5 6.0 Fig.15

Philips Semiconductors Product specification Presettable synchronous BCD decade up/down counter 74HC/HCT190 trem removal time PL to CP ns 2.0 4.5 6.0 Fig.15 t su set-up time U/D to CP 205 255 310 ns 2.0 4.5 6.0 Fig.17 t su set-up time D n toPL 100 125 150 ns 2.0 4.5 6.0 Fig.16 t su set-up time CE to CP 140 175 210 ns 2.0 4.5 6.0 Fig.17 t h hold time U/D to CP −44 −16 −13 ns 2.0 4.5 6.0 Fig.17 t h hold time D n toPL −14 ns 2.0 4.5 6.0 Fig.16 t h hold time CE to CP −19 ns 2.0 4.5 6.0 Fig.17 f max maximum clock pulse frequency 3.0 8.3 2.4 2.0 MHz 2.0 4.5 6.0 Fig.10 SYMBOL PARAMETER T amb (°C) UNIT TEST CONDITIONS 74HC VCC (V) WAVEFORMS +25 −40 TO +85 −40 TO +125

Philips Semiconductors Product specification Presettable synchronous BCD decade up/down counter 74HC/HCT190 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (ΔICC ) for a unit load of 1 is given in the family specifications. To determineΔICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT D n CP U/D CE, PL 0.5 0.65 1.15 1.5

Philips Semiconductors Product specification Presettable synchronous BCD decade up/down counter 74HC/HCT190 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr =tf= 6 ns; CL = 50 pF SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HCT VCC (V) WAVEFORMS +25 −40 to+85 −40 to+125 tPHL / tPLH propagation delay CP to Qn 28 48 60 72 ns 4.5 Fig.10 tPHL / tPLH propagation delay CP to TC 34 58 73 87 ns 4.5 Fig.10 tPHL / tPLH propagation delay CP toRC 20 35 44 53 ns 4.5 Fig.11 tPHL / tPLH propagation delay CE toRC 18 33 41 50 ns 4.5 Fig.11 tPHL / tPLH propagation delay D n to Qn 24 44 55 66 ns 4.5 Fig.12 tPHL / tPLH propagation delay PL to Qn 29 49 61 74 ns 4.5 Fig.13 tPHL / tPLH propagation delay U/D to TC 24 45 56 68 ns 4.5 Fig.14 tPHL / tPLH propagation delay U/D toRC 26 45 56 68 ns 4.5 Fig.14 tTHL / tTLH output transition time 7 15 19 22 ns 4.5 Fig.15 tW clock pulse width HIGH or LOW 25 10 31 38 ns 4.5 Fig.10 tW parallel load pulse width LOW 22 12 28 33 ns 4.5 Fig.15 trem removal time PL to CP 7 1 9 11 ns 4.5 Fig.15 tsu set-up time U/D to CP 42 25 53 63 ns 4.5 Fig.17 tsu set-up time D n toPL 20 10 25 30 ns 4.5 Fig.16 tsu set-up time CE to CP 31 18 39 47 ns 4.5 Fig.17 th hold time U/D to CP 0 −18 0 0 ns 4.5 Fig.17 th hold time D n toPL 0 −6 0 0 ns 4.5 Fig.16 th hold time CE to CP 0 −10 0 0 ns 4.5 Fig.17 fmax maximum clock pulse frequency 16 27 13 11 MHz 4.5 Fig.10

Philips Semiconductors Product specification Presettable synchronous BCD decade up/down counter 74HC/HCT190 AC WAVEFORMS Fig.10 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width and the maximum clock pulse frequency. (1) HC : VM = 50%; VI= GND to VCC . HCT : VM = 1.3 V; VI= GND to 3 V. Fig.11 Waveforms showing the clock and count enable inputs (CP,CE) to ripple clock output (RC) propagation delays. (1) HC : VM = 50%; VI= GND to VCC . HCT : VM = 1.3 V; VI= GND to 3 V. Fig.12 Waveforms showing the input (Dn) to output (Qn) propagation delays. (1) HC : VM = 50%; VI= GND to VCC . HCT : VM = 1.3 V; VI= GND to 3 V. Fig.13 Waveforms showing the input (PL) to output (Qn) propagation delays. (1) HC : VM = 50%; VI= GND to VCC . HCT : VM = 1.3 V; VI= GND to 3 V. Fig.14 Waveforms showing the up/down count input (U/D) to terminal count and ripple clock output (TC,RC) propagation delays. (1) HC : VM = 50%; VI= GND to VCC . HCT : VM = 1.3 V; VI= GND to 3 V. Fig.15 Waveforms showing the parallel load input (PL) pulse width, removal time to clock (CP) and the output (Qn) transition times. (1) HC : VM = 50%; VI= GND to VCC . HCT : VM = 1.3 V; VI= GND to 3V .

Philips Semiconductors Product specification Presettable synchronous BCD decade up/down counter 74HC/HCT190 PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. Fig.16 Waveforms showing the set-up and hold times from the parallel load input (PL) to the data input (Dn). The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : V M = 50%; VI= GND to VCC . HCT : VM = 1.3 V; VI= GND to 3 V. Fig.17 Waveforms showing the set-up and hold times from the count enable and up/down inputs (CE, U/D) to the clock (CP). The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : V M = 50%; VI= GND to VCC . HCT : VM = 1.3 V; VI= GND to 3 V.