74HCT165DB Datasheet PDF & Specifications

Manufacturer specification

1 manufacturers / 2 documents

Compare all 1 manufacturer specifications

Manufacturer	Series	Package	Documents	Available	Select specification
NXP Semiconductors	-	-	2	PDF HTML	Viewing

Online Datasheet

Read the NXP Semiconductors document online.

74HC165 NXP

Document overview

Manufacturer or author: Provided By digicamel.com
PDF pages: 22

Technical content

General description The 74HC165; 74HCT165 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL). The 74HC165; 74HCT165 are 8-bit parallel-load or serial-in shift registers with complementary serial outputs (Q7 andQ7) available from the last stage. When the parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the register asynchronously. When PL is HIGH, data enters the register serially at the DS input and shifts one place to the right (Q0→ Q1 → Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the succeeding stage. The clock input is a gated-OR structure which allows one input to be used as an active LOW clock enable ( CE) input. The pin assignment for the CP andCE inputs is arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of inputCE should only take place while CP HIGH for predictable operation. Either the CP or theCE should be HIGH before the LOW-to-HIGH transition ofPL to prevent shifting the data when PL is activated. 2. Features n Asynchronous 8-bit parallel load n Synchronous serial input n Complies with JEDEC standard no. 7A n ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V n Speciﬁed from−40 °Ct o+ 8 5°C and from−40 °C to +125°C 3. Applications n Parallel-to-serial data conversion 74HC165; 74HCT165 8-bit parallel-in/serial out shift register Rev. 03 — 14 March 2008 Product data sheet

1 C3/

74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 14 March 2008 3 of 22 NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register 6. Pinning information

6.1 Pinning

Fig 3. Functional diagram mna992 8-BIT SHIFT REGISTER PARALLEL-IN/SERIAL-OUT PL DS10 CP2 D0 D1 D2 D3 D4 D5 D6 D7 12 13 14 3 4 5 6 CE15 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as supply pin or input. Fig 4. Pin conﬁguration (DIP16, SO16 and (T)SSOP16) Fig 5. Pin conﬁguration (DHVQFN16) 74HC165 74HCT165 PL V CC CP CE D4 D3 D5 D2 D6 D1 D7 D0 Q7 DS GND Q7 001aah564 001aah565 74HC165 74HCT165 Q7 DS GND (1)D7 D0 D6 D1 D5 D2 D4 D3 CP CE GND PL VCC Transparent top view 7 10 6 11 5 12 4 13 3 14 2 15 terminal 1 index area

6.2 Pin description

↑ = LOW-to-HIGH clock transition. Table 2. Pin description Table 3. Function table[1]

74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] Ptot derates linearly with 12 mW/K above 70°C. [3] Ptot derates linearly with 8 mW/K above 70°C. [4] Ptot derates linearly with 5.5 mW/K above 60°C. [5] Ptot derates linearly with 4.5 mW/K above 60°C.

Recommended operating conditions

Table 4. Limiting values …continued Table 5. Recommended operating conditions Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. [1] tpd is the same as tPHL and tPLH . [2] tt is the same as tTHL and tTLH . [3] C PD is used to determine the dynamic power dissipation (PD inµW). Measurement points are given inTable8. VOL and VOH are typical voltage output levels that occur with the output load.

74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 14 March 2008 12 of 22 NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register Measurement points are given inTable8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. The parallel load (PL) pulse width, the parallel load to output (Q7 orQ7) propagation delays, the parallel load to clock (CP) and clock enable (CE) recovery time mna988 PL input CE, CP input Q7 or Q7 output tPHL tW trec VM VOH VI GND VI GND VOL VM VM Measurement points are given inTable8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 9. The data input (D7) to output (Q7 orQ7) propagation delays whenPL is LOW mna989 D7 input Q7 output Q7 output tPHL tPHL VM VOH VI GND VOH VOL VOL VM tPLH tPLH VM

74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. Measurement points are given inTable8. VOL and VOH are typical voltage output levels that occur with the output load. (1) CE may change only from HIGH-to-LOW while CP is LOW, seeSection1. Measurement points are given inTable8. VOL and VOH are typical voltage output levels that occur with the output load. Table 8. Measurement points

74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. Test data is given inTable9. T = Termination resistance should be equal to output impedance Zo of the pulse generator. C L = Load capacitance including jig and probe capacitance. Table 9. Test data

74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 14 March 2008 15 of 22 NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register 13. Package outline Fig 13. Package outline SOT38-4 (DIP16) REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA SOT38-4 95-01-14 03-02-13 M H c (e )1 M E A L seating plane w M e D A 2 Z E pin 1 index b 0 5 10 mm scale Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. UNIT A max. 12 b1 (1) (1) (1) b2 cD E e M ZHL mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) A min. A max. b max.wM Ee1 1.73 1.30 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 3.60 7.80 10.0 inches 0.068 0.051 0.021 0.015 0.014 0.009 1.25 0.85 0.049 0.033 0.77 0.73 0.26 0.24 0.14 0.31 0.39 DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 14 March 2008 16 of 22 NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register Fig 14. Package outline SOT109-1 (SO16) X w M q AA 1 A 2 bp D H E Lp Q detail X E Z e c L v M A (A )3 A y pin 1 index UNIT A max. A 1 A 2 A 3 bp cD (1) E (1) (1)eH E LL p QZ ywv q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 o o 0.25 0.1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 SOT109-1 99-12-27 03-02-19 076E07 MS-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.05 1.05 0.0410.244 0.228 0.028 0.020 0.028 0.0120.01 0.25 0.01 0.0040.039 0.016 0 2.5 5 mm scale SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 14 March 2008 17 of 22 NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register Fig 15. Package outline SOT338-1 (SSOP16) UNIT A 1 A 2 A 3 bp cD (1) E (1) eH E LL p QZ ywv q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 1.257.9 7.6 1.03 0.63 0.9 0.7 1.00 0.55 o o0.130.2 0.1 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. SOT338-1 99-12-27 03-02-19 (1) w M bp D H E E Z e c v M A X A y 1 8 16 9 q AA 1 A 2 Lp Q detail X L (A )3 MO-150 pin 1 index 0 2.5 5 mm scale SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 A max.

74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 14 March 2008 18 of 22 NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register Fig 16. Package outline SOT403-1 (TSSOP16) UNIT A 1 A 2 A 3 bp cD (1) E (2) (1)eH E LL p QZ ywv q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 o o0.13 0.10.21 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 SOT403-1 MO-153 99-12-27 03-02-18 w M bp D Z e 0.25 16 9 q AA 1 A 2 Lp Q detail X L (A )3 H E E c v M A XA y 0 2.5 5 mm scale TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 A max. 1.1 pin 1 index

74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 14 March 2008 19 of 22 NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register Fig 17. Package outline SOT763-1 (DHVQFN16) terminal 1 index area 0.51 A 1 EhbUNIT ye 0.2 c REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 3.6 3.4 D h 2.15 1.85 2.6 2.4 1.15 0.85 2.50.30 0.18 0.05 0.00 0.05 0.1 DIMENSIONS (mm are the original dimensions) 0.5 0.3 L 0.1 v 0.05 w 0 2.5 5 mm scale SOT763-1 DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm A (1) max. A c detail X yy1 Ce L Eh D h e b 15 10 X D E C B A terminal 1 index area AC C Bv M w M E (1) Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. D (1) 02-10-17 03-01-27

The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
Package SOT763-1 (DHVQFN16) added toSection 4 “Ordering information” andSection 13 “Package outline”.
Family data added, seeSection 10 “Static characteristics” 74HC_HCT165_CNV_2 December 1990 Product speciﬁcation - -

74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 14 March 2008 21 of 22 NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register 16. Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Deﬁnitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

16.2 Deﬁnitions

Draft —The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modiﬁcations or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet —A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the full data sheet shall prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes —NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation speciﬁcations and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use —NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications —Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the speciﬁed use without further testing or modiﬁcation. Limiting values —Stress above one or more limiting values (as deﬁned in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale —NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/proﬁle/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conﬂict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license —Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit:http://www.nxp.com For sales ofﬁce addresses, please send an email to:salesaddresses@nxp.com Document status[1][2] Product status[3] Deﬁnition Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development. Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation. Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 14 March 2008 Document identifier: 74HC_HCT165_3 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 18. Contents

Selected Specification

NXP Semiconductors 74HCT165DB overview.

Overview

74HCT165DB is listed in the Logic IC category. Available datasheets include documents from NXP Semiconductors. DigiCamel provides a local PDF and searchable HTML technical text for online reference.

Summary

8-bit parallel-in/serial out shift register Rev. 03-14 March 2008

Description

8-bit parallel-in/serial out shift register Rev. 03-14 March 2008

Source title 74HCT165DB Datasheet(PDF) - NXP Semiconductors

Related Parts

More parts from the same family.

Browse manufacturer