74HC162 PHILIPS

Document overview

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Technical content

Product specification File under Integrated Circuits, IC06 December 1990 INTEGRATED CIRCUITS 74HC/HCT162 Presettable synchronous BCD decade counter; synchronous reset For a complete data sheet, please also download:

  • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
  • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
  • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

Philips Semiconductors Product specification Presettable synchronous BCD decade counter; synchronous reset 74HC/HCT162

FEATURES

  • Synchronous counting and loading
  • Two count enable inputs for n-bit cascading
  • Positive-edge triggered clock
  • Synchronous reset
  • Output capability: standard
  • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT162 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT162 are synchronous presettable decade counters which feature an internal look-ahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q 0 to Q3) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable input ( PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock (providing that the set-up and hold time requirements forPE are met). Preset takes place regardless of the levels at count enable inputs (CEP and CET). For the “162” the clear function is synchronous. A LOW level at the master reset input ( MR) sets all four outputs of the flip-flops (Q0 to Q3) to LOW level after the next positive-going transition on the clock (CP) input (provided that the set-up and hold time requirements for MR are met). This action occurs regardless of the levels at PE, CET and CEP inputs. This synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate. The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH level output of Q 0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula: f max = QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf= 6 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC HCT tPHL propagation delay CP to Qn CP to TC CET to TC C L = 15 pF; VCC =5V 1 9 ns ns ns t PLH propagation delay CP to Qn CP to TC CET to TC ns ns ns f max maximum clock frequency 63 32 MHz C I input capacitance 3.5 3.5 pF C PD power dissipation capacitance per package notes 1 and 2 37 37 pF Notes 1. C PD is used to determine the dynamic power dissipation D inµW): PD = CPD × VCC 2 × fi+ ∑ (CL × VCC 2 × fo) where: fi= input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC 2 × fo) = sum of outputs C L = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI= GND to VCC For HCT the condition is VI= GND to VCC − 1.5 V

Philips Semiconductors Product specification Presettable synchronous BCD decade counter; synchronous reset 74HC/HCT162

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”. PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION

1 MR synchronous master reset (active LOW)

2 CP clock input (LOW-to-HIGH, edge-triggered)

3, 4, 5, 6 D 0 to D3 data inputs

7 CEP count enable input

8 GND ground (0 V)

PE parallel enable input (active LOW)

10 CET count enable carry input

14, 13, 12, 11 Q 0 to Q3 flip-flop outputs

15 TC terminal count output

CC positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

Philips Semiconductors Product specification Presettable synchronous BCD decade counter; synchronous reset 74HC/HCT162 FUNCTION TABLE Notes 1. The TC output is HIGH when CET is HIGH and the counter is at terminal count (HLLH). H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition X = don’t care ↑ = LOW-to-HIGH CP transition OPERATING MODE INPUTS OUTPUTS MR CP CEP CET PE D n Q n TC reset (clear) I ↑ XXX X L L parallel load h h X X X X I I I h L H L (1) count h ↑ h h h X count (1) hold (do nothing) h h X X I X X I h h X X qn qn (1) L Fig.4 Functional diagram.

Philips Semiconductors Product specification Presettable synchronous BCD decade counter; synchronous reset 74HC/HCT162 Fig.5 State diagram. Fig.6 Typical timing sequence: reset outputs to zero; preset to BCD seven; count to eight, nine, zero, one, two and three; inhibit.

Philips Semiconductors Product specification Presettable synchronous BCD decade counter; synchronous reset 74HC/HCT162 Fig.7 Logic diagram.

Philips Semiconductors Product specification Presettable synchronous BCD decade counter; synchronous reset 74HC/HCT162 DC CHARACTERISTICS FOR 74HC For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf= 6 ns; CL = 50 pF SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HC VCC (V) WAVEFORMS +25 −40 to+85 −40 to+125 tPHL / tPLH propagation delay CP to Qn 190 240 285 ns 2.0 4.5 6.0 Fig.8 t PHL / tPLH propagation delay CP to TC 215 270 325 ns 2.0 4.5 6.0 Fig.8 t PHL / tPLH propagation delay CET to TC 150 190 225 ns 2.0 4.5 6.0 Fig.9 t THL / tTLH output transition time 110 ns 2.0 4.5 6.0 Figs 8 and 9 t W clock pulse width HIGH or LOW 100 120 ns 2.0 4.5 6.0 Fig.8 t su set-up time MR, Dn to CP 100 125 150 ns 2.0 4.5 6.0 Figs 9 and 11 t su set-up time PE to CP 135 170 205 ns 2.0 4.5 6.0 Fig.9 t su set-up time CEP, CET to CP 200 250 300 ns 2.0 4.5 6.0 Fig.12 t h hold time D n,PE, CEP, CET, MR to CP −17 ns 2.0 4.5 6.0 Figs 9, 11 and f max maximum clock pulse frequency 6.0 4.8 4.0 MHz 2.0 4.5 6.0 Fig.8

Philips Semiconductors Product specification Presettable synchronous BCD decade counter; synchronous reset 74HC/HCT162 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (ΔICC ) for a unit load of 1 is given in the family specifications. To determineΔICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT MR 0.95 CP 0.80 CEP 0.25 D n 0.25 CET 1.50 PE 0.30

Philips Semiconductors Product specification Presettable synchronous BCD decade counter; synchronous reset 74HC/HCT162 AC CHARACTERISTICS FOR HCT GND = 0 V; tr = tf= 6 ns; CL = 50 pF SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HCT VCC (V) WAVEFORMS+25 −40 to+85 −40 to+125 tPHL / tPLH propagation delay CP to Qn 24 43 54 65 ns 4.5 Fig.8 tPHL propagation delay CP to TC 30 51 64 77 ns 4.5 Fig.8 tPLH propagation delay CP to TC 22 45 56 68 ns 4.5 Fig.8 tPHL propagation delay CET to TC 18 35 44 53 ns 4.5 Fig.9 tPLH propagation delay CET to TC 12 24 30 36 ns 4.5 Fig.9 tTHL / tTLH output transition time 7 15 19 22 ns 4.5 Figs 8 and 9 tW clock pulse width HIGH or LOW 16 7 20 24 ns 4.5 Fig.8 tsu set-up time D n to CP 20 9 25 30 ns 4.5 Fig.9 tsu set-up time PE to CP 35 16 44 53 ns 4.5 Fig.9 tsu set-up time CEP, CET to CP 40 23 50 60 ns 4.5 Fig.12 tsu set-up time MR to CP 20 12 25 30 ns 4.5 Fig.11 th hold time D n,PE, CEP, CET, MR to CP 0 −10 0 0 ns 4.5 Figs 9, 11 and 12 fmax maximum clock pulse frequency 17 29 14 11 MHz 4.5 Fig.8

Philips Semiconductors Product specification Presettable synchronous BCD decade counter; synchronous reset 74HC/HCT162 AC WAVEFORMS Fig.8 Waveforms showing the clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency. (1) HC : VM = 50%; VI= GND to VCC . HCT : VM = 1.3 V; VI= GND to 3 V. Fig.9 Waveforms showing the input (CET) to output (TC) propagation delays and output transition times. (1) HC : VM = 50%; VI= GND to VCC . HCT : VM = 1.3 V; VI= GND to 3 V. Fig.10 Waveforms showing the set-up and hold times for the input (Dn) and parallel enable input (PE). The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : V M = 50%; VI= GND to VCC . HCT : VM = 1.3 V; VI= GND to 3 V.

Philips Semiconductors Product specification Presettable synchronous BCD decade counter; synchronous reset 74HC/HCT162

APPLICATION INFORMATION

The HC/HCT162 facilitate designing counters of any modulus with minimal external logic. The output is glitch-free due to the synchronous reset. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. Fig.11 Waveforms showing theMR set-up and hold times. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI= GND to VCC . HCT : VM = 1.3 V; VI= GND to 3 V. Fig.12 Waveforms showing the CEP and CET set-up and hold times. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : V M = 50%; VI= GND to VCC . HCT : VM = 1.3 V; VI= GND to 3 V. Fig.13 Modulo-5 counter.