74HC138 PHILIPS

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Technical content

Product specification File under Integrated Circuits, IC06 September 1993 INTEGRATED CIRCUITS 74HC/HCT138 3-to-8 line decoder/demultiplexer; inverting For a complete data sheet, please also download:

  • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
  • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
  • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138

FEATURES

  • Demultiplexing capability
  • Multiple input enable for easy expansion
  • Ideal for memory chip select decoding
  • Active LOW mutually exclusive outputs
  • Output capability: standard
  • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT138 decoders accept three binary weighted address inputs (A 0, A1, A2) and when enabled, provide 8 mutually exclusive active LOW outputs (Y0 to Y7). The “138” features three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output will be HIGH unlessE1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the “138” to a 1-of-32 (5 lines to 32 lines) decoder with just four “138” ICs and one inverter. The ”138” can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW state. The ”138” is identical to the “238” but has inverting outputs. QUICK REFERENCE DATA GND = 0 V; T amb = 25°C; tr = tf= 6 ns Notes 1. C PD is used to determine the dynamic power dissipation (PD inµW): PD = CPD × VCC 2 × fi+∑ (CL × VCC 2 × fo) where: fi= input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC 2 × fo) = sum of outputs C L = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI= GND to VCC For HCT the condition is VI= GND to VCC − 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC HCT propagation delay C L = 15 pF; VCC = 5 V tPHL / tPLH An toYn 12 17 ns tPHL / tPLH E3 toYn En toYn 14 19 ns C I input capacitance 3.5 3.5 pF C PD power dissipation capacitance per package notes 1 and 2 67 67 pF

Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 2, 3 A 0 to A2 address inputs 4, 5 E1,E2 enable inputs (active LOW) 6E 3 enable input (active HIGH)

8 GND ground (0 V)

15, 14, 13, 12, 11, 10, 9, 7 Y0 toY7 outputs (active LOW)

16 V CC positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. handbook, halfpage MLB312 A 0 A 1 A 2 Y 0 Y 1 Y 2 Y 3 Y 4 Y 5 Y 6 Y 7 E 1 E 2 E 3 Fig.3 IEC logic symbol. (a) (b) Fig.4 Functional diagram.

Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138 FUNCTION TABLE Notes 1. H = HIGH voltage level L = LOW voltage level X = don’t care INPUTS OUTPUTS E1 E2 E3 A 0 A 1 A 2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 H X X X H X X X L X X X X X X X X X H H H H H H H H H H H H H H H H H H H H H H H H L L L L L L L L H H H H L H L H L L H H L L L L L H H H H L H H H H L H H H H L H H H H H H H H H H H H H H H H L L L L L L L L H H H H L H L H L L H H H H H H H H H H H H H H H H H H H H H H L H H H H L H H H H L H H H H L Fig.5 Logic diagram.

Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138 DC CHARACTERISTICS FOR 74HC For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf= 6 ns; CL = 50 pF SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HC VCC (V) WAVEFORMS +25 −40 to+85 −40 to+125 tPHL / tPLH propagation delay An toYn 150 190 225 ns 2.0 4.5 6.0 Fig.6 t PHL / tPLH propagation delay E3 toYn 150 190 225 ns 2.0 4.5 6.0 Fig.6 t PHL / tPLH propagation delay En toYn 150 190 225 ns 2.0 4.5 6.0 Fig.7 t THL / tTLH output transition time 110 ns 2.0 4.5 6.0 Figs 6 and 7

Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (ΔICC ) for a unit load of 1 is given in the family specifications. To determineΔICC per input, multiply this value by the unit load coefficient shown in the table below. AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf= 6 ns; CL = 50 pF INPUT UNIT LOAD COEFFICIENT An 1.50 En 1.25 E3 1.00 SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HCT VCC (V) WAVEFORMS +25 −40 to+85 −40 to+125 tPHL / tPLH propagation delay An toYn 20 35 44 53 ns 4.5 Fig.6 tPHL / tPLH propagation delay E3 toYn 18 40 50 60 ns 4.5 Fig.6 tPHL / tPLH propagation delay En toYn 19 40 50 60 ns 4.5 Fig.7 tTHL / tTLH output transition time 7 15 19 22 ns 4.5 Figs 6 and 7

Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138 AC WAVEFORMS PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. Fig.6 Waveforms showing the address input (An) and enable input (E3) to output (Yn) propagation delays and the output transition times. (1) HC : VM = 50%; VI= GND to VCC . HCT: VM = 1.3 V; VI= GND to 3 V. Fig.7 Waveforms showing the enable input (En) to output (Yn) propagation delays and the output transition times. (1) HC : VM = 50%; VI= GND to VCC . HCT: VM = 1.3 V; VI= GND to 3 V.