74HC11 PHILIPS

Document overview

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Technical content

Product specification File under Integrated Circuits, IC06 December 1990 INTEGRATED CIRCUITS 74HC/HCT11 Triple 3-input AND gate For a complete data sheet, please also download:

  • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
  • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
  • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

Philips Semiconductors Product specification Triple 3-input AND gate 74HC/HCT11

FEATURES

  • Output capability: standard
  • ICC category: SSI GENERAL DESCRIPTION The 74HC/HCT11 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT11 provide the 3-input AND function. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf= 6 ns Notes 1. C PD is used to determine the dynamic power dissipation (PD inµW): PD = CPD × VCC 2 × fi+ ∑ (CL × VCC 2 × fo) where: fi= input frequency in MHz fo = output frequency in MHz C L = output load capacitance in pF VCC = supply voltage in V ∑ (CL × VCC 2 × fo) = sum of outputs 2. For HC the condition is VI= GND to VCC For HCT the condition is VI= GND to VCC − 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC HCT tPHL / tPLH propagation delay nA, nB, nC to nY CL = 15 pF; VCC = 5 V 10 11 ns C I input capacitance 3.5 3.5 pF C PD power dissipation capacitance per gate notes 1 and 2 18 20 pF

Philips Semiconductors Product specification Triple 3-input AND gate 74HC/HCT11 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 3, 9 1A to 3A data inputs 2, 4, 10 1B to 3B data inputs

7 GND ground (0 V)

12, 6, 8 1Y to 3Y data outputs 13, 5, 11 1C to 3C data inputs 14 V CC positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. Fig.4 Functional diagram. Fig.5 Logic diagram (one gate). FUNCTION TABLE Notes 1. H = HIGH voltage level L = LOW voltage level INPUTS OUTPUT nA nB nC nY LLL L LLH L LHL L LHH L HLL L HLH L HHL L HHH H

Philips Semiconductors Product specification Triple 3-input AND gate 74HC/HCT11 DC CHARACTERISTICS FOR 74HC For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: SSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf= 6 ns; CL = 50 pF SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HC VCC (V) WAVEFORMS+25 −40 to +85 −40 to +125 tPHL / tPLH propagation delay nA, nB, nC to nY 32 100 125 150 ns 2.0 Fig.6 12 20 25 30 4.5 10 17 21 26 6.0 t THL / tTLH output transition times 19 75 95 110 ns 2.0 Fig.6 7 1 51 92 2 4 . 5 6 1 31 61 9 6 . 0

Philips Semiconductors Product specification Triple 3-input AND gate 74HC/HCT11 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: SSI Note to HCT types The value of additional quiescent supply current (ΔICC ) for a unit load of 1 is given in the family specifications. ‘To determineΔICC per input, multiply this value by the unit load coefficient shown in the table below. AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf= 6 ns; CL = 50 pF AC WAVEFORMS PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. INPUT UNIT LOAD COEFFICIENT nA, nB, nC 1.00 SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HCT VCC (V) WAVEFORMS+25 −40 to +85 −40 to +125 tPHL / tPLH propagation delay nA, nB, nC to nY 16 24 30 36 ns 4.5 Fig.6 tTHL / tTLH output transition times 7 15 19 22 ns 4.5 Fig.6 Fig.6 Waveforms showing the input (nA, nB, nC) to output (nY) propagation delays and the output transition times. (1) HC : VM = 50%; VI= GND to VCC HCT: VM = 1.3 V; VI= GND to 3 V.