74HC4094N

74HC4094 PHILIPS

Document overview

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Technical content

Product specification File under Integrated Circuits, IC06 December 1990 INTEGRATED CIRCUITS 74HC/HCT4094 8-stage shift-and-store bus register For a complete data sheet, please also download:

• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

Philips Semiconductors Product specification 8-stage shift-and-store bus register 74HC/HCT4094

FEATURES

• Output capability: standard
• ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT4094 are high-speed Si-gate CMOS devices and are pin compatible with the “4094” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4094 are 8-stage serial shift registers having a storage latch associated with each stage for strobing data from the serial input (D) to the parallel buffered 3-state outputs (QP 0 to QP7). The parallel outputs may be connected directly to common bus lines. Data is shifted on the positive-going clock (CP) transitions. The data in each shift register stage is transferred to the storage register when the strobe input (STR) is HIGH. Data in the storage register appears at the outputs whenever the output enable input (OE) signal is HIGH. Two serial outputs (QS 1 and QS2) are available for cascading a number of “4094” devices. Data is available at QS 1 on the positive-going clock edges to allow high-speed operation in cascaded systems in which the clock rise time is fast. The same serial information is available at QS 2 on the next negative-going clock edge and is for cascading “4094” devices when the clock rise time is slow.

APPLICATIONS

• Serial-to-parallel data conversion
• Remote control holding register QUICK REFERENCE DATA GND = 0 V; T amb = 25°C; tr = tf= 6 ns Notes 1. C PD is used to determine the dynamic power dissipation (PD inµW): PD = CPD × VCC 2 × fi+∑ (CL × VCC 2 × fo) where: fi= input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC 2 × fo) = sum of outputs C L = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI= GND to VCC For HCT the condition is VI= GND to VCC − 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC HCT tPHL / tPLH propagation delay C L = 15 pF; VCC = 5 V CP to QS1 15 19 ns CP to QS2 13 18 ns CP to QPn 20 21 ns STR to QPn 18 19 ns fmax maximum clock frequency 95 86 MHz C I input capacitance 3.5 3.5 pF C PD power dissipation capacitance per package notes 1 and 2 83 92 pF

Philips Semiconductors Product specification 8-stage shift-and-store bus register 74HC/HCT4094 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION

1 STR strobe input

2 D serial input

3 CP clock input

4, 5, 6, 7,14, 13, 12, 11 QP 0 to QP7 parallel outputs

8 GND ground (0 V)

9, 10 QS 1,Q S2 serial outputs

15 OE output enable input

CC positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

Philips Semiconductors Product specification 8-stage shift-and-store bus register 74HC/HCT4094 Fig.4 Functional diagram. Fig.5 Logic diagram.

Philips Semiconductors Product specification 8-stage shift-and-store bus register 74HC/HCT4094 FUNCTION TABLE Notes 1. H = HIGH voltage level L = LOW voltage level X = don’t care Z = high impedance OFF-state NC= no change ↑ = LOW-to-HIGH CP transition ↓ = HIGH-to-LOW CP transition 6 = the information in the seventh register stage is transferred to the 8th register stage and QSn output at the positive clock edge INPUTS PARALLEL OUTPUTS SERIAL OUTPUTS CP OE STR D QP 0 QP n QS 1 QS 2 L L H H H H X X L H H H X X X L H H Z Z NC L H NC Z Z NC QP n - 1 QP n - 1 NC Q’6 NC Q’6 Q’6 Q’6 NC NC QP 7 NC NC NC QP Fig.6 Timing diagram.

Philips Semiconductors Product specification 8-stage shift-and-store bus register 74HC/HCT4094 DC CHARACTERISTICS FOR 74HC For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf= 6 ns; CL = 50 pF SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HC VCC (V) WAVEFORMS +25 −40 to+85 −40 to+125 tPHL / tPLH propagation delay CP to QS1 150 190 225 ns 2.0 4.5 6.0 Fig.7 t PHL / tPLH propagation delay CP to QS2 135 170 205 ns 2.0 4.5 6.0 Fig.7 t PHL / tPLH propagation delay CP to QPn 195 245 295 ns 2.0 4.5 6.0 Fig.7 t PHL / tPLH propagation delay STR to QPn 180 225 270 ns 2.0 4.5 6.0 Fig.8 t PZH / tPZL 3-state output enable time OE to QPn 175 220 265 ns 2.0 4.5 6.0 Fig.9 t PHZ / tPLZ 3-state output disable time OE to QPn 125 155 190 ns 2.0 4.5 6.0 Fig.9 t THL / tTLH output transition time 19 110 ns 2.0 4.5 Fig.7 t W clock pulse width HIGH or LOW 100 120 ns 2.0 4.5 6.0 Fig.7 t W strobe pulse width HIGH 100 120 ns 2.0 4.5 6.0 Fig.8 t su set-up time D to CP ns 2.0 4.5 6.0 Fig.10 t su set-up time CP to STR 100 125 150 ns 2.0 4.5 6.0 Fig.8

Philips Semiconductors Product specification 8-stage shift-and-store bus register 74HC/HCT4094 th hold time D to CP ns 2.0 4.5 6.0 Fig.10 t h hold time CP to STR −14 ns 2.0 4.5 6.0 Fig.8 f max maximum clock pulse frequency 6.0 103 4.8 4.0 MHz 2.0 4.5 6.0 Fig.7 SYMBOL PARAMETER T amb (°C) UNIT TEST CONDITIONS 74HC VCC (V) WAVEFORMS +25 −40 to+85 −40 to+125

Philips Semiconductors Product specification 8-stage shift-and-store bus register 74HC/HCT4094 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (ΔICC ) for a unit load of 1 is given in the family specifications. To determineΔICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT OE, CP D STR 1.50 0.40 1.00

Philips Semiconductors Product specification 8-stage shift-and-store bus register 74HC/HCT4094 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf= 6 ns; CL = 50 pF SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HCT VCC (V) WAVEFORMS +25 −40 to+85 −40 to+125 tPHL / tPLH propagation delay CP to QS1 23 39 49 59 ns 4.5 Fig.7 tPHL / tPLH propagation delay CP to QS2 21 36 45 54 ns 4.5 Fig.7 tPHL / tPLH propagation delay CP to QPn 25 43 54 65 ns 4.5 Fig.7 tPHL / tPLH propagation delay STR to QPn 22 39 49 59 ns 4.5 Fig.8 tPZH / tPZL 3-state output enable time OE to QPn 20 35 44 53 ns 4.5 Fig.9 tPHZ / tPLZ 3-state output disable time OE to QPn 21 35 44 53 ns 4.5 Fig.9 tTHL / tTLH output transition time 7 15 19 22 ns 4.5 Fig.7 tW clock pulse width HIGH or LOW 16 7 20 24 ns 4.5 Fig.7 tW strobe pulse width HIGH 16 5 20 24 ns 4.5 Fig.8 tsu set-up time D to CP 10 4 13 15 ns 4.5 Fig.10 tsu set-up time CP to STR 20 9 25 30 ns 4.5 Fig.8 th hold time D to CP 4 0 4 4 ns 4.5 Fig.10 th hold time CP to STR 0 −4 0 0 ns 4.5 Fig.8 fmax maximum clock pulse frequency 30 80 24 20 MHz 4.5 Fig.7

Philips Semiconductors Product specification 8-stage shift-and-store bus register 74HC/HCT4094 AC WAVEFORMS Fig.7 Waveforms showing the clock (CP) to output (QPn,Q S1,Q S2) propagation delays, the clock pulse width and the maximum clock frequency. (1) HC : VM = 50%; VI= GND to VCC . HCT: VM = 1.3 V; VI= GND to 3 V. Fig.8 Waveforms showing the strobe (STR) to output (QPn) propagation delays and the strobe pulse width and the clock set-up and hold times for the strobe input. (1) HC : VM = 50%; VI= GND to VCC . HCT: VM = 1.3 V; VI= GND to 3 V. Fig.9 Waveforms showing the 3-state enable and disable times for input OE. (1) HC : VM = 50%; VI= GND to VCC . HCT: VM = 1.3 V; VI= GND to 3 V. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. Fig.10 Waveforms showing the data set-up and hold times for the data input (D). The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : V M = 50%; VI= GND to VCC . HCT: VM = 1.3 V; VI= GND to 3 V.