Summary
TRIPLE 3 INPUT OR GATE Oct-1992
Description
. HIGH SPEED tPD = 8 ns (TYP.) AT VCC = 5 V . LOW POWER DISSIPATION ICC = 1 µA (MAX.) AT TA = 25 °C . HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) . OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS . SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 4 mA (MIN.) . BALANCED PROPAGATION DELAYS tPLH = tPHL . WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V . PIN AND FUNCTION COMPATIBLE WITH 4075B The M54/74HC4075 isa high speed CMOSTRIPLE 3-INPUT OR GATE fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. The internal circuit is composed of 4 stages including buffered output, which gives high noise immunity and a stable output. All inputs are equipped with protection circuits against static discharge and transient excess voltage. 1/9