74HC373 ETC1

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OCTAL D-TYPE TRANSPARENT LATCH; 3-STATE

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© 3+state non-inverting outputs for SYMBOL | PARAMETER CONDITIONS UNIT bus oriented applications [ae | © Common 3state output enable propagation delay Vos input teu! ere | cL = 15 pF ‘© Functionally identical to the “563”, ‘PLH LE toan | Veo=5V "573" and "533" + «Guna: bosdrver [GL putas | rc © loc category: MSI econ } power dissipation GENERAL DESCRIPTION CPD capacitance per latch notes T and 2 The 74HC/HCT373 are high-speed - ‘Si-gate CMOS devices and are pin GND = OV: Tamb = 25 °City = ty = 6 ns compatible with low power Schottky TTL (LSTTL). They are specified in Notes compliance with JEDEC standard no. 7A. 1. Cp is used to determine the dynamic power dissipation (Pp in wW): ‘The 7AHC/HCTI79 ae octal Dtype PD = CPD x Voc? x fi +E (CL x VCC? x fo) where: transparent latches featuring seperate fi <i i : tance i ji = input frequency in MHz CL_ = output load capacitance in pF D-type inputs for each latch and 3-state fo = output frequency in MHz Vee = supply voltage in V ‘outputs for bus oriented applications. Cy x Voc? x 14) = sum of outputs A latch enable (LE) input and an output LX VCC % fo! * a enable (OE) input are common to all 2. For HC_ the condition is V) = GND to Vcc latches. For HCT the condition is Vi = GND to Vcc ~ 1.5 V ‘The "373" consists of eight D-type transparent latches with 3.state true ‘outputs. When LE is HIGH, data at the PACKAGE OUTLINES Da lnpeaiter the latches n cle 204ead DIL; plastic (SOT146). condition the latches are transparent, ; rere latch output wil chanes ote gach 208ad mini-pack: plastic (S020; SOTI69A) time its corresponding D-input changes. When LE is LOW the latches store the PIN DESCRIPTION information that was present at the D-inputs a set-up time preceding the [PINNo. | SYMBOL NAME AND FUNCTION HIGH-to- LOW transition of LE. When OE is LOW, the contents of the 1 OE ‘3-state output enable input (active LOW) B latches are available at the outputs. 2,5,6,9,12 When OE is HIGH, the outputs go to 16 16,19 | 20t0Q7 ‘B-state latch outputs the high impedence OFF ste eg Operation of the OE input does not , 4, 7, 8, 13, i affect the state of the latches. 14,17, 18 Doro D7 date inputs ‘The "373" is functionally identical to 10 GND ground (0 V) the “539 "569" and "873", but the " Le latch enable input (active HIGH) "563" and “533” have inverted outputs : and the "663" and "eye" hee 20 Vec positive supply voltage different pin arrangement. at] OF fame Yon oo [=] [ao, aw ey rola] a>, 2-0 Af? a °&] fa) % soy obs 2 ‘ 37a 7 | t ig [Jes 4% pie oo ufos age 2s [a] fa} wo, afew “f $s ot PE og ov [a] fi)ue 1 ven at+—fa Fig. 1 Pin configuration. Fig. 2 Logic symbol Fig, 3 IEC logic symbol, September 1993 619

«Pj LC] [| [as] s ‘e] Ef fake os} [] [| [ess tPA veel [] [ashe ars Nels se] Cl Fy fede Ke Fig. 4 Functional diagram. Fig. 5 Logic diagram (one latch). FUNCTION TABLE INPUTS OUTPUTS OPERATING MODES wares [aE te] 0, | enable and read L Lt L register H H H (transparent mode) i H = HIGH voltage level latch and 1 h = HIGH voltage level one set-up time prior to the register, reed t h 4 4 HIGH-to-LOW LE transition a L = LOW voltage level latch register and x x z | = LOW voltage level one set-up time prior to the Gable gots x) © | 2 HIGHtOLOW LE wonsiton X= don't care Z = high impedance OF F-state VY VY VY VY V Y VY V wrod! | fearon] [laren] | [laren] fearenl] feasonl] tenes] | Poaee am TT mi am Ty ry ry opel EE TE eer] 7 7 vy ily ly ify 7 °° * * “ “ ° fe cams Fig. 6 Logic diagram,

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Octal D-type transparent latch; 3-state 74HC/HCT373 MSI DC CHARACTERISTICS FOR 74HC For the OC characteristics see chapter “HCMOS family characteristics”, section “Family specifications”. Output capability: bus driver Ic category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 Vj t,= t¢= 6 ns; C), = 50 pF Tamb (°C) TEST CONDITIONS svweou | paraneren a ee a [in| | in] sn | a | s 150 190 225 2.0 tPHL/ propagation delay 30 38 45 | ns 45 | Fig.7 ‘LH Pn toQn 26 33 38 6.0 175 265 2.0 tpHL/ | propagation delay % 33 45 | Figs LH LEtoQ, 30 45 6.0 i 1 225 20 tpzH/ __} 3-state output enable time 4° x 32 45 | Fig.9 wP2L DE t0 On 13, | 26 |33 38 60 touz! | Saw oupurdiaierine| [47 | 150 || 90 25 20 LZ | OF ton 14 | 26 [33 38 60 cra! 14 | 75 90 20 ‘Output transition time 5 15 18 45 tTLH \\4 _|s 15 6.0 A 80 | 17 100 2.0 w UE pike width 16 |6 20 | 45 45 7 6.0 50/14 65 75 2.0 teu set-up time 10 1s 13 | 15 45. | Fig. 10 Dp to LE a |a nf 13 60 " 5 5 2.0 hold time | 5 5 45 Fig. 10 * Paro re Hel 5 5 60 { September 1993 621

DC CHARACTERISTICS FOR 74HCT For the DC characteristics see chapter “HCMOS family characteristics”, section “Family specifications”, Output capability: bus driver lec category: MSI Note to HCT types The value of additional quiescent supply current (I¢c) for a unit load of 1 is given in the family specifications. To determine Alc per input, multiply this value by the unit load coefficient shown in the table below. UNIT LOAD COEFFICIENT Dy 0.30 Le 1.50 OE 1.00 AC CHARACTERISTICS FOR 74HCT GND = 0 V;t,= t¢= 6 ns; CL = 50 pF 74CHT SYMBOL | PARAMETER Vcc | WAVEFORMS 40 t0 +85 7 mmm | [| tpHL/ | propagation delay Fig.7 'PLH Dp to Qn *PHL/ | propagation delay Fig. 8 LH LEt0Q, . tpzy/ | state output enable time Fig. 9 bea OE to Op * tpHz/ | State output disable time PLZ OE to 0, ATHL | output transition time 12 Fig. 7 'TLH Pat transi LE pulse width w HIGH *I* | =| im [ele | set-up time | 45 | Fig. 10 teu Sr TOLE 12/6 18 18 ns 9. hold time . 45 | Fig 10 th Botte a |-1 4 4 ns m

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Octal D-type transparent latch; 3-state 74HC/HCT373 Msi AC WAVEFORMS tw—el Fig. 8 Waveforms showing the latch enable input Fig. 7 Waveforms showing the input (Dp) (LE) pulse width, the latch enable input to output to output (Qn) propagation delays and (Qp) propagation delays and the output transition the output transition times. times. “i +" Wi a c 0, ovat ~ =| a =e Lean) a, ouTeUT von banner wait Fig. 10 Waveforms showing the data set-up and hold times for Dp input to LE input. reemee aig TI Sah ol is Note to Fig. 10 ‘The shaded areas indicate when the input is Fig. 9 Waveforms showing the 3-state enable and permitted to change for predictable output disable times. performance. Note to AC waveforms (1) HC : Vy = 50%; V) = GND to Voc. HCT: Vy = 1.3V; Vj = GND to 3V. | September 1993 623