74HC373

74HC373 WINGS

Document overview

• Manufacturer or author: Provided By digicamel.com
• PDF pages: 6

Technical content

Octal Transparent D-type Latches W ith 3-State Outputs GENERAL DESCRIPTION 74HC373 is fabricated with high-speed silicon gate CMOS technology. It has the high noise immunity and low power consumption of standard CMOS integrated circuits. The eight latches in 74HC373 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the levels that were set up at the D inputs. An output-enable input (OE) makes the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high- impedance state and increased drive provide the capability to drive bus lines without interface or pull-up components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off. These 8-bit latches with 3-state outputs are designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bi-directional bus drivers, and working registers.

FEATURES

• Wide operating supply voltage range: 2-6V
• 8 high-current latches with 3-state outputs in a single package
• Full parallel access for loading
• Low input current: 1 µA (Max.)
• Low power consumption: 80 µA (Max.) LOGIC DIAGRAM OE (1) LE (11) FUNCTIONAL DESCRIPTION Truth Table Inputs Outputs OE LE D Q L H H H L H L L L L X Q0 H X X Z H = High Level (steady state). L= Low Level (steady state) X = Irrelevant (any input, including transitions) 1D C1 2D C1 3D C1 4D C1 5D C1 6D C1 7D C1 8D C1

DC supply voltage (Vcc) - 0.5 ~ + 7.0 V DC input or output Voltage (VIN, VOUT) -0.5 to Vcc +0.5 V DC Current Drain per pin, any output (Iout) ±35 mA DC Current per pin, Vcc or GND (Icc) ±70 mA Storage Temperature( TSTG) -65 ~ +150 ℃ Note: 1. Absolute maximum ratings are those values beyon d which the safety of the device cannot be guaranteed. RECOMMENDED OPERATING CONDITONS Parameter Min. Normal Max. Unit Vcc Supply V oltage 2.0 5.0 6.0 V VIH High-level Input Voltage VCC = 2.0V VCC = 4.5V VCC = 6.0V 1.5 3.15 4.2 V VIL Low-level Input Voltage VCC= 2.0V VCC = 4.5V VCC = 6.0V 0.5 1.35 1.8 V VI Input V oltage 0 Vcc V VO Output V oltage 0 Vcc V 74HC373 -40 +85 ℃ Operating Temperature (TA) Input Rise/Fall Times (tr, tf) V CC = 2.0V VCC = 4.5V VCC = 6.0V 1000 500 400 ns Note: 2. All unused inputs of the device must be held at Vcc or GND to ensure proper device operation. DC ELECTRICAL CHARACTERISTICS ( apply across temperature range unless otherwise specified) TA＝25oC -40 ~ +85 Parameter Test Conditions Vcc Min. Typ. Max. Min. Max. Unit 2V 1.9 1.998 1.9 4.5V 4.4 4.499 4.4 IOH = -20uA 6V 5.9 5.999 5.9 IOH = -6mA 4.5V 3.98 4.3 3.84 VOH VI =VIH or VIL IOH=-7.8mA 6V 5.48 5.8 5.34 V 2V 0.002 0.1 0.1 4.5V 0.001 0.1 0.1 IOL = 20uA 6V 0.001 0.1 0.1 IOL = 6mA 4.5V 0.17 0.26 0.33 VOL VI =VIH or VIL IOL = 7.8mA 6V 0.15 0.26 0.33 V II VI = VCC or 0 6V ±0.1 ±100 ±1000 nA IOZ V O = VCC or 0 6V ±0.01 ±0.5 ±5 µA ICC VI = VCC or 0, IO = 0 6V 8 80 µA Ci 2V～6V 3 10 10 pF

TIMING REQUIREMENTS OVER RECOMMENDED OPERATING TEMPERATURE (unless otherwise specified) T A 25℃ -40 ~ +85 Parameter VDD Min Max Min Max Unit

2.0 V 80 100

tw Pulse duration, LE high 4.5V 16 20 ns

6.0 V 14 17

2.0 V 50

tsu Setup time, data before LE↓ 4.5V 10 13 ns

6.0 V 9

2.0 V 20

th Hold time, data after LE↓ 4.5V 10 12 ns

6.0 V 10 12

AC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPER ATING TEMPERATURE, CL = 50 pF (unless otherwise specified) Parameter From To VDD T A = 25℃ -40 ~ +85 (Input) (Output) Min Typ Max Min Max Unit

2.0 V 58 150 190

D Q 4.5V 15 30 38 ns

6.0 V 13 26 32

2.0 V 73 175 220

4.5V 18 35 44 tpd LE Any Q

6.0 V 15 30 38

___ 2.0 V 65 150 190 ten OE Any Q 4.5V 17 30 38 ns

6.0 V 14 26 32

2.0 V 50 150 190

4.5V 15 30 38 tdis ___ OE Any Q

2.0 V 28 60 75

tt Any Q 4.5V 8 12 15 ns

6.0 V 6 10 13

AC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPER ATING TEMPERATURE, CL = 150 pF (unless otherwise specified) Parameter From To VDD T A = 25℃ -40 ~ +85 (Input) (Output) Min Typ Max Min Max Unit

2.0 V 82 200 250

D Q 4.5V 22 40 50 ns

6.0 V 19 34 43

2.0 V 100 225 285

4.5V 24 45 57 tpd LE Any Q

6.0 V 20 38 48

___ 2.0 V 90 200 250 ten OE Any Q 4.5V 23 40 50 ns

2.0 V 45 210 265

tt Any Q 4.5V 17 42 53 ns

6.0 V 13 36 45

AC SWITCHING WAVEFORM AND AC TEST CIRCUIT V oltage Waveforms Pulse Durations V oltage Waveforms Setup & Hold and Input Rise & Fall Times V oltage Waveforms Propagation Delay and Output Transition Times V oltage Waveforms Enable and Disable Times for 3-State Outputs t w 50% 50% 50% 50% Low-Level Pulse V cc V cc High-Level Pulse tr 50% 10% 90% 90% 50% 10% tf Vcc 0 V Input 0 V Input 50% tsu Vcc th Reference Data 50% 50% 50% 90% 50% 10% tPZL tPLZ tPHZ Vcc 0 V VOL VOH ≈0 V tPZH ≈Vcc Output Control (Low-Level Enabling) Output Waveform1 Output Waveform ≈Vcc tPLH tr tPHL tf tf tr tPHL tPLH 50% 50% 50% 10% 90% 90% 50% 10% 90% 50% 10% 90%50% 10% Input In-Phase Output Out-of-Phase Output Vcc 0 V VOH VOL VOH VOL

1kΩ 50 pF or 150 pF Closed Open tPHZ Open Closed tdis tPLZ 1kΩ 50 pF Closed Open tpd or tt - 50 pF or 150 pF Open Open Notes: A. C L includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal condit ions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal condition s such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chose n arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR≤ 1 MHz, Zo = 50 Ω, tr=6ns, tf =6ns. D. The outputs are measured one at a time with one input transition per measurement. E. t PLZ and tPHZ are the same as tdis. F. t PZL and tPZH are the same as ten. G. t PLH and tPHL are the same as tpd. PIN DESCRIPTION PIN NO. SYMBOL DESCRIPTION 1D - 8D 1Q - 8Q GND OE LE VCC Data Inputs Outputs Ground (0V) Output-enable latch-enable Positive power supply OE 4D 5D GND LE VCC Pin Configuration (DIP-20) Logic Symbol OE LE 3 VDD RL Test Point From Output Under Test CL (see Note A)

The Coordinate of Each Pad Note: Substrate should be connected to Vcc or left it open. 74HC373 Pad size = 90 um x 90 um Die Size = 49 mil x 77 mil 5Q LE GND VCC OE 1Q 8Q