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Document overview
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Technical content
- General description The 74HC373; 74HCT373 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A. The 74HC373; 74HCT373 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all latches. The 74HC373; 74HCT373 consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D input changes. When LE is LOW the latches store the information that was present at the D inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high- impedance OFF-state. Operation of the OE input does not affect the state of the latches. The 74HC373; 74HCT373 is functionally identical to:
- 74HC563; 74HCT563: but inverted outputs and different pin arrangement
- 74HC573; 74HCT573: but different pin arrangement 2. Features and benefits 3-state non-inverting outputs for bus oriented applications Common 3-state output enable input Functionally identical to the 74HC563; 74HCT563 and 74HC573; 74HCT573 ESD protection: HBM JESD22-A114F exceeds 2 000 V MM JESD22-A115-A exceeds 200 V Specified from 40 Ct o+ 8 5C and from 40 Ct o+ 1 2 5C 74HC373; 74HCT373 Octal D-type transparent latch; 3-state Rev. 5 — 13 December 2011 Product data sheet
Table 1. Ordering information
1 TO 8
Product data sheet Rev. 5 — 13 December 2011 3 of 26 NXP Semiconductors 74HC373; 74HCT373 Octal D-type transparent latch; 3-state Fig 2. Logic symbol Fig 3. IEC logic symbol 001aae048 OE LE 001aae049 11 C1 OE LE EN Fig 4. Logic diagram (one latch) 001aae051 LE QD LE LE LE Fig 5. Logic diagram 001aae052 D LE LE Q LATCH D LE LE Q LATCH D LE LE Q LATCH D LE LE Q LATCH D LE LE Q LATCH D LE LE Q LATCH D LE LE Q LATCH D LE LE Q LATCH LE OE
5.1 Pinning
5.2 Pin description
Table 2. Pin description
6.1 Function table
Z = high-impedance OFF-state. [1] For DIP20 package: P tot derates linearly with 12 mW/K above 70 C. [2] For SO20: P tot derates linearly with 8 mW/K above 70 C. [3] For SSOP20 and TSSOP20 packages: P tot derates linearly with 5.5 mW/K above 60 C. [4] For DHVQFN20 package: P tot derates linearly with 4.5 mW/K above 60 C. Table 3. Function table [1] Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
- Recommended operating conditions
Table 5. Recommended operating conditions Table 6. Static characteristics 74HC373 At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Table 6. Static characteristics 74HC373 …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Table 7. Static characteristics 74HCT373 At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Table 7. Static characteristics 74HCT373 …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Table 8. Dynamic characteristics 74HC373 Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Table 8. Dynamic characteristics 74HC373 …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
[1] t pd is the same as tPLH and tPHL. [2] t en is the same as tPZH and tPZL. [3] t dis is the same as tPLZ and tPHZ. [4] t t is the same as tTHL and tTLH. [5] C PD is used to determine the dynamic power dissipation (PD in W). (CL VCC2 fo) = sum of outputs. Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Table 9. Dynamic characteristics 74HCT373 Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Table 9. Dynamic characteristics 74HCT373 …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
[1] t pd is the same as tPLH and tPHL. [2] t en is the same as tPZH and tPZL. [3] t dis is the same as tPLZ and tPHZ. [4] t t is the same as tTHL and tTLH. [5] C PD is used to determine the dynamic power dissipation (PD in W). (CL VCC2 fo) = sum of outputs. Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Measurement points are given in Table 10. Measurement points are given in Table 10.
Measurement points are given in Table 10. Measurement points are given in Table 10. Table 10. Measurement points
Test data is given in Table 11. Table 11. Test data
Product data sheet Rev. 5 — 13 December 2011 18 of 26 NXP Semiconductors 74HC373; 74HCT373 Octal D-type transparent latch; 3-state 12. Package outline Fig 13. Package outline SOT146-1 (DIP20) UNIT A max. 1 2 b1 cD E e MHL REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm inches DIMENSIONS (inch dimensions are derived from the original mm dimensions) SOT146-1 99-12-27 03-02-13 A min. A max. b Z max.wMEe1 1.73 1.30 0.53 0.38 0.36 0.23 26.92 26.54 6.40 6.22 3.60 7.80 10.0 8.3 24.2 0.51 3.2 0.068 0.051 0.021 0.015 0.014 0.009 1.060 1.045 0.25 0.24 0.14 0.31 0.39 SC-603MS-001 MH c (e )1 ME A L seating plane w M e D Z b E pin 1 index 0 5 10 mm scale Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. (1)(1) (1) DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1
Product data sheet Rev. 5 — 13 December 2011 19 of 26 NXP Semiconductors 74HC373; 74HCT373 Octal D-type transparent latch; 3-state Fig 14. Package outline SOT163-1 (SO20) UNIT A max. A1 A2 A3 bp cD (1) E (1) (1)eH E LL p Q Zy w v θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm inches 2.65 0.3 0.1 2.45 2.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 o o 0.25 0.1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 SOT163-1 w M bp detail X Z e D y 0.25 075E04 MS-013 pin 1 index 0.1 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.51 0.49 0.30 0.29 0.05 1.4 0.0550.419 0.394 0.043 0.039 0.035 0.0160.01 0.25 0.01 0.0040.043 0.0160.01 0 5 10 mm scale X θ AA1 HE Lp Q E c L v M A (A )3 A SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 99-12-27 03-02-19
Product data sheet Rev. 5 — 13 December 2011 20 of 26 NXP Semiconductors 74HC373; 74HCT373 Octal D-type transparent latch; 3-state Fig 15. Package outline SOT339-1 (SSOP20) UNIT A1 A2 A3 bp cD (1) E(1) eH E LL p Q (1)Z y w v θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.21 0.05 1.80 1.65 0.38 0.25 0.20 0.09 7.4 7.0 5.4 5.2 0.65 7.9 7.6 0.9 0.7 0.9 0.5 o o0.131.25 0.2 0.1 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. 1.03 0.63 SOT339-1 MO-150 99-12-27 03-02-19 X w M θ A bp D HE Lp Q detail X E Z e c L v M A (A )3 A 11 0 20 11 y 0.25 pin 1 index 0 2.5 5 mm scale SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1 A max.
Product data sheet Rev. 5 — 13 December 2011 21 of 26 NXP Semiconductors 74HC373; 74HCT373 Octal D-type transparent latch; 3-state Fig 16. Package outline SOT360-1 (TSSOP20) UNIT A1 A2 A3 bp cD (1) E (2) (1)eH E LL p QZ y w v θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.5 0.2 o o0.13 0.10.21 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 SOT360-1 MO-153 99-12-27 03-02-19 w M bp D Z e 0.25 11 0 20 11 pin 1 index θ AA1 Lp Q detail X L (A )3 HE E c v M A XA y 0 2.5 5 mm scale TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 A max. 1.1
Product data sheet Rev. 5 — 13 December 2011 22 of 26 NXP Semiconductors 74HC373; 74HCT373 Octal D-type transparent latch; 3-state Fig 17. Package outline SOT764-1 (DHVQFN20) terminal 1 index area 0.51 A1 EhbUNIT ye 0.2 c REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 4.6 4.4 Dh 3.15 2.85 2.6 2.4 1.15 0.85 3.50.30 0.18 0.05 0.00 0.05 0.1 DIMENSIONS (mm are the original dimensions) 0.5 0.3 L 0.1 v 0.05 w 0 2.5 5 mm scale SOT764-1 DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm A(1) max. A c detail X yy1 Ce L Eh Dh e b 19 12 101 X D E C B A terminal 1 index area A C C Bv M w M E(1) Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. D(1) 02-10-17 03-01-27
Table 12. Abbreviations Table 13. Revision history
- Legal pages updated. 74HC_HCT373 v.4 20100903 Product data sheet - 74HC_HCT373 v.3 74HC_HCT373 v.3 20060120 Product data sheet - 74HC_HCT373_CNV v.2 74HC_HCT373_CNV v.2 19970827 Product specification - -
Product data sheet Rev. 5 — 13 December 2011 24 of 26 NXP Semiconductors 74HC373; 74HCT373 Octal D-type transparent latch; 3-state 15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
Product data sheet Rev. 5 — 13 December 2011 25 of 26 NXP Semiconductors 74HC373; 74HCT373 Octal D-type transparent latch; 3-state Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74HC373; 74HCT373 Octal D-type transparent latch; 3-state © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 13 December 2011 Document identifier: 74HC_HCT373 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 17. Contents