Download PDF74HC373 ONSEMI
Document overview
- Manufacturer or author: Provided By digicamel.com
- PDF pages: 9
Technical content
Features
- Output Drive Capability: 15 LSTTL Loads
- Outputs Directly Interface to CMOS, NMOS and TTL
- Operating V oltage Range: 2.0 to 6.0 V
- Low Input Current: 1.0 /C0109A
- High Noise Immunity Characteristic of CMOS Devices
- In Compliance with the JEDEC Standard No. 7.0 A Requirements
- ESD Performance: HBM /C0062 2000 V; Machine Model /C0062 200 V
- Chip Complexity: 186 FETs or 46.5 Equivalent Gates
- This is a Pb−Free Device http://onsemi.com MARKING DIAGRAM HC373 = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week /C0071 = Pb−Free Package See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet.
ORDERING INFORMATION
/C0071 TSSOP−20 DT SUFFIX CASE 948E1 (Note: Microdot may be in either location)
http://onsemi.com DATA INPUTS D7 18 1OUTPUT ENABLE PIN 20 = V CC PIN 10 = GND NONINVERTING OUTPUTS 11LATCH ENABLE FUNCTION TABLE Inputs Output Output Latch Enable Enable D Q LH HH LH LL L L X No Change HX XZ X = Don’t Care Z = High Impedance OUTPUT ENABLE GND Q1 5 V CC LATCH ENABLE LOGIC DIAGRAM PIN ASSIGNMENT Design Criteria Value Units Internal Gate Count* 46.5 ea Internal Gate Propagation Delay 1.5 ns Internal Gate Power Dissipation 5.0 /C0109W Speed Power Product 0.0075 pJ *Equivalent to a two−input NAND gate.
http://onsemi.com ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V Iin DC Input Current, per Pin ±20 mA Iout DC Output Current, per Pin ±35 mA ICC DC Supply Current, VCC and GND Pins ±75 mA PD Power Dissipation in Still Air, TSSOP Package† 450 mW Tstg Storage Temperature – 65 to + 150 /C0095C TL Lead Temperature, 1 mm from Case for 10 Seconds (TSSOP Package) 260 /C0095C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above t he Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. †Derating — TSSOP Package: − 6.1 mW//C0095C from 65/C0095 to 125/C0095C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High −Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V TA Operating Temperature, All Package Types – 55 + 125 /C0095C tr, tf Input Rise and Fall Time V CC = 2.0 V (Figure 1) V CC = 4.5 V VCC = 6.0 V 1000 500 400 ns Device Package Shipping† 74HC373DTR2G TSSOP−20* 2500 Units / Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance cir- cuit. For proper operation, V in and Vout should be constrained to the range GND /C0118 (Vin or Vout) /C0118 VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC). Unused outputs must be left open.
http://onsemi.com DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions VCC (V) – 55 to 25/C0095C /C0118 85/C0095C /C0118 125/C0095C Unit VIH Minimum High−Level Input Voltage Vout = VCC – 0.1 V |Iout| /C0118 20 /C0109A 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 V VIL Maximum Low−Level Input Voltage Vout = 0.1 V |Iout| /C0118 20 /C0109A 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 V VOH Minimum High−Level Output Voltage Vin = VIH |Iout| /C0118 20 /C0109A 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V Vin = VIH |Iout| /C0118 2.4 mA |Iout| /C0118 6.0 mA |Iout| /C0118 7.8 mA 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.2 3.7 5.2 VOL Maximum Low−Level Output Voltage Vin = VIL |Iout| /C0118 20 /C0109A 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V Vin = VIL |Iout| /C0118 2.4 mA |Iout| /C0118 6.0 mA |Iout| /C0118 7.8 mA 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.4 0.4 0.4 Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 /C0109A IOZ Maximum Three−State Leakage Current Output in High−Impedance State Vin = VIL or VIH Vout = VCC or GND ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 /C0109A 6.0 4.0 40 40 /C0109A NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
http://onsemi.com AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) Symbol Parameter VCC (V) Guaranteed Limit Unit– 55 to 25/C0095C /C0118 85/C0095C /C0118 125/C0095C tPLH tPHL Maximum Propagation Delay, Input D to Q (Figures 1 and 5) 2.0 3.0 4.5 6.0 125 155 110 190 130 ns tPLH tPHL Maximum Propagation Delay, Latch Enable to Q (Figures 2 and 5) 2.0 3.0 4.5 6.0 140 175 120 210 140 ns tPLZ tPHZ Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) 2.0 3.0 4.5 6.0 150 100 190 125 225 150 ns tPZL tPZH Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) 2.0 3.0 4.5 6.0 150 100 190 125 225 150 ns tTLH tTHL Maximum Output Transition Time, Any Output (Figures 1 and 5) 2.0 3.0 4.5 6.0 ns Cin Maximum Input Capacitance 10 10 10 pF Cout Maximum Three−State Output Capacitance (Output in High−Impedance State) 15 15 15 pF NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). CPD Power Dissipation Capacitance (Per Enabled Output)* Typical @ 25°C, VCC = 5.0 V pF36 * Used to determine the no −load dynamic power consumption: P D = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the ON Semiconductor High −Speed CMOS Data Book (DL129/D).
http://onsemi.com PACKAGE DIMENSIONS TSSOP−20 CASE 948E−02 ISSUE C DIM A MIN MAX MIN MAX INCHES 6.60 0.260 MILLIMETERS B 4.30 4.50 0.169 0.177 C 1.20 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.27 0.37 0.011 0.015 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0 8 0 8 /C0095/C0095/C0095/C0095 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ 11 0 1120 PIN 1 IDENT A B −T− 0.100 (0.004) C D G H SECTION N−N K JJ 1 N N M F −W− SEATING PLANE −V− −U− SUM0.10 (0.004) V ST 20X REFK L L/22X SU0.15 (0.006) T DETAIL E 0.25 (0.010) DETAIL E 6.40 0.252 SU0.15 (0.006) T 7.06 16X 0.36 16X 1.26 0.65 DIMENSIONS: MILLIMETERS PITCH SOLDERING FOOTPRINT* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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