MM74HC164 FAIRCHILD

Document overview

  • Manufacturer or author: Provided By digicamel.com
  • PDF pages: 7

Technical content

Features

I Typical operating frequency: 50 MHz I Typical propagation delay: 19 ns (clock to Q) I Wide operating supply voltage range: 2V to 6V I Low input current: 1 µA maximum I Low quiescent supply current: 80 µA maximum (74HC Series) I Fanout of 10 LS-TTL loads Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Order Number Package Package DescriptionNumber MM74HC164M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC164MX_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC164MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC164MTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC164N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

www.fairchildsemi.com 2 MM74HC164 Connection Diagram Top View Truth Table H = HIGH Level (steady state), L = LOW Level (steady state) X = Irrelevant (any input, including transitions) ↑ = Transition from LOW-to-HIGH level. Q AO , QBO , QHO = the level of QA, QB, or QH , respectively, before the indi- cated steady state input conditions were established. Q An, QGn = The level of QA or QG before the most recent ↑ transition of the clock; indicated a one-bit shift. Logic Diagram Inputs Outputs Clear Clock A B Q A Q B ... Q H LX X X LL L HL X X Q AO Q BO Q HO H ↑ HH H Q An Q Gn H ↑ LX L Q An Q Gn H ↑ XL L Q An Q Gn

3 www.fairchildsemi.com MM74HC164 Absolute Maximum Ratings(Note 1) (Note 2) Recommended Operating Conditions Note 1: Absolute Maximum Ratings are those values beyond which dam- age to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N ” package: − 12 mW/ °C from 65°C to 85°C. Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH , and VOL ) occur for HC at 4.5V. Thus the 4.5V values should be used when rent (IIN, ICC , and IOZ ) occur for CMOS at the higher voltage and so the 6.0V values should be used. Supply Voltage (VCC ) −0.5 to +7.0V DC Input Voltage (VIN) −1.5 to VCC +1.5V DC Output Voltage (VOUT ) −0.5 to VCC +0.5V Clamp Diode Current (IIK, IOK ) ±20 mA DC Output Current, per pin (IOUT ) ±25 mA DC V CC or GND Current, per pin (ICC ) ±50 mA Storage Temperature Range (TSTG ) −65°C to +150°C Power Dissipation (PD ) (Note 3) 600 mW S.O. Package only 500 mW Lead Temperature (T (Soldering 10 seconds) 260 °C Min Max Units Supply Voltage (VCC )2 6 V DC Input or Output Voltage (VIN, VOUT )0 V CC V Operating Temperature Range (TA) −40 +85 °C Input Rise or Fall Times (tr, tf) VCC = 2.0V 1000 ns VCC = 4.5V 500 ns VCC = 6.0V 400 ns Symbol Parameter Conditions VCC TA = 25°CT A = −40 to 85°CT A = −55 to 125°C Units Typ Guaranteed Limits VIH Minimum HIGH Level 2.0V 1.5 1.5 1.5 VInput Voltage 4.5V 3.15 3.15 3.15 6.0V 4.2 4.2 4.2 VIL Maximum LOW Level 2.0V 0.5 0.5 0.5 VInput Voltage 4.5V 1.35 1.35 1.35 6.0V 1.8 1.8 1.8 VOH Minimum HIGH Level V IN = VIH or VIL V VIN = VIH or VIL VOL Maximum LOW Level V IN = VIH or VIL V Output Voltage |I OUT | ≤ 20 µA 2.0V 0 0.1 0.1 0.1 4.5V 0 0.1 0.1 0.1 6.0V 0 0.1 0.1 0.1 VIN = VIH or VIL IIN Maximum Input V IN = VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA Current ICC Maximum Quiescent V IN = VCC or GND 6.0V 8.0 80 160 µA Supply Current I OUT = 0 µA

www.fairchildsemi.com 4 MM74HC164 VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns C L = 50 pF, tr = tf = 6 ns (unless otherwise specified) Note 5: C PD determines the no load dynamic power consumption, PD = CPD VCC 2 f + ICC VCC , and the no load dynamic current consumption, IS = CPD VCC f + ICC . Symbol Parameter Conditions Typ Guaranteed Units Limit fMAX Maximum Operating Frequency 30 MHz tPHL , tPLH Maximum Propagation Delay 19 30 ns Clock to Output t PHL Maximum Propagation Delay 23 35 ns Clear to Output tREM Minimum Removal Time, −20n s Clear to Clock tS Minimum Setup Time 12 20 ns Data to Clock t H Minimum Hold Time 1 5 ns Clock to Data tW Minimum Pulse Width 10 16 ns Clear or Clock Symbol Parameter Conditions VCC TA = 25°CT A = −40 to 85°CT A = −55 to 125°C Units Typ Guaranteed Limits fMAX Maximum Operating Frequency 2.0V 5 4 3 MHz4.5V 27 21 18 6.0V 31 24 20 tPHL , tPLH Maximum Propagation Delay 2.0V 115 175 218 254 nsClock to Output 4.5V 13 35 44 51 6.0V 20 30 38 44 tPHL Maximum Propagation Delay 2.0V 140 205 256 297 nsClear to Output 4.5V 28 41 51 59 6.0V 24 35 44 51 tREM Minimum Removal Time 2.0V −70 0 0 nsClear to Clock 4.5V −30 0 0 6.0V −20 0 0 tS Minimum Setup Time 2.0V 25 100 125 150 nsData to Clock 4.5V 14 20 25 30 6.0V 12 17 21 25 tH Minimum Hold Time 2.0V −25 5 5 nsClock to Data 4.5V 0 5 5 5 6.0V 1 5 5 5 tW Minimum Pulse Width 2.0V 22 80 100 120 nsClear or Clock 4.5V 11 16 20 24 6.0V 10 14 18 20 tTHL , tTLH Maximum Output 2.0V 75 95 110 nsRise and Fall Time 4.5V 15 19 22 6.0V 13 16 19 tr, tf Maximum Input 2.0V 1000 1000 1000 nsRise and Fall Time 4.5V 500 500 500 6.0V 400 400 400 C PD Power Dissipation Capacitance (Note 5) (per package) 5.0V 150 pF C IN Maximum Input Capacitance 5 10 10 10 pF

5 www.fairchildsemi.com MM74HC164 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A

www.fairchildsemi.com 6 MM74HC164 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 7 www.fairchildsemi.com MM74HC164 8-Bit Serial-in/Parallel-out Shift Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com