74HC164

SN54HC164 TI

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SN54HC164, SN74HC164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS115D – DECEMBER 1982 – REVISED AUGUST 2003 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068 Wide Operating Voltage Range of 2 V to 6 V /C0068 Outputs Can Drive Up To 10 LSTTL Loads /C0068 Low Power Consumption, 80-µA Max ICC /C0068 Typical tpd = 20 ns /C0068 ±4-mA Output Drive at 5 V /C0068 Low Input Current of 1 µA Max /C0068 AND-Gated (Enable/Disable) Serial Inputs /C0068 Fully Buffered Clock and Serial Inputs /C0068 Direct Clear description/ordering information These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.

ORDERING INFORMATION

TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING –40 C to 85C PDIP – N Tube of 25 SN74HC164N SN74HC164N –40 C to 85C SOIC – D Tube of 50 SN74HC164D HC164 –40 C to 85C SOIC – D Reel of 2500 SN74HC164DR HC164 –40°C to 85°C Reel of 250 SN74HC164DT –40°C to 85°C SOP – NS Reel of 2000 SN74HC164NSR HC164 TSSOP – PW Tube of 90 SN74HC164PW HC164TSSOP – PW Reel of 2000 SN74HC164PWR HC164 Reel of 250 SN74HC164PWT –55 C to 125C CDIP – J Tube of 25 SNJ54HC164J SNJ54HC164J –55°C to 125°C CFP – W Tube of 150 SNJ54HC164W SNJ54HC164W LCCC – FK Tube of 55 SNJ54HC164FK SNJ54HC164FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SN54HC164 ...J O R W PACKAGE SN74HC164 . . . D, N, NS, OR PW PACKAGE (TOP VIEW) A B Q A Q B Q C Q D GND VCC Q H Q G Q F Q E CLR CLK 321 2 0 1 9 91 01 11 21 3 Q G NC Q F NC Q E Q A NC Q B NC Q C B A NC CLK CLR V Q D GND NC SN54HC164 . . . FK PACKAGE (TOP VIEW) CC H Q NC – No internal connection Copyright  2003, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

SN54HC164, SN74HC164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS115D – DECEMBER 1982 – REVISED AUGUST 2003

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CLR CLK A B Q A Q B ...Q H L X X X L L L H LXX Q A0 Q B0 Q H0 H ↑ HHH Q An Q Gn H ↑ LXL Q An Q Gn H ↑ X L L Q An Q Gn Q A0, QB0, QH0 = the level of QA, QB, or QH , respectively, before the indicated steady-state input conditions were established Q An, QGn = the level of QA or QG before the most recent ↑ transition of CLK: indicates a 1-bit shift logic diagram (positive logic) A B CLR CLK Pin numbers shown are for the D, J, N, NS, PW, and W packages. R Q A R Q B R Q C R Q D R Q E R Q F R Q G R Q H

SN54HC164, SN74HC164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS115D – DECEMBER 1982 – REVISED AUGUST 2003 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 typical clear, shift, and clear sequence CLK A B CLR Q A Q B Q C Q D Q E Q F Q G Q H Clear Clear Serial InputsOutputs absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.

SN54HC164, SN74HC164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS115D – DECEMBER 1982 – REVISED AUGUST 2003

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions (see Note 3) SN54HC164 SN74HC164 UNIT MIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 2 5 6 2 5 6 V V High-level input voltage VCC = 2 V 1.5 1.5 VVIH High-level input voltage VCC = 4.5 V 3.15 3.15 VIH VCC = 6 V 4.2 4.2 V Low-level input voltage VCC = 2 V 0.5 0.5 VVIL Low-level input voltage VCC = 4.5 V 1.35 1.35 VIL VCC = 6 V 1.8 1.8 VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V t/v† Input transition rise/fall time VCC = 2 V 1000 1000 ns∆t/∆v† Input transition rise/fall time VCC = 4.5 V 500 500 ns VCC = 6 V 400 400 TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. † If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C SN54HC164 SN74HC164 UNITPARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX UNIT V V = V or V I = –20 A 2 V 1.9 1.998 1.9 1.9 VV V = V or V VVOH VI = VIH or VIL OH 6 V 5.9 5.999 5.9 5.9 VOH II H I L V V = V or V I = 20 A 2 V 0.002 0.1 0.1 0.1 VV V = V or V VVOL VI = VIH or VIL OL 6 V 0.001 0.1 0.1 0.1 VOL II H I L II VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA ICC VI = VCC or 0, IO = 0 6 V 8 160 80 µA C i 2 V to 6 V 3 10 10 10 pF

SN54HC164, SN74HC164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS115D – DECEMBER 1982 – REVISED AUGUST 2003 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC TA = 25°C SN54HC164 SN74HC164 UNITVCC MIN MAX MIN MAX MIN MAX UNIT f Clock frequency 2 V 6 4.2 5 MHzfclock Clock frequency 4.5 V 31 21 25 MHzclock

6 V 36 25 28

2 V 100 150 125

CLR low 4.5 V 20 30 25 nstw Pulse duration

6 V 17 25 21

2 V 80 120 100

CLK high or low 4.5 V 16 24 20

6 V 14 20 18

t Setup time before CLK↑ Data nst Setup time before CLK↑ Data 4.5 V 20 30 25 nstsu Setup time before CLK↑ nstsu Setup time before CLK↑ CLR inactive CLR inactive 4.5 V 20 30 25 t Hold time, data after CLK↑

2 V 5 5 5

nsth Hold time, data after CLK↑ 4.5 V 5 5 5 nsh

6 V 5 5 5

switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM TO VCC TA = 25°C SN54HC164 SN74HC164 UNITPARAMETER FROM (INPUT) TO (OUTPUT) VCC MIN TYP MAX MIN MAX MIN MAX UNIT f 2 V 6 10 4.2 5 MHzfmax 4.5 V 31 54 21 25 MHzmax

6 V 36 62 25 28

2 V 140 205 295 255

tPHL CLR Any Q 4.5 V 28 41 59 51 ns PHL

6 V 24 35 51 46

2 V 115 175 265 220

tpd CLK Any Q 4.5 V 23 35 53 44pd

6 V 20 30 45 38

t

2 V 38 75 110 95

nstt 4.5 V 8 15 22 19 nst

6 V 6 13 19 16

operating characteristics, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT C pd Power dissipation capacitance No load 135 pF

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

NOTES: A. C L includes probe and test-fixture capacitance. characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms

MCFP002A – JANUARY 1995 – REVISED FEBRUARY 2002 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 W (R-GDFP-F14) CERAMIC DUAL FLATPACK 0.360 (9,14) 0.250 (6,35) 141 0.235 (5,97) 0.004 (0,10) 0.026 (0,66)

4 Places

0.015 (0,38) 0.045 (1,14) 0.335 (8,51) 0.008 (0,20) 0.045 (1,14) Base and Seating Plane 0.005 (0,13) MIN 0.019 (0,48) 0.390 (9,91) 0.260 (6,60) 0.080 (2,03) 4040180-2/C 02/02 0.360 (9,14) 0.250 (6,35) 0.280 (7,11) MAX 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification only. E. Falls within MIL STD 1835 GDFP1-F14 and JEDEC MO-092AB

MLCC006B – OCTOBER 1996 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 4040140/D 10/96

28 TERMINAL SHOWN

B 0.358 (9,09) MAX (11,63) 0.560 (14,22) 0.560 0.458 0.858 (21,8) 1.063 (27,0) (14,22) ANO. OF MINMAX 0.358 0.660 0.761 0.458 0.342 (8,69) MIN (11,23) (16,26) 0.640 0.739 0.442 (9,09) (11,63) (16,76) 0.962 1.165 (23,83) 0.938 (28,99) 1.141 (24,43) (29,59) (19,32)(18,78) 0.020 (0,51) TERMINALS 0.080 (2,03) 0.064 (1,63) (7,80) 0.307 (10,31) 0.406 (12,58) 0.495 (12,58) 0.495 (21,6) 0.850 (26,6) 1.047 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.035 (0,89) 0.010 (0,25) 121314151618 17 432 0.020 (0,51) 0.010 (0,25) 12826 27 B SQ A SQ 0.055 (1,40) 0.045 (1,14) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004

/C0077/C0069/C0067/C0072/C0065/C0078/C0073/C0067/C0065/C0076 MPDI002C – JANUARY 1995 – REVISED DECEMBER 20002 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 N (R-PDIP-T) PLASTIC DUAL-IN-LINE PACKAGE BB AC AD 0.325 (8,26) 0.300 (7,62) 0.010 (0,25) NOM Gauge Plane 0.015 (0,38) 0.430 (10,92) MAX 1.060 (26,92) 0.940 (23,88) 0.920 0.850 0.775 0.745 (19,69) (18,92) 0.775 (19,69) (18,92) 0.745A MIN DIM A MAX PINS (23,37) (21,59) Seating Plane 14/18 PIN ONLY 20 pin vendor option 4040049/E 12/2002 0.070 (1,78) A 0.015 (0,38) 0.021 (0,53) 0.200 (5,08) MAX 0.125 (3,18) MIN 0.240 (6,10) 0.260 (6,60) M0.010 (0,25) 0.100 (2,54)

16 PINS SHOWN

D D D0.030 (0,76) 0.045 (1,14) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A). D. The 20 pin end lead shoulder width is a vendor option, either half or full width.

MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

8 PINS SHOWN

0.197 (5,00)A MAX A MIN (4,80) 0.189 0.337 (8,55) (8,75) 0.344 0.386 (9,80) (10,00) 0.394 16DIM PINS ** 4040047/E 09/01 0.069 (1,75) MAX Seating Plane 0.004 (0,10) 0.010 (0,25) 0.010 (0,25) 0.016 (0,40) 0.044 (1,12) 0.244 (6,20) 0.228 (5,80) 0.020 (0,51) 0.014 (0,35) 1 4 8 5 0.150 (3,81) 0.157 (4,00) 0.008 (0,20) NOM 0°– 8° Gage Plane A 0.004 (0,10) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). D. Falls within JEDEC MS-012

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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