MC54_1 MOTOROLA

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Technical content

/C0077/C0079/C0084/C0079/C0082/C0079/C0076/C0065 SEMICONDUCTOR TECHNICAL DATA 1 REV 7 Motorola, Inc. 1995 /C0072/C0101/C0120 /C0073/C0110/C0118/C0101/C0114/C0116/C0101/C0114 High–Performance Silicon–Gate CMOS The MC54/74HC04A is identical in pinout to the LS04 and the MC14069. The device inputs are compatible with Standard CMOS out- puts; with pullup resistors, they are compatible with LSTTL outputs. The device consists of six three–stage inverters.

  • Output Drive Capability: 10 LSTTL Loads
  • Outputs Directly Interface to CMOS, NMOS and TTL
  • Operating Voltage Range: 2 to 6V
  • Low Input Current: 1µA
  • High Noise Immunity Characteristic of CMOS Devices
  • In Compliance With the JEDEC Standard No. 7A Requirements
  • Chip Complexity: 36 FETs or 9 Equivalent Gates LOGIC DIAGRAM Y1A1 Y = A Pinout: 14–Lead Packages (Top View) 1314 12 11 10 9 8 21 3 4 5 6 7 VCC A6 Y6 A5 Y5 A4 Y4 A1 Y1 A2 Y2 A3 Y3 GND L H /C0077/C0067/C0053/C0052/C0047/C0055/C0052/C0072/C0067/C0048/C0052/C0065 FUNCTION TABLE Inputs Outputs A H L Y D SUFFIX SOIC PACKAGE CASE 751A–03 N SUFFIX PLASTIC PACKAGE CASE 646–06 DT SUFFIX TSSOP PACKAGE CASE 948G–01 J SUFFIX CERAMIC PACKAGE CASE 632–08

ORDERING INFORMATION

MOTOROLA High–Speed CMOS Logic Data DL129 — Rev 6 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS* ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Symbol ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Parameter ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ Value ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Unit ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ VCC ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Supply Voltage (Referenced to GND) ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ – 0.5 to + 7.0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ V ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Vin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Input Voltage (Referenced to GND) ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ – 0.5 to VCC + 0.5 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ V ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Vout ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Output Voltage (Referenced to GND) ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ – 0.5 to VCC + 0.5 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ V ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Iin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Input Current, per Pin ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ±/n63686172000000000000000020 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mA ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Iout ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Output Current, per Pin ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ±/n63686172000000000000000025 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mA ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ICC ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Supply Current, VCC and GND Pins ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ±/n63686172000000000000000050 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mA ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ PD ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Power Dissipation in Still Air, Plastic or Ceramic DIP† ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ 750 500 450 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mW ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Tstg ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Storage Temperature ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ – 65 to + 150 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ /C0095C ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ TL ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP , SOIC or TSSOP Package Ceramic DIP ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ 260 300 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ /C0095C *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. †Derating — Plastic DIP: – 10 mW//C0095C from 65/C0095 to 125/C0095C Ceramic DIP: – 10 mW//C0095C from 100/C0095 to 125/C0095C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ Symbol ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Parameter ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Min ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Max ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Unit ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VCC ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Supply Voltage (Referenced to GND) ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 2.0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 6.0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ V ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ Vin, Vout ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Input Voltage, Output Voltage (Referenced to GND) ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ VCC ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ V ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ TA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Operating T emperature, All Package Types ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ – 55 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ + 125 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ /C0095C ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tr, tf ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Input Rise and Fall Time V CC = 2.0 V (Figure 1) V CC = 4.5 V VCC = 6.0 V ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 1000 500 400 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance cir- cuit. For proper operation, Vin and Vout should be constrained to the range GND /C0118 (Vin or Vout) /C0118 VCC . Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC ). Unused outputs must be left open.

High–Speed CMOS Logic Data DL129 — Rev 6

3 MOTOROLA

DC CHARACTERISTICS (Voltages Referenced to GND) VCC V Guaranteed Limit Symbol Parameter Condition VCC V –55 to 25°C ≤85°C ≤125°C Unit VIH Minimum High–Level Input VoltageVout = 0.1V or VCC –0.1V |Iout| ≤ 20µA 2.0 3.0 4.5 6.0 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 V VIL Maximum Low–Level Input VoltageVout = 0.1V or VCC – 0.1V |Iout| ≤ 20µA 2.0 3.0 4.5 6.0 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 V VOH Minimum High–Level Output Voltage Vin = VIH or VIL |Iout| ≤ 20µA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V Vin =VIH or VIL |Iout| ≤ 2.4mA |Iout| ≤ 4.0mA |Iout| ≤ 5.2mA 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 VOL Maximum Low–Level Output Voltage Vin = VIH or VIL |Iout| ≤ 20µA 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V Vin = VIH or VIL |Iout| ≤ 2.4mA |Iout| ≤ 4.0mA |Iout| ≤ 5.2mA 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±/n6368617200000000000000000.1 ±/n6368617200000000000000001.0 ±/n6368617200000000000000001.0 µA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0µA 6.0 1.0 10 40 µA NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns) VCC V Guaranteed Limit Symbol Parameter VCC V –55 to 25°C ≤85°C ≤125°C Unit tPLH , tPHL Maximum Propagation Delay, Input A or B to Output Y (Figures 1 and 2) 2.0 3.0 4.5 6.0 110 ns tTLH , tTHL Maximum Output Transition Time, Any Output (Figures 1 and 2) 2.0 3.0 4.5 6.0 110 ns C in Maximum Input Capacitance 10 10 10 pF NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High– Speed CMOS Data Book (DL129/D). C PD Power Dissipation Capacitance (Per Inverter)* Typical @ 25°C, VCC = 5.0 V pFC PD Power Dissipation Capacitance (Per Inverter)* 20 pF * Used to determine the no–load dynamic power consumption: PD = CPD VCC 2f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

High–Speed CMOS Logic Data DL129 — Rev 6

5 MOTOROLA

CASE 632–08 ISSUE Y MIN MIN MAX MAX INCHES MILLIMETERS DIM A B C D F G J K L M N 0.785 0.280 0.200 0.020 0.065 0.015 0.170 15° 0.040 0.750 0.245 0.155 0.015 0.055 0.008 0.125 0.020 19.94 7.11 5.08 0.50 1.65 0.38 4.31 15° 1.01 19.05 6.23 3.94 0.39 1.40 0.21 3.18 0.51

0.100 BSC

0.300 BSC

2.54 BSC

7.62 BSC

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMESNION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. 14 8 1 7 -A- -B- -T- SEATING PLANE F G N K C L M 0.25 (0.010) T AM S 0.25 (0.010) T BM S J 14 PLD 14 PL N SUFFIX PLASTIC DIP PACKAGE CASE 646–06 ISSUE L NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. 1 7 14 8 B A F H G D K C N L J M SEATING PLANE DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.715 0.770 18.16 19.56 B 0.240 0.260 6.10 6.60 C 0.145 0.185 3.69 4.69 D 0.015 0.021 0.38 0.53 F 0.040 0.070 1.02 1.78 G 0.100 BSC 2.54 BSC H 0.052 0.095 1.32 2.41 J 0.008 0.015 0.20 0.38 K 0.115 0.135 2.92 3.43 L 0.300 BSC 7.62 BSC M 0 10 0 10 N 0.015 0.039 0.39 1.01 /C0095 /C0095 /C0095 /C0095

MOTOROLA High–Speed CMOS Logic Data DL129 — Rev 6 OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751A–03 ISSUE F MIN MIN MAX MAX MILLIMETERS INCHES DIM A B C D F G J K M P R 8.55 3.80 1.35 0.35 0.40 0.19 0.10 5.80 0.25 8.75 4.00 1.75 0.49 1.25 0.25 0.25 6.20 0.50 0.337 0.150 0.054 0.014 0.016 0.008 0.004 0.228 0.010 0.344 0.157 0.068 0.019 0.049 0.009 0.009 0.244 0.019 1.27 BSC 0.050 BSC NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. –A– –B– P 7 PL G C KSEATING PLANE D 14 PL M J R X 45° 1 7 814 0.25 (0.010) T B AM S S B0.25 (0.010)M M F DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948G–01 ISSUE O DIM MIN MAX MIN MAX INCHESMILLIMETERS A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0 8 0 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–. /C0095 /C0095 /C0095 /C0095 SU0.15 (0.006)T 2X L/2 SUM0.10 (0.004) V ST L –U– SEATING PLANE 0.10 (0.004) –T– ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ SECTION N–N DETAIL E J J1 K ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ DETAIL E F M –W– 0.25 (0.010) 814 PIN 1 IDENT. HG A D C B SU0.15 (0.006)T –V– 14X REFK N N

High–Speed CMOS Logic Data DL129 — Rev 6

7 MOTOROLA

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