74HC

74HC109 PHILIPS

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 9

Technical content

Product specification Supersedes data of December 1990 File under Integrated Circuits, IC06

1997 Nov 25

Dual JK flip-flop with set and reset; positive-edge trigger For a complete data sheet, please also download:

• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

1997 Nov 25 2

Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74HC/HCT109

FEATURES

• J,K inputs for easy D-type flip-flop
• Toggle flip-flop or “do nothing” mode
• Output capability: standard
• ICC category: flip-flops GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, J K flip-flops with individual J,K inputs, clock (CP) inputs, set (SD ) and reset (R D ) inputs; also complementary Q andQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J andK inputs control the state changes of the flip-flops as described in the mode select function table. The J andK inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The J K design allows operation as a D-type flip-flop by tying the J andK inputs together. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf= 6 ns Notes 1. C PD is used to determine the dynamic power dissipation (PD inµW): PD = CPD × VCC 2 × fi+∑ (CL × VCC 2 × fo) where: fi= input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC 2 × fo) = sum of outputs C L = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI= GND to VCC For HCT the condition is VI= GND to VCC − 1.5 V.

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC HCT tPHL / tPLH propagation delay C L = 15 pF; VCC = 5 V nCP to nQ, nQ1 5 1 7 n s nSD to nQ, nQ1 2 1 4 n s nR D to nQ, nQ1 2 1 5 n s fmax maximum clock frequency 75 61 MHz C I input capacitance 3.5 3.5 pF C PD power dissipation capacitance per flip-flop notes 1 and 2 20 22 pF

1997 Nov 25 3

Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74HC/HCT109 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 15 1 R D , 2R D asynchronous reset-direct input (active LOW) 2, 14, 3, 13 1J, 2J, 1 K, 2K synchronous inputs; flip-flops 1 and 2 4, 12 1CP, 2CP clock input (LOW-to-HIGH, edge-triggered) 5, 11 1 SD , 2SD asynchronous set-direct input (active LOW) 6, 10 1Q, 2Q true flip-flop outputs 7, 9 1 Q, 2Q complement flip-flop outputs

8 GND ground (0 V)

16 V CC positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

1997 Nov 25 4

Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74HC/HCT109 Fig.4 Functional diagram. FUNCTION TABLE Notes 1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition X = don’t care ↑ = LOW-to-HIGH CP transition OPERATING MODE INPUTS OUTPUTS SD R D CP J KQ Q asynchronous set L H X X X H L asynchronous reset H L X X X L H undetermined L L X X X H H toggle H H ↑ hl qq load “0” (reset) H H ↑ ll L H load “1” (set) H H ↑ hh H L hold “no change” H H ↑ lh q q PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. Fig.5 Logic diagram (one flip-flop). handbook, full pagewidth MBK217 C C C C C K J CP S R C C C C C Q Q

1997 Nov 25 5

Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74HC/HCT109 DC CHARACTERISTICS FOR 74HC For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: flip-flops AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf= 6 ns; CL = 50 pF SYMBOL PARAMETER Tamb (°C) TEST CONDITIONS 74HC UNIT VCC (V) WAVEFORMS +25 −40 to+85 −40 to+125 tPHL / tPLH propagation delay nCP to nQ, nQ 175 220 265 ns 2.0 4.5 6.0 Fig.6 t PLH propagation delay nSD to nQ 120 150 180 ns 2.0 4.5 6.0 Fig.7 t PHL propagation delay nSD to nQ 155 195 235 ns 2.0 4.5 6.0 Fig.7 t PHL propagation delay nR D to nQ 185 230 280 ns 2.0 4.5 6.0 Fig.7 t PLH propagation delay nR D to nQ 170 215 255 ns 2.0 4.5 6.0 Fig.7 t THL / tTLH output transition time 110 ns 2.0 4.5 6.0 Fig.6 t W clock pulse width HIGH or LOW 100 120 ns 2.0 4.5 6.0 Fig.6 t W set or reset pulse width HIGH or LOW 100 120 ns 2.0 4.5 6.0 Fig.7 t rem removal time nSD ,nR D to nCP 105 ns 2.0 4.5 6.0 Fig.7 t su set-up time nJ, nK to nCP 105 ns 2.0 4.5 6.0 Fig.6 t h hold time nJ, nK to nCP ns 2.0 4.5 6.0 Fig.6 f max maximum clock pulse frequency 6.0 5.0 4.0 MHz 2.0 4.5 6.0 Fig.6

1997 Nov 25 6

Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74HC/HCT109 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: flip-flops AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf= 6 ns; CL = 50 pF SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HCT VCC (V) WAVEFORMS+25 −40 to+85 −40 to+125 tPHL / tPLH propagation delay nCP to nQ, nQ 20 35 44 53 ns 4.5 Fig.6 tPLH propagation delay nSD to nQ 13 26 33 39 ns 4.5 Fig.7 tPHL propagation delay nSD to nQ 19 35 44 53 ns 4.5 Fig.7 tPHL propagation delay nR D to nQ 19 35 44 53 ns 4.5 Fig.7 tPLH propagation delay nR D to nQ 16 32 40 48 ns 4.5 Fig.7 tTHL / tTLH output transition time 7 15 19 22 ns 4.5 Fig.6 tW clock pulse width HIGH or LOW 18 9 23 27 ns 4.5 Fig.6 tW set or reset pulse width HIGH or LOW 16 8 20 24 ns 4.5 Fig.7 trem removal time nSD , nR D to nCP 16 8 20 24 ns 4.5 Fig.7 tsu set-up time nJ, nK to nCP 18 8 23 27 ns 4.5 Fig.6 th hold time nJ, nK to nCP 3 −3 3 3 ns 4.5 Fig.6 fmax maximum clock pulse frequency 27 55 22 18 MHz 4.5 Fig.6

1997 Nov 25 7

Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74HC/HCT109 AC WAVEFORMS Fig.6 Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nJ, nK to nCP set-up, the nCP to nJ, nK hold times, the output transition times and the maximum clock pulse frequency. The shaded areas indicate when the input is permitted to change for predictable output performance. handbook, full pagewidth MBK216 VM (1) nCP INPUT nSD INPUT nR D INPUT nQ OUTPUT nQ OUTPUT VM (1) VM (1) VM (1) VM (1) tW trem trem tW tPHLtPLH tPLHtPHL Fig.7 Waveforms showing the set (nSD ) and reset (nR D ) input to output (nQ, nQ) propagation delays, the set and reset pulse widths and the nR D , nSD to nCP removal time. (1) HC: VM = 50%; VI= GND to VCC . HCT: VM = 1.3 V; VI= GND to 3 V.

1997 Nov 25 8

Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74HC/HCT109 SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (T stg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. R EPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300°C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400°C, contact may be up to 5 seconds. SO, SSOP and TSSOP R EFLOW SOLDERING Reflow soldering techniques are suitable for all SO, SSOP and TSSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250°C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. W AVE SOLDERING Wave soldering can be used for all SO packages. Wave soldering isnot recommended for SSOP and TSSOP packages, because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering is used -and cannot be avoided for SSOP and TSSOP packages - the following conditions must be observed:

• A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used.
• The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions:
• Only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1).
• Do not consider wave soldering TSSOP packages with 48 leads or more, that is TSSOP48 (SOT362-1) and TSSOP56 (SOT364-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260°C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150°C within 6 seconds. Typical dwell time is 4 seconds at 250°C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. R EPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonally- opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300°C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320°C.

1997 Nov 25 9

Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74HC/HCT109 DEFINITIONS LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.