74ACT11112 TI

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Technical content

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET SCAS064A – D3339, JUNE 1989 – REVISED APRIL 1993 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Copyright  1993, Texas Instruments Incorporated 2–1

  • Inputs Are TTL-Voltage Compatible
  • Fully Buffered to Offer Maximum Isolation From External Disturbance
  • Flow-Through Architecture Optimizes PCB Layout
  • Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
  • EPIC/C0116 (Enhanced-Performance Implanted CMOS) 1-/C0109m Process
  • 500-mA Typical Latch-Up Immunity at 125°C
  • Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs

description

This device contains two independent J-K negative-edge-triggered flip-flops. A low level at the PRE or CLR input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high. The 74ACT11112 is characterized for operation from – 40°C to 85°C. FUNCTION TABLE INPUTS OUTPUTS PRE CLR CLK J K Q Q L H X X X H L H LX X X L H L LX X X H /C0123H /C0123 H H ↓ LL Q 0 Q 0 H H ↓ HLH L H H ↓ LHL H H H ↓ H H TOGGLE H H H X X Q 0 Q 0 † This configuration is nonstable; that is, it will not persist when either PRE or CLR returns to the inactive (high) level. D OR N PACKAGE (TOP VIEW) 1PRE GND 2PRE 1CLK 1CLR VCC 2CLR 2CLK EPIC is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET SCAS064A – D3339, JUNE 1989 – REVISED APRIL 1993 POST OFFICE BOX 655303 • DALLAS, TEXAS 752652–2 logic symbol†

2 CLR

2 PRE

1 CLK

1 PRE

1 CLR

S R 1J1J 112K S R † This symbol is in accordnace with ANSI/IEEE Std 91-1984 and IEC Publication 617-42. logic diagram, each flip-flop (positive logic) TGTG TG C C C C Q C C PRE J K CLK CLR C C C C Q TG absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET SCAS064A – D3339, JUNE 1989 – REVISED APRIL 1993 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–3 recommended operating conditions MIN MAX UNIT VCC Supply voltage 4.5 5.5 V VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V VI Input voltage 0 VCC V VO Output voltage 0 VCC V IOH High-level output current –24 mA IOL Low-level output current 24 mA /C0068t//C0068v Input transition rise or fall rate 0 10 ns/V TA Operating free-air temperature –4 0 85 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C MIN MAX UNITPARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX UNIT IOH =5 0 /C0109A 4.5 V 4.4 4.4 IOH = –50 /C0109A 5.5 V 5.4 5.4 VOH IOH =2 4 m A 4.5 V 3.94 3.8 V IOH = –24 mA 5.5 V 4.94 4.8 IOH = – 75 mA† 5.5 V 3.85 IOL =5 0/C0109A 4.5 V 0.1 0.1 IOL = 50 /C0109A 5.5 V 0.1 0.1 VOL IOL =2 4m A 4.5 V 0.36 0.44 V IOL = 24 mA 5.5 V 0.36 0.44 IOL = 75 mA† 5.5 V 1.65 II VI = VCC or GND 5.5 V ± 0.1 ±1 /C0109A ICC VI = VCC or GND, I O = 0 5.5 V 4 40 /C0109A /C0068ICC ‡ VI = VCC or GND 5.5 V 0.9 1 mA C i VI = VCC or GND 5 V 3.5 pF † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. ‡ This parameter is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC . timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX UNIT MIN MAX MIN MAX UNIT fclock Clock frequency 125 125 MHz t Pulse duration PRE or CLR low 4 4 nstw Pulse duration CLK high or low 4 4 ns t Setup time before CLK↓ Data high or low 3.5 4.5 nstsu Setup time before CLK ↓ PRE or CLR inactive 2 2 ns th Hold time after CLK↓ 1.5 1.5 ns

NOTES: A. C L includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 W , tr = 3 ns, tf = 3 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms

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