CD74HC221 TI

Document overview

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Technical content

Features

  • Overriding RESET Terminates Output Pulse
  • Triggering from the Leading or Trailing Edge
  • Q and Q Buffered Outputs
  • Separate Resets
  • Wide Range of Output-Pulse Widths
  • Schmitt Trigger on B Inputs
  • Fanout (Over Temperature Range)
  • Wide Operating Temperature Range . . . -55 oC to 125oC
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types - 2V to 6V Operation - High Noise Immunity: N IL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, V IL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il≤ 1µA at VOL , VOH

Description

The CD74HC221, and CH74HCT221 are dual monostable multivibrators with reset. An external resistor (RX) and an external capacitor (CX) control the timing and the accuracy for the circuit. Adjustment of RX and CX provides a wide range of output pulse widths from the Q andQ terminals. Pulse triggering on the B input occurs at a particular voltage level and is not related to the rise and fall time of the trigger pulse. Once triggered, the outputs are independent of further trigger inputs on A and B. The output pulse can be terminated by a LOW level on the Reset (R) pin. Trailing Edge triggering (A) and leading-edge-triggering (B) inputs are provided for triggering from either edge of the input pulse. On power up, the IC is reset. If either Mono is not used each input (on the unused device) must be terminated either high or low. The minimum value of external resistance, R X, is typically 500Ω . The minimum value of external capacitance, CX, is 0pF . The calculation for the pulse width is tW = 0.7 RXC X at VCC = 4.5V. Pinout CD74HC221, CD74HCT221 (PDIP, SOIC) TOP VIEW

Ordering Information

PART NUMBER TEMP. RANGE ( oC) PACKAGE PKG. NO. CD74HC221E -55 to 125 16 Ld PDIP E16.3 CD74HCT221E -55 to 125 16 Ld PDIP E16.3 CD74HC221M -55 to 125 16 Ld SOIC M16.15 CD74HCT221M -55 to 125 16 Ld SOIC M16.15 NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer or die are available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. 2C X GND 2C XR X VCC 1C X 1C XR X November 1997 - Revised April 1999 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1997 CD74HC221, CD74HCT221 High Speed CMOS Logic Dual Monostable Multivibrator with Reset File Number 1670.1 [ /Title (CD74 HC221 CD74 HCT22 /Sub- ject (High Speed CMOS Logic Dual Monos table Multi-

L ↑ H ↓ HH XXLLH LH ↑ (Note 3) (Note 3) NOTE: H = High Voltage Level, L = Low Voltage Level, X = Irrelevant,↑ = Transition from Low to High Level,↓ = Transition from High to Low Level, = One High Level Pulse, = One Low Level Pulse 3. For this combination the reset input must be low and the following sequence must be used: pin 1 (or 9) must be set high or pin 2 (or 10) set low; then pin 1 (or 9) must be low and pin 2 (or 10) set high. Now the reset input goes from low-to-high and the device will be triggered. MONO 2 VCC 2C X 2C XR X MONO 1 VCC 14 15 1C X 1C XR X 1C X 1R X 2C X 2R X CD74HC221, CD74HCT221

1 (9) A 2 (10) B S QM QM R S MASK FF MAIN FF QQ R 3 (11) 4 (12) (13) 5 QQ C P Q R QD C C VCC R D C QC RESET FF VCC PP PULLDOWN FFN MIRROR VOLTAGE VCC P OP AMP P N GND 15 (7) R XC X VCC C X C X 14 (6) OP AMP R R XN CD74HC221, CD74HCT221

Absolute Maximum Ratings Thermal Information DC Input Diode Current, IIK DC Output Diode Current, IOK DC Drain Current, per Output, IO DC Output Source or Sink Current per Output Pin, IO Operating Conditions Supply Voltage Range, VCC DC Input or Output Voltage, V Input Rise and Fall Time, tr, tf on InputsA andR Input Rise and Fall Time, t r, tf on Input B Thermal Resistance (Typical, Note 4)θ JA (oC/W) θJC (oC/W) oC (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 4. θJA is measured with the component mounted on an evaluation PC board in free air. PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40 oC TO 85oC -55 oCT O1 2 5oC UNITSVI(V) I O (mA) MIN TYP MAX MIN MAX MIN MAX HC TYPES High Level Input Voltage V Low Level Input Voltage High Level Output Voltage CMOS Loads V OH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V High Level Output Voltage TTL Loads - - --- - - - - V Low Level Output Voltage CMOS Loads V OL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V Low Level Output Voltage TTL Loads - - --- - - - - V CD74HC221, CD74HCT221

0 6 - - 8 - 80 - 160 µA HCT TYPES High Level Input Voltage VIH - - 4.5 to 5.5 2-- 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 High Level Output Voltage CMOS Loads V High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads V Low Level Output Voltage TTL Loads Input Leakage Current I I VCC and GND Quiescent Device Current ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA Additional Quiescent Device Current Per Input Pin: 1 Unit Load ΔI CC VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40 oC TO 85oC -55 oCT O1 2 5oC UNITSVI(V) I O (mA) MIN TYP MAX MIN MAX MIN MAX HCT Input Loading Table INPUT UNIT LOADS All Inputs 0.3 NOTE: Unit Load isΔICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC. Prerequisite For Switching Function PARAMETER SYMBOL V CC (V) 25oC -40 oC TO 85oC -55 oC TO 125oC UNITSMIN TYP MAX MIN MAX MIN MAX HC TYPES Input Pulse Width A tWL 27 0- -9 0- 1 0 5 -n s 4.5 14 - - 18 - 21 - ns 61 2- -1 5-1 8-n s Input Pulse Width B tWH 27 0- -9 0- 1 0 5 -n s 4.5 14 - - 18 - 21 - ns 61 2- -1 5-1 8-n s CD74HC221, CD74HCT221

tWL 27 0- -9 0- 1 0 5 -n s 4.5 14 - - 18 - 21 - ns 61 2- -1 5-1 8-n s Recovery Time R toA or B tSU 20--0-0- n s 4 . 5 0--0-0- n s 60--0-0- n s Output Pulse Width Q orQ C X = 0.1µF RX = 10kΩ tW 5 630 - 770 602 798 595 805 µs Output Pulse Width Q or Q C X = 28pF, RX = 2kΩ C X = 1000pF, RX = 2kΩ tW 4 . 5 - 1 . 5 ----- µs C X = 1000pF, RX = 10kΩ tW 4 . 5 -7----- µs HCT TYPES Input Pulse Width A tWL 4.5 14 - - 18 - 21 - ns Input Pulse Width B tWH 4.5 14 - - 18 - 21 - ns Input Pulse Width Reset tWL 4.5 18 - - 23 - 27 - ns Recovery Time R toA or B tSU 4 . 5 0--0-0- n s Output Pulse Width Q orQ C X = 0.1µF RX = 10kΩ tW 5 630 - 770 602 798 595 805 µs Output Pulse Width Q or Q C X = 28pF, RX = 2kΩ C X = 1000pF, RX = 2kΩ tW 4 . 5 - 1 . 5 ----- µs C X = 1000pF, RX = 10kΩ tW 4 . 5 -7----- µs Switching SpecificationsInput tr, tf = 6ns PARAMETER SYMBOL TEST CONDITIONS V CC (V) 25oC -40oC TO 85oC -55oC TO 125oC UNITSMIN TYP MAX MIN MAX MIN MAX HC TYPES Propagation Delay, TriggerA, B,R to Q tPLH C L = 50pF 2 - - 210 - 265 - 315 ns C L = 50pF 4.5 - - 42 - 53 - 63 ns C L = 50pF 6 - - 36 - 45 - 54 ns C L = 15pF 5 - 18 - - - - - ns Propagation Delay, TriggerA, B,R toQ tPHL C L = 50pF 2 - - 170 - 215 - 255 ns C L = 50pF 4.5 - - 34 - 43 - 51 ns C L = 50pF 6 - - 29 - 37 - 43 ns C L = 15pF 5 - 14 - - - - - ns Prerequisite For Switching Function (Continued) PARAMETER SYMBOL V CC (V) 25oC -40 oC TO 85oC -55 oC TO 125oC UNITSMIN TYP MAX MIN MAX MIN MAX CD74HC221, CD74HCT221

Propagation Delay, R to Q tPLH C L = 50pF 2 - - 160 - 200 - 240 ns 4.5 - - 32 - 40 - 48 ns 6 - - 27 - 34 - 41 ns Propagation Delay, R toQ tPHL C L = 50pF 2 - - 180 - 225 - 270 ns 4.5 - - 36 - 45 - 54 ns 6 - - 31 - 38 - 46 ns Output Transition Time t TLH , tTHL C L = 50pF 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns Input Capacitance C IN - - - - 10 - 10 - 10 pF Pulse Width Match Between Circuits in the Same Package C X = 1000pF, RX = 10kΩ - 4.5 to 5.5 - ±2- - - - - % Power Dissipation Capacitance (Notes 5, 6) HCT TYPES Propagation Delay, TriggerA, B,R to Q tPLH C L = 50pF 4.5 - - 42 - - - 63 ns C L = 15pF 5 - 18 - - - - - ns Propagation Delay, TriggerA, B,R toQ tPHL C L = 50pF 4.5 - - 34 - 43 - 51 ns C L = 15pF 5 - 14 - - - - - ns Propagation Delay, R to Q tPLH C L = 50pF 4.5 - - 38 - - - 57 ns Propagation Delay, R toQ tPHL C L = 50pF 4.5 - - 37 - - - 56 ns Output Transition Time t TLH , tTHL C L = 50pF 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns Input Capacitance C IN - - - - 10 - 10 - 10 pF Pulse Width Match Between Circuits in the Same Package C X = 1000pF, RX = 10kΩ - 4.5 to 5.5 - ±2- - - - - % Power Dissipation Capacitance (Notes 5, 6) NOTES: 5. CPD is used to determine the dynamic power consumption, per multivibrator. 6. PD = (CPD + CL) VCC 2 fi +Σ where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage. Switching SpecificationsInput tr, tf = 6ns (Continued) PARAMETER SYMBOL TEST CONDITIONS V CC (V) 25oC -40oC TO 85oC -55oC TO 125oC UNITSMIN TYP MAX MIN MAX MIN MAX CD74HC221, CD74HCT221

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