71V016SA RENESAS
Document overview
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Technical content
Features
◆◆◆◆◆ 64K x 16 advanced high-speed CMOS Static RAM ◆◆◆◆◆ Equal access and cycle times — Commercial: 10/12/15/20ns — Industrial: 10/12/15/20ns ◆◆◆◆◆ One Chip Select plus one Output Enable pin ◆◆◆◆◆ Bidirectional data inputs and outputs directly LVTTL-compatible ◆◆◆◆◆ Low power consumption via chip deselect ◆◆◆◆◆ Upper and Lower Byte Enable Pins ◆◆◆◆◆ Single 3.3V power supply ◆◆◆◆◆ Available in 44-pin Plastic SOJ, 44-pin TSOP, and 48-Ball Plastic FBGA packages ◆◆◆◆◆ Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆◆◆◆◆ Green parts available, see ordering information
Description
The IDT71V016 is a 1,048,576-bit high-speed Static RAM organized as 64K x 16. It is fabricated using high-performance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for high-speed memory needs. The IDT71V016 has an output enable pin which operates as fast as 5ns, with address access times as fast as 10ns. All bidirectional inputs and outputs of the IDT71V016 are LVTTL compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71V016 is packaged in a JEDEC standard 44-pin Plastic SOJ, a 44-pin TSOP Type II, and a 48-ball plastic 7 x 7 mm FBGA. Functional Block Diagram Output Enable Buffer Address Buffers Chip Enable Buffer Write Enable Buffer Byte Enable Buffers OE A0 –A 15 Row / Column Decoders CS WE BHE BLE 64K x 16 Memory Array Sense Amps and Write Drivers Low Byte I/O Buffer I/O8 I/O15 I/O7 I/O0 3834 drw 01 High Byte I/O Buffer 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit) Commercial an d Industrial Temperature Ranges
Jun.23.20 123456 A BLE OE A0 A1 A2 NC BI / O 8 BHE A3 A4 CS I/O0 CI / O 9 I/O10 A5 A6 I/O1 I/O2 DV SS I/O11 NC A 7 I/O3 VDD EV DD I/O12 NC NC I/O 4 VSS FI / O 14 I/O13 A14 A15 I/O5 I/O6 G I/O 15 NC A 12 A13 WE I/O7 HN C A 8 A9 A10 A11 NC 3834 tbl 02a Pin Configurations - PBG44, PHG44(1) SOJ/TSOP Top View Pin Description Truth Table (1) I/O NC A12 A13 A14 A15 WE I/O6 I/O5 I/O4 VSS VDD I/O3 I/O2 I/O1 I/O0 CS A4 44 A OE BHE BLE I/O I/O14 I/O13 I/O12 VSS VDD I/O11 I/O10 I/O9 I/O8 A10 A11 NC NC PBG44 PHG44 3834 drw 02 71V016SA NOTE: 1. H = V IH, L = VIL, X = Don't care. A 0 – A 15 Address Inputs Input CS Chip Select Input WE Write Enable Input OE Output Enable Input BHE High Byte Enable Input BLE Low Byte Enable Input I/O 0 – I/O 15 Data Input/Output I/O V DD 3.3V Power Power V SS Ground Gnd 3834 tbl 01 CS OE WE BLE BHE I/O0-I/O7 I/O8-I/O15 Function H X X X X High-Z High-Z Deselected – Standby LLH L H D A T A OUT High-Z Low Byte Read L L H H L High-Z DATA OUT High Byte Read LLH L L D A T A OUT DATAOUT Word Read LX L L L D A T A IN DATAIN Word Write LX L L H D A T A IN High-Z Low Byte Write L X L H L High-Z DATA IN High Byte Write L H H X X High-Z High-Z Outputs Disabled L X X H H High-Z High-Z Outputs Disabled 3834 tbl 02 FBGA (BF48, BFG48)(1) Top View NOTE: 1. This text does not indicate orientation of actual part-marking. NOTE: 1. This text does not indicate orientation of actual part-marking.
71V016SA, 3.3V CMOS Static RAM Jun.23.20 Symbol Parameter 71V016SA10 71V016SA12 71V016SA15 71V016SA20 UnitCom'l Ind'l Com'l Ind'l Com'l Ind'l Com'l Ind'l ICC Dynamic Operating Current CS ≤ VLC, Outputs Open, V DD = Max., f = f MAX(3) Max. 160 170 150 160 130 130 120 120 mA ISB Dynamic Standby Power Supply Current CS ≥ VHC, Outputs Open, V DD = Max., f = f MAX(3) 45 50 40 45 35 35 30 30 mA ISB1 Full Standby Power Supply Current (static) CS ≥ VHC, Outputs Open, V DD = Max., f = 0 (3) 10 10 10 10 10 10 10 10 mA 3834 tbl 08 Absolute Maximum Ratings (1) Recommended Operating Temperature and Supply Voltage (VDD = Min. to Max., Commercial and Industrial Temperature Ranges) Capacitance (TA = +25°C, f = 1.0MHz, SOJ package) Recommended DC Operating Conditions (VDD = Min. to Max., V LC = 0.2V, V HC = VDD – 0.2V) NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. NOTES: 1. For 71V016SA10 only. 2. For all speed grades except 71V016SA10. 3. V IH (max.) = VDD+2V for pulse width less than 5ns, once per cycle. 4. V IL (min.) = –2V for pulse width less than 5ns, once per cycle.NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. NOTES: 1. All values are maximum guaranteed values. 2. All inputs switch between 0.2V (Low) and V DD – 0.2V (High). 3. f MAX = 1/t RC (all address inputs are cycling at f MAX); f = 0 means no address input lines are changing . 4. Typical values are based on characterization data for H step only measured at 3.3V, 25°C and with equal read and write cycles . Symbol Rating Value Unit VDD Supply Voltage Relative to V SS –0.5 to +4.6 V VIN, VOUT Terminal Voltage Relative to V SS –0.5 to V DD+0.5 V TBIAS Temperature Under Bias –55 to +125 oC TSTG Storage T emperature –55 to +125 oC PT Power Dissipation 1.25 W IOUT DC Output Current 50 mA 3834 tbl 03 Grade Temperature V SS VDD Commercial 0°C to +70°C 0V See Below Industrial -40°C to +85°C 0V See Below 3834 tbl 04 Symbol Parameter Min. Typ. Max. Unit VDD(1 ) Supply Voltage 3.15 3.3 3.6 V VDD(2 ) Supply Voltage 3.0 3.3 3.6 V Vss Ground 0 0 0 V VIH Input High Voltage 2.0 ____ VDD+0.3(3) V VIL Input Low Voltage –0.3 (4) ____ 0.8 V 3834 tbl 05 Symbol Parameter (1 ) Conditions Max. Unit CIN Input Capacitance V IN = 3dV 6 pF CI/O I/O Capacitance V OUT = 3dV 7 pF 3834 tbl 06 Symbol Parameter Test Condition IDT71V016SA UnitMin. Max. |ILI| Input Leakage Current V DD = Max., V IN = V SS to V DD __ _ 5µ A |ILO| Output Leakage Current V DD = Max., CS = V IH, VOUT = V SS to V DD __ _ 5µ A VOL Output Low Voltage I OL = 8mA, V DD = Min. __ _ 0.4 V VOH Output High Voltage I OH = –4mA, V DD = Min. 2.4 ___ V 3834 tbl 07
Figure 3. Output Capacitive Derating Figure 1. AC Test Load Figure 2. AC Test Load *Including jig and scope capacitance.
71V016SA, 3.3V CMOS Static RAM Jun.23.20 71V016SA10 71V016SA12 71V016SA15 71V016SA20 READ CYCLE tOH Output Hold from Address Change 4 — 4 — 4 — 4 — ns tBE Byte Enable Low to Output Valid — 5 — 6 — 7 ____ 8n s WRITE CYCLE 3834 tbl 10 Timing Waveform of Read Cycle No. 1 (1,2,3) NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. OE, BHE, and BLE are LOW. DATAOUT ADDRESS 3834 drw 06 tRC tAA tOH tOH DATAOUT VALIDPREVIOUS DATAOUT VALID NOTE: 1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
71V016SA, 3.3V CMOS Static RAM Jun.23.20 Timing Waveform of Read Cycle No. 2 (1) NOTES: 1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE. 2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured ±200mV from steady state. Timing Waveform of Write Cycle No. 1 ( WE Controlled Timing)(1,2,4) NOTES: 1. WE is HIGH for Read Cycle. 2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter. 3. Transition is measured ±200mV from steady state. ADDRESS OE CS DATAOUT 3834 drw 07 (3) (3) (3) DATA VALID tAA tRC tOE tOLZ tCHZ tOHZ OUT BHE, BLE (3) tACS (3) tBLZ tCLZ (2) tBE tOH tBHZ (3)(2) ADDRESS CS DATAIN 3834 drw 08 (5) (5) (5) DATAIN VALID tWC tAS tWHZ (2)tCW tCHZ tOW tWR WE tAW DATAOUT tDW tDH PREVIOUS DATA VALID DATA VALID BHE, BLE tBW tWP (5) tBHZ (3)
71V016SA, 3.3V CMOS Static RAM Jun.23.20 Timing Waveform of Write Cycle No. 2 ( CS Controlled Timing)(1,4) NOTES: 1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE. 2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured ±200mV from steady state. Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing)(1,4) ADDRESS CS DATAIN 3834 drw 09 DATAIN VALID tWC tAS (2)tCW tWR WE tAW DATAOUT tDW tDH BHE, BLE tBW tWP ADDRESS CS DATAIN 3834 drw 10 DATAIN VALID tWC tAS (2)tCW tWR WE tAW DATAOUT tDW tDH BHE, BLE tBW tWP
71V016SA, 3.3V CMOS Static RAM Jun.23.20
Ordering Information
X Process/ Temperature Range Blank I(1) Commercial (0°C to +70°C) Industrial (-40°C to +85°C) Y PH BF 400-mil SOJ (PBG44) 400-mil TSOP Type II (PHG44) 7.0 x 7.0 mm FBGA (BF48, BFG48) 71V016 Device Type Speed in nanoseconds 3834 drw 11 X G Green Tube or Tray Tape and Reel X Blank (2) NOTE: 1. Contact your local sales office for industrial temp. range for other speeds, packages and powers. 2. Green parts available. For specific speeds, packages and powers contact your local sales office. Note that information regarding recently obsoleted parts are included in this datasheet for customer convenience.
IDT71V016SA, 3.3V CMOS Static RAM Jun.15.20 Orderable Part Information Speed (ns) Orderable Part ID Pkg. Code Pkg. Type Temp. Grade 10 71V016SA10BF BF48 CABGA C 71V016SA10BF8 BF48 CABGA C 71V016SA10BFG BFG48 CABGA C 71V016SA10BFG8 BFG48 CABGA C 71V016SA10BFGI BFG48 CABGA I 71V016SA10BFGI8 BFG48 CABGA I 71V016SA10PHG PHG44 TSOP C 71V016SA10PHG8 PHG44 TSOP C 71V016SA10PHGI PHG44 TSOP I 71V016SA10PHGI8 PHG44 TSOP I 71V016SA10YG PBG44 SOJ C 71V016SA10YG8 PBG44 SOJ C 12 71V016SA12BF BF48 CABGA C 71V016SA12BF8 BF48 CABGA C 71V016SA12BFG BFG48 CABGA C 71V016SA12BFG8 BFG48 CABGA C 71V016SA12BFGI BFG48 CABGA I 71V016SA12BFGI8 BFG48 CABGA I 71V016SA12BFI BF48 CABGA I 71V016SA12BFI8 BF48 CABGA I 71V016SA12PHG PHG44 TSOP C 71V016SA12PHG8 PHG44 TSOP C 71V016SA12PHGI PHG44 TSOP I 71V016SA12PHGI8 PHG44 TSOP I 71V016SA12YG PBG44 SOJ C 71V016SA12YG8 PBG44 SOJ C 71V016SA12YGI PBG44 SOJ I 71V016SA12YGI8 PBG44 SOJ I Speed (ns) Orderable Part ID Pkg. Code Pkg. Type Temp. Grade 15 71V016SA15BF BF48 CABGA C 71V016SA15BF8 BF48 CABGA C 71V016SA15BFG BFG48 CABGA C 71V016SA15BFG8 BFG48 CABGA C 71V016SA15BFGI BFG48 CABGA I 71V016SA15BFGI8 BFG48 CABGA I 71V016SA15BFI BF48 CABGA I 71V016SA15BFI8 BF48 CABGA I 71V016SA15PHG PHG44 TSOP C 71V016SA15PHG8 PHG44 TSOP C 71V016SA15PHGI PHG44 TSOP I 71V016SA15PHGI8 PHG44 TSOP I 71V016SA15YG PBG44 SOJ C 71V016SA15YG8 PBG44 SOJ C 71V016SA15YGI PBG44 SOJ I 71V016SA15YGI8 PBG44 SOJ I 20 71V016SA20BF BF48 CABGA C 71V016SA20BF8 BF48 CABGA C 71V016SA20BFG BFG48 CABGA C 71V016SA20BFG8 BFG48 CABGA C 71V016SA20BFGI BFG48 CABGA I 71V016SA20BFGI8 BFG48 CABGA I 71V016SA20BFI BF48 CABGA I 71V016SA20BFI8 BF48 CABGA I 71V016SA20PHG PHG44 TSOP C 71V016SA20PHG8 PHG44 TSOP C 71V016SA20PHGI PHG44 TSOP I 71V016SA20PHGI8 PHG44 TSOP I 71V016SA20YG PBG44 SOJ C 71V016SA20YG8 PBG44 SOJ C 71V016SA20YGI PBG44 SOJ I 71V016SA20YGI8 PBG44 SOJ I
71V016SA, 3.3V CMOS Static RAM Jun.23.20 Datasheet Document History 01/07/00 Updated to new format Pg. 1, 3, 5, 8 Added Industrial Temperature range offerings Pg. 2 Numbered I/Os and address pins on FBGA Top View Pg. 6 Revised footnotes on Write Cycle No. 1 diagram Pg. 7 Revised footnotes on Write Cycle No. 2 and No. 3 diagrams Pg. 9 Added Datasheet Document History 08/30/00 Pg. 3 Tighten I CC and ISB. Pg. 5 Tighten t CLZ, tCHZ, tOHZ, tBHZ and tWHZ 08/22/01 Pg. 8 Removed footnote "available in 15ns and 20ns only" 06/20/02 Pg. 8 Added tape and reel field to ordering information 01/30/04 Pg. 8 Added "Restricted hazardous substance device" to ordering information. 09/27/06 Pg. 8 Corrected ordering information, changed position of I and G. 02/14/07 Pg.8 Added H step generation to data sheet ordering information. 06/26/07 Pg.3 Changed typical parameters for ICC, DC electrical characteristics table. 10/13/08 Pg.8 Removed "IDT" from orderable part number 10/11/11 Pg.1,8 Updated datasheet with removal of Obsolete HSA part number. 08/13/13 Pg.1,3,5,8 Added 10ns for Industrial Temperature range offerings. 06/23/20 Pg.1 - 9 Rebranded as Renesas datasheet Pg.1 & 8 Updated Industrial temp and Green availability Pg.2 & 8 Updated package codes Pg.9 Added Orderable Part Information tables
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