70T3509M RENESAS
Document overview
- Manufacturer or author: Renesa Electronics Corporation
- PDF pages: 24
Technical content
Feb.28.22 Functional Block Diagram HIGH-SPEED 2.5V 1024K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE 70T3509M REPEATR A0R CNTENR ADSR Dout0-8_R Dout9-17_R I/O0R - I/O35RDin_R ADDR_R OER BE3R BE2R BE1R BE0R R/WR CE0R CE1R1 FT/PIPER1a 0a1b 0b1c 0c1d 0d dcba CLKR Counter/ Address Reg. dcba 0d 1d0c 1c0b 1b0a 1a B W R B W R B W R FT/PIPER Counter/ Address Reg. CNTENL ADSL REPEATL Dout0-8_L Dout9-17_L Dout18-26_L Dout27-35_L Dout18-26_R Dout27-35_R B W L B W L B W L B W L I/O0L - I/O35L A19L A0L Din_L ADDR_L OEL 5682 drw 01 BE3L BE2L BE1L BE0L R/WL CE0L CE1L 1024K x 36 MEMORY ARRAY CLKL abcd FT/PIPEL 0/1 1d 0d 1c 0c 1b 0b 1a 0a B W R JTAG TCK TRST TMS TDO TDI 0d 1d0c 1c0b 1b0a 1a ab cd FT/PIPEL 1/01/0 INTERRUPT LOGIC R/WL CE 0 L CE1L R/WR CE0 R CE1R INTL INTR ZZ CONTROL LOGIC ZZL(1) ZZR(1) A19R (2)(2) Features: ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location ◆ High-speed data access – Commercial: 4.2ns (133MHz)(max.) – Industrial: 4.2ns (133MHz)(max.) ◆ Selectable Pipelined or Flow-Through output mode ◆ Counter enable and repeat features ◆ Interrupt Flags ◆ Full synchronous operation on both ports – 7.5ns cycle time, 133MHz operation (9.5Gbps bandwidth) – 1.5ns setup to clock and 0.5ns hold on all control, data, and address inputs @ 133MHz – Fast 4.2ns clock to data out NOTES: 1. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/ FTx and OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode. 2. See Truth Table I for Functionality. – Data input, address, byte enable and control registers – Self-timed write allows fast cycle time ◆ Separate byte controls for multiplexed bus and bus matching compatibility ◆ Dual Cycle Deselect (DCD) for Pipelined Output Mode ◆ 2.5V (±100mV) power supply for core ◆ LVTTL compatible, selectable 3.3V (±150mV) or 2.5V (±100mV) power supply for I/Os and control signals on each port ◆ Includes JTAG functionality ◆ Available in a 256-pin Ball Grid Array (BGA) ◆ Common BGA footprint provides design flexibility over seven density generations (512K to 36M-bit) ◆ Green parts available, see ordering information
6.42 70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Range s Feb.28.22 Description: The IDT70T3509M is a high-speed 1024K x 36 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70T3509M has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE 0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70T3509M can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (V DD) is at 2.5V. E16 I/O14R D16 I/O16R C16 I/O16L B16 NC A16 NC A15 NC B15 I/O17L C15 I/O17R D15 I/O15L E15 I/O14L E14 I/O13L D14 I/O15R D13 VDD C12 A6L C14 OPTL B14 VDD A14 A0L A12 A5L B12 A4L C11 ADSL D12 VDDQR D11 VDDQR C10 CLKL B11 REPEATL A11 CNTENL VDDQR BE1L CE1L VDDQL BE0L CE0L D10 VDDQL A7L BE3L BE2L B13 A1L A13 A2L A10 OEL VDDQR A9L A8L A12L A10L VDDQL A14L A15L A13L VDDQL A18L PIPE/FTL A19L TDO VSS I/O20L I/O19R I/O19L NC TDI NC I/O18L I/O18R I/O20R I/O21R I/O21L I/O22L VDDQL I/O23L I/O22R I/O23R VDDQL I/O24R I/O24L I/O25L VDDQR I/O26L I/O25R I/O26R VDDQR I/O27L I/O28R I/O27R VDDQL I/O29R I/O29L I/O28L VDDQL I/O30L I/O31R I/O30R VDDQR I/O32R I/O32L I/O31L VDDQR I/O33L I/O34R I/O33R I/O35R I/O34L TMS I/O35L NC TRST A18R NC TCK A19R A13R A15R P12 A6R BE1R BE0R BE3R BE2R P10 CLKR T11 CNTENR P11 ADSR R12 A4R T12 A5R P13 A3R A7R R13 A1R T13 A2R A12R A14R T14 A0R R14 OPTR P14 I/O0L P15 I/O0R R15 NC T15 NC T16 NC R16 NC P16 I/O1L N16 I/O2R N15 I/O1R N14 I/O2L M16 I/O4L M15 I/O3L M14 I/O3R L16 I/O5R L15 I/O4R L14 I/O5L K16 I/O7L K15 I/O6L K14 I/O6R J16 I/O8L J15 I/O7R J14 I/O8R H16 I/O10R H15 IO9L H14 I/O9R G16 I/O11R G15 I/O11L G14 I/O10L F16 I/O12L F14 I/O12R F15 I/O13R CE0R R11 REPEATR A11R CE1R A11L B10 R/WL C13 A3L A10R R10 R/WR A9R T10 OER A8R VDD VDD INTL VSS VSS E10 VSS E11 VDD E12 VDD E13 VDDQR VDD NC VSS VSS F10 VSS F12 VDD F13 VDDQR VSS VSS VSS VSS VSS G10 VSS G11 VSS G12 VSS G13 VDDQL VSS VSS VSS VSS VSS H10 VSS H11 VSS H12 VSS H13 VDDQL ZZR VSS VSS VSS VSS J10 VSS J11 VSS J12 ZZL J13 VDDQR VSS VSS VSS VSS VDD NC NC VSS VDD VDD INTR VSS VDDQR VDDQR VDDQL VDDQL VSS K10 VSS K11 VSS K12 VSS VSS L10 VSS L11 VSS L12 VDD VSS M10 VSS M11 VDD M12 VDD VDDQR N10 VDDQR N11 VDDQL N12 VDDQL K13 VDDQR L13 VDDQL M13 VDDQL N13 VDD NC F11 VSS 5682 drw 02e A17R A17L A16L A16R PIPE/FTR Pin Configuration (1,2,3,4) 70T3509M BP256(5,7) BPG256(5,7) 256-Pin BGA Top View(6) NOTES: 1. All V DD pins must be connected to 2.5V power supply. 2. All V DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V DD (2.5V), and 2.5V if OPT pin for that port is set to V SS (0V). 3. All V SS pins must be connected to ground supply. 4. Package body is approximately 17mm x 17mm x 1.76mm, with 1.0mm ball-pitch. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking.
6.42 70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Rang es Feb.28.22 Pin Names Left Port Right Port Names CE0L, CE1L CE0R, CE1R Chip Enables (Input) (5) R/WL R/WR Read/Write Enable (Input) OEL OER Output Enable (Input) A0L - A 19L A0R - A 19R Address (Input) I/O0L - I/O35L I/O0R - I/O35R Data Input/Output CLKL CLKR Clock (Input) PL/FTL PL/FTR Pipeline/Flow-T hrough (Input) ADSL ADSR Address Strobe Enable (Input) CNTENL CNTENR Counter Enable (Input) REPEATL REPEATR Counter Repeat(3) (Input) BE0L - BE3L BE0R - BE3R Byte Enables (9-bit bytes) (Input) (5) VDDQL VDDQR Power (I/O Bus) (3.3V or 2.5V) (1) (Input) OPTL OPTR Option for selecting V DDQX(1,2) (Input) ZZL ZZR Sleep Mode pin (4) (Input) VDD Power (2.5V)(1) (Input) VSS Ground (0V) (Input) TDI Test Data Input TDO Test Data Output TCK T est Logic Clock (10MHz) (Input) TMS T est Mode Select (Input) TRST Reset (Initialize T AP Controller) (Input) INTL INTR Interrupt Flag (Output) 5682 tbl 01 NOTES: 1. V DD, OPT X, and V DDQX must be set to appropriate operating levels prior to applying inputs on the I/Os and controls for that port. 2. OPT X selects the operating voltage levels for the I/Os and controls on that port. If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V levels and VDDQX must be supplied at 3.3V. If OPT X is set to V SS (0V), then that port's I/Os and address controls will operate at 2.5V levels and V DDQX must be supplied at 2.5V. The OPT pins are independent of one another—both ports can operate at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V with the other at 2.5V. 3. When REPEAT X is asserted, the counter will reset to the last valid address loaded via ADSX. 4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/ FTx and OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode. It is recommended that boundary scan not be operated during sleep mode. 5. Chip Enables and Byte Enables are double buffered when PL/ FT = VIH, i.e., the signals take two cycles to deselect.
6.42 70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Range s Feb.28.22 NOTES: 1. "H" = V IH, "L" = V IL, "X" = Don't Care. 2. ADS, CNTEN, REPEAT = X. 3. OE and ZZ are asynchronous input signals. 4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illust rated here. Truth Table I—Read/Write and Enable Control (1,2,3,4) OE CLK CE0 CE1 BE3 BE2 BE1 BE0 R/W ZZ Byte 3 I/O27-35 Byte 2 I/O18-26 Byte 1 I/O9-17 Byte 0 I/O0-8 MODE X ↑ HLXXXXX LH i g h - ZH i g h - ZH i g h - ZH i g h - Z D e s e l e c t e d – P o w e r D o w n X ↑ LLXXXXXXA c t i v eA c t i v eA c t i v eA c t i v e N o t A l l o w e d X ↑ HHXXXXXXA c t i v eA c t i v eA c t i v eA c t i v e N o t A l l o w e d X ↑ LHHHHHX LH i g h - ZH i g h - ZH i g h - ZH i g h - Z A l l B y t e s D e s e l e c t e d X ↑ LHHHHL L LH i g h - ZH i g h - ZH i g h - Z D IN Write to Byte 0 Only X ↑ L H H H L H L L High-Z High-Z D IN High-Z Write to Byte 1 Only X ↑ LHHLHHL LH i g h - Z D IN High-Z High-Z Write to Byte 2 Only X ↑ LHLHHHL L D IN High-Z High-Z High-Z Write to Byte 3 Only X ↑ L H H H L L L L High-Z High-Z D IN DIN Write to Lower 2 Bytes Only X ↑ LHLLHHL L D IN DIN High-Z High-Z Write to Upper 2 bytes Only X ↑ LHLLLLLL D IN DIN DIN DIN Write to All Bytes L ↑ LHHHHL H LH i g h - ZH i g h - ZH i g h - Z D OUT Read Byte 0 Only L ↑ L H H H L H H L High-Z High-Z D OUT High-Z Read Byte 1 Only L ↑ LHHLHHHLH i g h - Z D OUT High-Z High-Z Read Byte 2 Only L ↑ LHLHHHHL D OUT High-Z High-Z High-Z Read Byte 3 Only L ↑ L H H H L L H L High-Z High-Z D OUT DOUT Read Lower 2 Bytes Only L ↑ LHLLHHHL D OUT DOUT High-Z High-Z Read Upper 2 Bytes Only L ↑ LHLLLLHL D OUT DOUT DOUT DOUT Read All Bytes H ↑ XXXXXXX LH i g h - ZH i g h - ZH i g h - ZH i g h - Z O u t p u t s D i s a b l e d XXXXXXXXX HH i g h - ZH i g h - ZH i g h - ZH i g h - Z S l eep Mode 5682 tbl 02 Truth Table II—Address Counter Control (1,2) NOTES: 1. "H" = V IH, "L" = V IL, "X" = Don't Care. 2. Read and write operations are controlled by the appropriate setting of R/ W, CE0, CE 1, BEn and OE. 3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle. 4. ADS and REPEAT are independent of all other memory control signals including CE0, CE 1 and BEn 5. The address counter advances if CNTEN = V IL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE 1, BEn. 6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location. 7. Address A 19 must be managed as part of a full depth counter implementation using the IDT70T3509M. For physical addresses 00000 H through 7FFFF H the value of a A 19 is 0, while for physical addresses 80000 H through FFFFF H the value of A 19 is 1. The user needs to keep track of the device counter and make sure that A19 is actively driven from 0-to-1 or 1-to-0 and held as needed at the appropriate address boundaries for full depth counter opera tion and that A 19 is in the appropriate state when using the REPEAT function. Address Previous Internal Address Internal Address Used CLK ADS CNTEN REPEAT (6) I/O(3) MODE An X An ↑ L (4) XH D I/O (n) External Address Used XA n A n + 1 ↑ H L (5) HD I/O(n+1) Counter Enabled—Internal Address generation (7) XA n + 1 A n + 1 ↑ HH H D I/O(n+1) External Address Blocked—Counter disabled (An + 1 reused) XX A n ↑ XX L (4) DI/O(n) Counter Set to last valid ADS load 5682 tbl 03
6.42 70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Rang es Feb.28.22 Recommended Operating Temperature and Supply Voltage (1) NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. Grade Ambient Temperature GND V DD Commercial 0 OC to +70OC0 V 2 . 5 V + 100mV Industrial -40 OC to +85OC0 V 2 . 5 V + 100mV 5682 tbl 04 Recommended DC Operating Conditions with VDDQ at 3.3V NOTES: 1. V IL (min.) = -1.0V for pulse width less than t CYC/2, or 5ns, whichever is less. 2. V IH (max.) = V DDQ + 1.0V for pulse width less than t CYC/2 or 5ns, whichever is less. 3. To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to V DD (2.5V), and V DDQX for that port must be supplied as indicated above. Symbol Parameter Min. Typ. Max. Unit VDD Core Supply Voltage 2.4 2.5 2.6 V VDDQ I/O Supply Voltage (3) 3.15 3.3 3.45 V VSS Ground 0 0 0 V VIH Input High Voltage (Address, Control &Data I/O Inputs)(3) 2.0 ____ VDDQ + 150mV(2) V VIH Input High Voltage _ JT AG 1.7 ____ VDD + 100mV(2) V VIH Input High Voltage - ZZ, OPT, PIPE/FT VDD - 0.2V ____ VDD + 100mV(2) V VIL Input Low Voltage -0.3 (1) ____ 0.8 V VIL Input Low Voltage - ZZ, OPT, PIPE/FT -0.3(1) ____ 0.2 V 5682 tbl 05b Recommended DC Operating Conditions with VDDQ at 2.5V NOTES: 1. V IL (min.) = -1.0V for pulse width less than t CYC/2 or 5ns, whichever is less. 2. V IH (max.) = V DDQ + 1.0V for pulse width less than t CYC/2 or 5ns, whichever is less. 3. To select operation at 2.5V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to V ss(0V), and V DDQX for that port must be supplied as indicated above. Symbol Parameter Min. Typ. Max. Unit VDD Core Supply Voltage 2.4 2.5 2.6 V VDDQ I/O Supply Voltage (3) 2.4 2.5 2.6 V VSS Ground 0 0 0 V VIH Input High Volltage (Address, Control & Data I/O Inputs)(3) 1.7 ____ VDDQ + 100mV(2) V VIH Input High Voltage _ JT AG 1.7 ____ VDD + 100mV(2) V VIH Input High Voltage - ZZ, OPT , PIPE/FT VDD - 0.2V ____ VDD + 100mV(2) V VIL Input Low Voltage -0.3 (1) ____ 0.7 V VIL Input Low Voltage - ZZ, OPT , PIPE/FT -0.3(1) ____ 0.2 V 5682 tbl 05a
6.42 70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Range s Feb.28.22 Absolute Maximum Ratings (1) Symbol Rating Com'l & Ind Unit VTERM (VDD) VDD T erminal Voltage with Respect to GND -0.5 to 3.6 V VTERM(2) (VDDQ) VDDQ T erminal Voltage with Respect to GND -0.3 t o VDDQ + 0.3 V VTERM(2) (INPUTS and I/O's) Input and I/O T erminal Voltage with Respect to GND -0.3 t o VDDQ + 0.3 V TBIAS(3) T emperature Under Bias -55 to +125 oC TSTG Storage T emperature -65 to +150 oC TJN Junction T emperature +150 oC IOUT(For VDDQ = 3.3V) DC Output Current 50 mA IOUT(For VDDQ = 2.5V) DC Output Current 40 mA 5682 tbl 06 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This is a steady-state DC parameter that applies after the power supply has reached its nominal operating value. Power sequencing is not necessary; however, the voltage on any Input or I/O pin cannot exceed V DDQ during power supply ramp up. 3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected. NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. C OUT also references C I/O. Capacitance(1) (TA = +25°C, F = 1.0MHZ) BGA ONLY Symbol Parameter Conditions Max. Unit CIN Input Capacitance V IN = 0V 35 pF COUT(2) Output Capacitance V OUT = 0V 35 pF 5682 tbl 07 Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV) Symbol Parameter Test Conditions 70T3509MS UnitMin. Max. |ILI| Input Leakage Current (1) VDDQ = Max., V IN = 0V t o VDDQ ___ 20 µA |ILI| JTAG & ZZ Input Leakage Current (1,2) VDD = Max., VIN = 0V to V DD ___ 60 µA |ILO| Output Leakage Current (1,3) CE0 = V IH and CE 1 = V IL, VOUT = 0V t o VDDQ ___ 20 µA VOL (3.3V) Output Low Voltage (1) IOL = +4mA, V DDQ = Min. ___ 0.4 V VOH (3.3V) Output High Voltage (1) IOH = -4mA, V DDQ = Min. 2.4 ___ V VOL (2.5V) Output Low Voltage (1) IOL = +2mA, V DDQ = Min. ___ 0.4 V VOH (2.5V) Output High Voltage (1) IOH = -2mA, V DDQ = Min. 2.0 ___ V 5682 tbl 08 NOTES: 2. Applicable only for TMS, TDI and TRST inputs. 3. Outputs tested in tri-state mode.
6.42 70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Rang es Feb.28.22 Temperature and Supply Voltage Range (3) (VDD = 2.5V ± 100mV) NOTES: 1. At f = f MAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/t CYC, using "AC TEST CONDITIONS". 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. V DD = 2.5V, T A = 25°C for Typ, and are not production tested. I DD DC (f=0) = 30mA (Typ). 5. CEX = V IL means CE0X = V IL and CE 1X = V IH (enabled) CEX = V IH means CE0X = V IH and CE 1X = V IL (disabled) CEX < 0.2V means CE0X < 0.2V and CE 1X > V DDQ - 0.2V (enabled - CMOS levels) CEX > VDDQ - 0.2V means CE0X > V DDQ - 0.2V and CE 1X < 0.2V (disabled - CMOS levels) "X" represents "L" for left port or "R" for right port. 6. I SB1, ISB2 and ISB4 will all reach full standby levels (ISB3) on the appropriate port(s) if ZZ L and/or ZZ R = V IH. 70T3509MS133 Com'l & Ind Symbol Parameter Test Condition Version Typ. (4) Max. Unit IDD Dynamic Operating Current (Both Ports Active) CE L and CER= VIL, Outputs Disabled, f = fMAX(1) COM'L S 800 1120 mA IND S 800 1370 ISB1(6) Standby Current (Both Ports - TTL Level Inputs) CE L = CER = V IH f = fMAX(1) COM'L S 560 760 mA IND S 560 940 ISB2(6) Standby Current (One Port - TTL Level Inputs) CE "A" = V IL and CE"B" = VIH(5) Active Port Outputs Disabled, f=fMAX(1) COM'L S 680 880 mA IND S 680 1090 ISB3 Full Standby Current (Both Ports - CMOS Level Inputs) Both Ports CE0L = CE0R > VDDQ - 0.2V and CE1L = CE1R < 0.2V, VIN > VDDQ - 0.2V or V IN < 0.2V, f = 0 (2) COM'L S 20 60 mA IND S 20 80 ISB4(6) Full Standby Current (One Port - CMOS Level Inputs) CE "A" < 0.2V and CE"B" > VDDQ - 0.2V (5) VIN > VDDQ - 0.2V or V IN < 0.2V Active Port, Outputs Disabled, f = f MAX(1) COM'L S 680 880 mA IND S 680 1090 Izz Sleep Mode Current (Both Ports - TTL Level Inputs) ZZ L = ZZR = VIH f=fMAX(1) COM'L S 20 60 mA IND S 20 80 5682 tbl 09
6.42 70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Rang es Feb.28.22 (Read and Write Cycle Timing) (2,3) (VDD = 2.5V ± 100mV, TA = 0°C to +70°C) NOTES: 1. The Pipelined output parameters (t CYC2, t CD2) apply to either or both left and right ports when FT/PIPEX = V DD (2.5V). Flow-through parameters (t CYC1, t CD1) apply when FT/PIPE = V ss (0V) for that port. 2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable ( OE), FT/PIPE and OPT. FT/PIPE and OPT should be treated as DC signals, i.e. steady state during operation. 4. Guaranteed by design (not production tested). 70T3509MS133 Com'l & Ind Symbol Parameter Min. Max. Unit tCYC1 Clock Cycle Time (Flow-Through) (1) 25 ____ ns tCYC2 Clock Cycle Time (Pipelined) (1) 7.5 ____ ns tCH1 Clock High Time (Flow-Through) (1) 10 ____ ns tCL1 Clock Low Time (Flow-Through) (1) 10 ____ ns tCH2 Clock High Time (Pipelined) (2) 3 ____ ns tCL2 Clock Low T ime (Pipelined) (1) 3 ____ ns tSA Address Setup Time 1.8 ____ ns tHA Address Hold T ime 0.5 ____ ns tSC Chip Enable Setup Time 1.8 ____ ns tHC Chip Enable Hold Time 0.5 ____ ns tSB Byte Enable Setup Time 1.8 ____ ns tHB Byte Enable Hold Time 0.5 ____ ns tSW R/W Setup Time 1.8 ____ ns tHW R/W Hold Time 0.5 ____ ns tSD Input Data Setup Time 1.8 ____ ns tHD Input Data Hold Time 0.5 ____ ns tSAD ADS Setup Time 1.8 ____ ns tHAD ADS Hold Time 0.5 ____ ns tSCN CNTEN Setup Time 1.8 ____ ns tHCN CNTEN Hold Time 0.5 ____ ns tSRPT REPEAT Setup Time 1.8 ____ ns tHRPT REPEAT Hold Time 0.5 ____ ns tOE Output Enable to Data Valid ____ 4.6 ns tOLZ(4) Output Enable to Output Low-Z 1 ____ ns tOHZ(4) Output Enable to Output High-Z 1 4.2 ns tCD1 Clock to Data Valid (Flow-Through) (1) ____ 15 ns tCD2 Clock to Data Valid (Pipelined) (1) ____ 4.2 ns tDC Data Output Hold After Clock High 1 ____ ns tCKHZ(4) Clock High to Output High-Z 1 4.2 ns tCKLZ(4) Clock High to Output Low-Z 1 ____ ns tINS Interrupt Flag Set Time ____ 7n s tINR Interrupt Flag Reset Time ____ 7n s tCOLS Collision Flag Set Time ____ 4.2 ns tCOLR Collision Flag Reset Time ____ 4.2 ns tZZSC Sleep Mode Set Cycles 2 ____ cycles tZZRC Sleep Mode Recovery Cycles 3 ____ cycles Port-to-Port Delay tCO Clock-to-Clock Offset 6 ____ ns 5682 tbl 11
6.42 70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Range s Feb.28.22 An An + 1 An + 2 An + 3 tCYC2 tCH2 tCL2 R/W ADDRESS CE0 CLK CE1 BEn (3) DATAOUT OE tCD2 tCKLZ Qn Qn + 1 Qn + 2 tOHZ tOLZ tOE 5682 drw 05 (1) (1) tSC tHC tSB tHB tSW tHW tSA tHA tDC tSC tHC tSB tHB (4) (1 Latency) (5) (5) Timing Waveform of Read Cycle for Pipelined Operation (FT/PIPE'X' = VIH)(1,2) NOTES: 1. OE is asynchronously controlled; all other inputs depicted in the above waveforms are synchronous to the rising clock edge. 2. ADS = V IL, CNTEN and REPEAT = V IH. 3. The output is disabled (High-Impedance state) by CE0 = V IH, CE 1 = V IL, BEn = V IH following the next rising edge of the clock. Refer to Truth Table 1. 4. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. If BEn was HIGH, then the appropriate Byte of DATA OUT for Qn + 2 would be disabled (High-Impedance state). 6. "x" denotes Left or Right port. The diagram is with respect to that port. Timing Waveform of Read Cycle for Flow-Through Output (FT/PIPE"X" = VIL)(1,2,6) An An + 1 An + 2 An + 3 tCYC1 tCH1 tCL1 R/W ADDRESS DATAOUT CE0 CLK OE tSC tHC tCD1 tCKLZ Qn Qn + 1 Qn + 2 tOHZ tOLZ tOE tCKHZ 5682 drw 06 (5) (1) CE1 BEn (3) tSB tHB tSW tHW tSA tHA tDC tDC (4) tSC tHC tSB tHB
6.42 70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Rang es Feb.28.22 CLK"A" R/W"A ADDRESS"A" DATAIN"A" CLK"B" R/W"B" ADDRESS"B" DATAOUT"B" tSW tHW tSA tHA tSD tHD tSW tHW tSA tHA tCO(3) tCD2 NO MATCH VALID NO MATCHMATCH MATCH VALID 5682 drw 09tDC Timing Waveform of Left Port Write to Pipelined Right Port Read(1,2,4) NOTES: 1. CE0, BEn, and ADS = V IL; CE 1, CNTEN, and REPEAT = V IH. 2. OE = V IL for Port "B", which is being read from. OE = V IH for Port "A", which is being written to. 3. If t CO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to val id read on opposite port will be tCO + 2 t CYC2 + t CD2). If t CO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on oppos ite port will be t CO + t CYC2 + t CD2). 4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A" Timing Waveform with Port-to-Port Flow-Through Read(1,2,4) DATAIN "A" CLK "B" R/W "B" ADDRESS "A" R/W "A" CLK "A" ADDRESS "B" NO MATCHMATCH NO MATCHMATCH VALID tCD1 tDC DATAOUT "B" 5682 drw 10 VALID VALID tSW tHW tSA tHA tSD tHD tHW tCD1 tCO tDC tSA tSW tHA (3) NOTES: 1. CE0, BEn, and ADS = V IL; CE 1, CNTEN, and REPEAT = V IH. 2. OE = V IL for the Right Port, which is being read from. OE = V IH for the Left Port, which is being written to. 3. If t CO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to v alid read on opposite port will be tCO + t CYC + t CD1). If t CO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on oppo site port will be tCO + t CD1). 4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
6.42 70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Range s Feb.28.22 R/W ADDRESS An An +1 An + 2 An + 2 An + 3 An + 4 DATAIN Dn + 2 CE0 CLK 5682 drw 11 Qn Qn + 3DATAOUT CE1 BEn tCD2 tCKHZ tCKLZ tCD2 tSC tHC tSB tHB tSW tHW tSA tHA tCH2 tCL2 tCYC2 READ NOP READ tSD tHD (3) (1) tSW tHW WRITE (4) Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(2) NOTES: 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 2. CE0, BEn, and ADS = V IL; CE 1, CNTEN, and REPEAT = V IH. "NOP" is "No Operation". 3. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be rewritten to guarantee data integrity. R/W ADDRESS An An +1 An + 2 An + 3 An + 4 An + 5 DATAIN Dn + 3Dn + 2 CE0 CLK 5682 drw 12 DATAOUT Qn Qn + 4 CE1 BEn OE tCH2 tCL2 tCYC2 tCKLZ tCD2 tOHZ tCD2 tSD tHD READ WRITE READ tSC tHC tSB tHB tSW tHW tSA tHA (3) (1) tSW tHW (4) Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled)(2) NOTES: 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 2. CE 0, BEn, and ADS = V IL; CE 1, CNTEN, and REPEAT = V IH. 3. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if tim ing so allows.
6.42 70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Rang es Feb.28.22 Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(2) Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(2) NOTES: 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 2. CE0, BEn, and ADS = V IL; CE 1, CNTEN, and REPEAT = V IH. 3. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be rewritten to guarantee data in tegrity. R/W ADDRESS An An +1 An + 2 An + 2 An + 3 An + 4 DATAIN Dn + 2 CE0 CLK 5682 drw 13 QnDATAOUT CE1 BEn tCD1 Qn + 1 tCH1 tCL1 tCYC1 tSD tHD tCD1 tCD1 tDC tCKHZ Qn + 3 tCD1 tDC tSC tHC tSB tHB tSW tHW tSA tHA READ NOP READ tCKLZ (3) (1) tSW tHW WRITE(5) , R/W ADDRESS An An +1 An + 2 An + 3 An + 4 An + 5(3) DATAIN Dn + 2 CE0 CLK 5682 drw 14 QnDATAOUT CE1 BEn tCD1 tCH1 tCL1 tCYC1 tSD tHD tCD1 tDC Qn + 4 tCD1 tDC tSC tHC tSB tHB tSW tHW tSA tHA READ WRITE READ tCKLZ (1) Dn + 3 tOHZ tSW tHW OE tOE
6.42 70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Range s Feb.28.22 A0- A18 An CLK DATAOUT Qx - 1(2) Qx Qn Qn + 2(2) Qn + 3 ADS CNTEN tCYC2 tCH2 tCL2 5682 drw 15a tSA tHA tSAD tHAD tCD2 tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD tSAD tHAD tSCN tHCN READ WITH COUNTER Qn + 1 (3) A19(3) tSA Timing Waveform of Pipelined Read with Address Counter Advance(1) NOTES: 1. CE0, OE, BEn = V IL; CE 1, R/ W, and REPEAT = V IH. 2. If there is no address change via ADS = V IL (loading a new address) or CNTEN = V IL (advancing the address), i.e. ADS = V IH and CNTEN = V IH, then the data remains constant for subsequent clocks. 3. Address A 19 must be managed as part of a full depth counter implementation using the IDT70T3509M. For physical addresses 00000 H through 7FFFF H the value of a A 19 is 0, while for physical addresses 80000 H through FFFFF H the value of A 19 is 1. The user needs to keep track of the device counter and make sure that A 19 is actively driven from 0-to-1 or 1-to-0 and held as needed at the appropriate address boundaries for full depth counter opera tion. As shown this transition reflects An = 7FFFF H or FFFFF H. Timing Waveform of Flow-Through Read with Address Counter Advance(1) An CLK DATAOUT Qx(2) Qn Qn + 1 Qn + 2 Qn + 3(2) Qn + 4 ADS CNTEN tCYC1 tCH1 tCL1 5682 drw 16a tSA tHA tSAD tHAD READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD tCD1 tDC tSAD tHAD tSCN tHCN READ WITH COUNTER (3) A19(3) tSA A0- A18
6.42 70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Rang es Feb.28.22 An tCYC2 CLK DATAIN R/W REPEAT 5682 drw 18a INTERNAL(3) ADDRESS ADS CNTEN WRITE TO ADS ADDRESS An ADVANCE COUNTER WRITE TO An+1 ADVANCE COUNTER WRITE TO An+2 HOLD COUNTER WRITE TO An+2 REPEAT READ LAST ADS ADDRESS An DATAOUT tSA tHA An tSAD tHAD tSW tHW tSCN tHCN tSRPT tHRPT tSD tHD tCD1 An+1 An+2 An+2 An An+1 An+2 An+2 D0 D1 D2 D3 An An+1 An+2 An+2 ADVANCE COUNTER READ An+1 ADVANCE COUNTER READ An+2 HOLD COUNTER READ An+2 (4) (7) A19(7) tSA A0- A18 Timing Waveform of Write with Address Counter Advance (Flow-through or Pipelined Inputs)(1) Timing Waveform of Counter Repeat(2,6) An CLK DATAIN Dn Dn + 1 Dn + 1 Dn + 2 ADS CNTEN tCH2 tCL2 tCYC2 5682 drw 17a INTERNAL(3) ADDRESS An An + 1 An + 2 An + 3 An + 4 Dn + 3 Dn + 4 tSA tHA tSAD tHAD WRITE COUNTER HOLD WRITE WITH COUNTERWRITE EXTERNAL ADDRESS WRITE WITH COUNTER tSD tHD tSCN tHCN (7) (5) (5) A19(7) tSA A0- A18 NOTES: 1. CE0, BEn, and R/ W = V IL; CE 1 and REPEAT = V IH. 2. CE0, BEn = V IL; CE 1 = V IH. 3. The "Internal Address" is equal to the "External Address" when ADS = V IL and equals the counter output when ADS = V IH. 4. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid ADS load will be accessed. For more information on REPEAT function refer to Truth Table II. A 19 must be in the appropriate state when using the REPEAT function to guarantee the correct address location is loaded. 5. CNTEN = V IL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. T he ‘An +1’Address is written to during this cycle. 6. For Pipelined Mode user should add 1 cycle latency for outputs as per timing waveform of read cycle for pipelined operations. 7. Address A 19 must be managed as part of a full depth counter implementation using the IDT70T3509M. For physical addresses 00000 H through 7FFFF H the value of a A 19 is 0, while for physical addresses 80000 H through FFFFF H the value of A 19 is 1. The user needs to keep track of the device counter and make sure that A 19 is actively driven from 0-to-1 or 1-to-0 and held as needed at the appropriate address boundaries for full depth counter opera tion. As shown this transition reflects An = 7FFFF H or FFFFF H.
6.42 70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Range s Feb.28.22 tSW tHW FFFFF CLKR CER(1) ADDRESSR(3) tSA tHA FFFFF tSC tHC tINR CLKL R/WL ADDRESSL(3) CEL(1) tSA tHA tSC tHC 5682 drw 19 INTR tINS R/WR tSW tHW Waveform of Interrupt Timing(2) Truth Table III - Interrupt Flag(1) Left Port Right Port FunctionCLKL R/WL(2) CEL(2) A19L-A0L INTL CLKR R/WR(2) CER(2) A19R-A0R INTR ↑ L L FFFFF X ↑ X X X L Set Right INTR Flag ↑ X XXX ↑ H L FFFFF H Reset Right INTR Flag ↑ XX X L ↑ L L FFFFE X Set Left INTL Flag ↑ H L FFFFE H ↑ X X X X Reset Left INTL Flag 5682 tbl 12 NOTES: 1. CE0 = V IL and CE 1 = V IH. 2. All timing is the same for Left and Right ports. 3. Address is for internal register, not the external bus, i.e. address needs to be qualified by one of the Address counter cont rol signals. NOTES: 1. INTL and INTR must be initialized at power-up by Resetting the flags. 2. CE0 = V IL and CE 1 = V IH, R/ W and CE are synchronous with respect to the clock and need valid set-up and hold times. 3. Address is for internal register, not the external bus, i.e. address needs to be qualified by one of the Address counter cont rol signals.
6.42 70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Rang es Feb.28.22 Timing Waveform - Entering Sleep Mode (1,2) Timing Waveform - Exiting Sleep Mode (1,2) (3) R/W DATAOUT R/W OE (4) Dn Dn+1 An+1An (5) (5) NOTES: 1. CE 1 = VIH. 2. All timing is same for Left and Right ports. 3. CE0 has to be deactivated ( CE0 = V IH) three cycles prior to asserting ZZ (ZZx = V IH) and held for two cycles after asserting ZZ (ZZx = V IH). 4. CE0 has to be deactivated ( CE0 = V IH) one cycle prior to de-asserting ZZ (ZZx = V IL) and held for three cycles after de-asserting ZZ (ZZx = V IL). 5. The device must be in Read Mode (R/ W High) when exiting sleep mode. Outputs are active but data is not valid until the following cycle.
6.42 70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Range s Feb.28.22 Width Expansion The IDT70T3509M can be used in applications requiring expanded width. Through combining the control signals, the devices can be grouped as necessary to accommodate applications needing 72-bits or wider. Functional Description The IDT70T3509M provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse width is independent of the cycle time. An asynchronous output enable is provided to ease asyn- chronous bus interfacing. Counter enable inputs are also provided to stall the operation of the address counters for fast interleaved memory applications. The combination of a HIGH on CE 0 and a LOW on CE1 for one clock cycle will power down the internal circuitry to reduce static power consumption. Multiple chip enables allow easier banking of multiple IDT70T3509Ms for depth expansion configurations. Two cycles are required with CE 0 LOW and CE1 HIGH to reactivate the outputs. Sleep Mode The IDT70T3509M is equipped with an optional sleep or low power mode on both ports. The sleep mode pin on both ports is asynchronous and active high. During normal operation, the ZZ pin is pulled low. When ZZ is pulled high, the port will enter sleep mode where it will meet lowest possible power conditions. The sleep mode timing diagram shows the modes of operation: Normal Operation, No Read/Write Allowed and Sleep Mode. For normal operation all inputs must meet setup and hold times prior to sleep and after recovering from sleep. Clocks must also meet cycle high and low times during these periods. Three cycles prior to asserting ZZ (ZZx = V IH) and three cycles after de-asserting ZZ (ZZx = VIL), the device must be disabled via the chip enable pins. If a write or read operation occurs during these periods, the memory array may be corrupted. Validity of data out from the RAM cannot be guaranteed immediately after ZZ is asserted (prior to being in sleep). When exiting sleep mode, the device must be in Read mode (R/Wx = V IH)when chip enable is asserted, and the chip enable must be valid for one full cycle before a read will result in the output of valid data. During sleep mode the RAM automatically deselects itself. The RAM disconnects its internal clock buffer. The external clock may continue to run without impacting the RAMs sleep current (I ZZ). All outputs will remain in high-Z state while in sleep mode. All inputs are allowed to toggle. The RAM will not be selected and will not perform any reads or writes.
Figure 2. JTAG Configuration for IDT70T3509M is available at www.idt.com. and thus cannot be treated as a single JTAG device in the scan chain. commands but must be treated as separate entities in JTAG operations.
- 30pF loading on external output signals.
- Refer to AC Electrical Test Conditions stated earlier in this document.
- JTAG operations occur at one speed (10MHz). The base device may run at
any speed specified in this datasheet. Figure 5. Standard JTAG Timing
- Device inputs = All device inputs except TDI, TMS, and TRST.
- Device outputs = All device outputs except TDO.
6.42 70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Rang es Feb.28.22 Identification Register Definitions Instruction Field Array D Value Array D Instruction Field Array C Value Array C Instruction Field Array B Value Array B Instruction Field Array A Value Array A Description Revision Number (31:28) 0x0 Revision Number (63:60) 0x0 Revision Number (95:92) 0x0 Revision Number (127:124) 0x0 Reserved for Version number IDT Device ID (27:12) 0x333 IDT Device ID (59:44) 0x333 IDT Device ID (91:76) 0x333 IDT Device ID (123:108) 0x333 Defines IDT Part numb er IDT JEDEC ID (11:1) 0x33 IDT JEDEC ID (43:33) 0x33 IDT JEDEC ID (75:65) 0x33 IDT JEDEC ID (107:97) 0x33 Allows unique identification of device vendor as IDT ID Register Indicator Bit (Bit 0) 1 ID Register Indicator Bit (Bit 32) 1 ID Register Indicator Bit (Bit 64) 1 ID Register Indicator B it (Bit 96) 1 Indicates the presence of an ID Register 5682 tbl 16 Scan Register Sizes System Interface Parameters NOTES: 1. Device outputs = All device outputs except TDO. 2. Device inputs = All device inputs except TDI, TMS, and TRST. 3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by conta cting your local IDT sales representative. Register Name Bit Size Array A Bit Size Array B Bit Size Array C Bit Size Array D Bit Size 70T3509M Instruction (IR) 4 4 4 4 16 Bypass (BYR) 1 1 1 1 4 Identification (IDR) 32 32 32 32 128 Boundary Scan (BSR) Note (3) Note (3) Note (3) Note (3) Note (3) 5682 tbl 17 Instruction Code Description EXTEST 0000000000000000 Forces contents of the boundary scan cells onto the device outputs (1). Places the boundary scan register (BSR) between T DI and T DO. BYPASS 1111111111111111 Place s the b y p ass re g is te r (BYR) b e twe e n TDI and TDO. IDCODE 0010001000100010 Loads the ID register (IDR) with the vendor ID code and places the register between TDI and TDO. HIGHZ 0100010001000100 Places the bypass register (BYR) between T DI and T DO. Forces all device output drivers except INTx to a High-Z state. CLAMP 0011001100110011 Uses BYR. Forces contents of the boundary scan cells onto the device outputs. Places the bypass register (BYR) between TDI and TDO. SAMPLE/PRELOAD 0001000100010001 Places the boundary scan register (BSR) between TDI and TDO. SAMPLE allows data from device inputs (2) to be captured in the boundary scan cells and shifted serially through TDO. PRELOAD allows data to be input serially into the boundary scan cells via the TDI. RESERVED 0101010101010101, 0111011101110111, 1000100010001000, 1001100110011001, 1010101010101010, 1011101110111011, 1100110011001100 Several combinations are reserved. Do not use codes other than those identified above. PRIVATE 0110011001100110,1110111011101110, 1101110111011101 For internal use only. 5682 tbl 18
6.42 70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Range s Feb.28.22
Ordering Information
NOTES: 1. Contact your local sales office for Industrial temp range in other speeds, packages and powers. 2. Green parts available. For specific speeds, packages and powers contact your local sales office . A Power 999 Speed A Package A Process/ Temperature Range XXXXX Device Type Blank I(1) BP(3) 133 70T3509M S Commercial (0°C to +70°C) Industrial (-40°C to +85°C) 256-pin BGA (BP256, BPG256) 36Mbit (1024K x 36) 2.5V Synchronous Dual-Port RAM Standard Power Speed in MegahertzCommercial and Industrial 5682 drw 26 A G(2) Green Blank Tray Tape and Reel A Orderable Part Information Speed (MHz) Orderable Part ID Pkg. Code Pkg. Type Temp. Grade 133 70T3509MS133BP BP256 CABGA C 70T3509MS133BPI BP256 CABGA I 70T3509MS133BPG BPG256 CABGA C 70T3509MS133BPGI BPG256 CABGA I
6.42 70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Rang es Feb.28.22 Datasheet Document History 11/09/04: Initial Public Release of Preliminary Datasheet 03/24/05: Page 1 Added I-temp offering to features Page 6 Added I-temp information to the Recommended Operating Temperature and Supply Voltage table Page 8 Added I-temp values to the DC Electrical Characteristics table Page 10 Added I-temp to the heading of the AC Electrical Characteristics table Page 23 Added I-temp to ordering information Page 1 Added green availability to features Page 1 - 23 Removed Preliminary status 06/14/05: Page 1 Added feature to highlight footprint compatibility Page 3 & 23 Added a footnote to highlight package thickness of BP-256 vs. BC-256 08/27/07: Page 1 Functional Block Diagram changed to correct chip enable logic and added footnote 2 referencing Truth Table I 07/28/08: Page 8 Corrected a typo in the DC Chars table 01/19/09: Page 23 Removed "IDT" from orderable part number 07/15/14: Page 23 Added Tape & Reel to Ordering Information Page 23 Ordering Information restored from 70T3719_99 to 70T3509M Product Discontinuation Notice - PDN# SP-17-02 Last time buy expires June 15, 2018 Page 3 & 23 Updated package code BP-256 to BP256 and BPG256 Page 23 Added Orderable Part Information table Page 23 Corrected "ns" to "MHz" in the header of the Orderable Part Information table 02/28/22: Page 1 - 24 Source file updated to reflect previous Corporate Marketing rebranding Page 2 Updated the package code Page 22 Corrected the Orderable Part Information table 02/14/18: 07/09/19: 10/29/19:
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