MB39A104 FUJITSU

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  • Manufacturer or author: Provided By digicamel.com
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DS04-27231-3EFUJITSU SEMICONDUCTOR DATA SHEET ASSP For Power Management Applications (General Purpose DC/DC Converter) 2-ch DC/DC Converter IC with Overcurrent Protection MB39A104 n DESCRIPTION The MB39A104 is a 2-channel DC/DC converter IC using pulse width modulation (PWM), incorporating an overcurrent protection circuit (requiring no current sense resistor). This IC is ideal for down conversion. Operating at high frequency reduces the value of coil. This is ideal for built-in power supply such as LCD monitors and ADSL. This product is covered by US Patent Number 6,147,477. n FEATURES

  • Built-in timer-latch overcurrent protection circuit (requiring no current sense resistor)
  • Power supply voltage range : 7 V to 19 V
  • Reference voltage : 5.0 V – 1 %
  • Error amplifier threshold voltage : 1.24 V – 1 %
  • High-frequency operation capability : 1.5 MHz (Max)
  • Built-in standby function: 0 mA (T yp)
  • Built-in soft-start circuit independent of loads
  • Built-in totem-pole type output for Pch MOS FET n PACKAGE 24-pin plastic SSOP (FPT-24P-M03)

(TOP VIEW) (FPT-24P-M03) VCCO : VH : OUT1 : VS1 : ILIM1 : DTC1 : VCC : CSCP : FB1 : -INE1 : CS1 : RT : : CTL : GNDO : OUT2 : VS2 : ILIM2 : DTC2 : GND : VREF : FB2 : -INE2 : CS2 : CT

Pin No. Symbol I/O Descriptions 1V C C O ¾ Output circuit power supply terminal (Connect to same potential as VCC pin.)

2 VH O Power supply terminal for FET drive circuit (VH = VCC - 5 V)

3 OUT1 O External Pch MOS FET gate drive terminal

4 VS1 I Overcurrent protection circuit input terminal

Overcurrent protection circuit detection resistor connection terminal. Set overcurrent detection reference voltage depending on external resistor and internal current resource (110 mA at RT = 24 kW ) 6D T C 1 I PWM comparator block (PWM) input terminal. Compares the lowest voltage among FB1 and DTC terminals with triangular wave and controls output. 7V C C ¾ Power supply terminal for reference power supply and control circuit (Connect to same potential as the VCCO terminal) 8C S C P ¾ Timer-latch short-circuit protection capacitor connection terminal

9 FB1 O Error amplifier (Error Amp 1) output terminal

10 -INE1 I Error amplifier (Error Amp 1) inverted input terminal

11 CS1 ¾ Soft-start capacitor connection terminal

12 RT ¾ Triangular wave oscillation frequency setting resistor connection terminal

13 CT ¾ Triangular wave oscillation frequency setting capacitor connection terminal

14 CS2 ¾ Soft-start capacitor connection terminal

15 -INE2 I Error amplifier (Error Amp 2) inverted input terminal

16 FB2 O Error amplifier (Error Amp 2) output terminal

17 VREF O Reference voltage output terminal

18 GND ¾ Output circuit ground terminal (Connect to same potential as GNDO

terminal.) 19 DTC2 I PWM comparator block (PWM) input terminal. Compares the lowest voltage among FB2 and DTC terminals with triangular wave and controls output.

20 ILIM2 I

Overcurrent protection circit detection resistor connection terminal. Set overcurrent detection reference voltage depending on external resistor and internal current resource (110 mA at RT = 24 kW )

21 VS2 I Overcurrent protection circuit input terminal

22 OUT2 O External Pch MOS FET gate drive terminal

23 GNDO ¾ Output circuit ground terminal (Connect to same potential as GND terminal.) 24 CTL I Power supply control terminal. Setting the CTL terminal at “L” level places IC in the standby mode.

10 VREF

-INE1 CS1 FB1 DTC1 -INE2 CS2 FB2 DTC2 CSCP 12 13 1817 RT CT GND VREF CTL VCC GNDO VH ILIM2 VS2 OUT2 ILIM1 VS1 OUT1 VCCO 10 mA 1.24 V 1.24 V (3.1 V) SCP Comp. SCP Logic UVLO OSC VREF Bias Voltage Current Protection Logic Current Protection Logic IO = 200 mA at VCCO = 12 V IO = 200 mA at VCCO = 12 V VR1 VH VCC - 5 V 1.24 V 2.5 V 1.5 V 5.0 V bias Power ON/OFF CTL 10 mA Pch Drive2 Pch Drive1 PWM Comp.1 PWM Comp.2 Error Amp2 Error Amp1 CH1 CH2 L priority L priority L priority L priority Accuracy –1% H:UVLO release H: at OCP H priorityH: at SCP Error Amp Reference Error Amp Power Supply

n ABSOLUTE MAXIMUM RATINGS * : The packages are mounted on the epoxy board (10 cm · 10 cm). WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. n RECOMMENDED OPERATING CONDITIONS * : See“ n SETTING THE TRIANGULAR OSCILLA TION FREQUENCY”. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Parameter Symbol Condition Rating Unit Min Max Power supply voltage V CC VCC, VCCO terminal ¾ 20 V Output current I O OUT1, OUT2 terminal ¾ 60 mA Output peak current I OP Duty £ 5% (t = 1/fOSC ·Duty) ¾ 700 mA Power dissipation P D Ta £ +25 °C ¾ 740* mW Storage temperature T STG ¾- 55 +125 °C Parameter Symbol Condition Value UnitMin Typ Max Power supply voltage V CC VCC, VCCO terminal 7 12 19 V Reference voltage output current IREF VREF terminal -1 ¾ 0m A VH output current I VH VH terminal 0¾ 30 mA Input voltage VINE -INE1, -INE2 terminal 0 ¾ VCC - 0.9 V VDTC DTC1, DTC2 terminal 0 ¾ VCC - 0.9 V Control input voltage V CTL CTL terminal 0 ¾ 19 V Output current I O OUT1, OUT2 terminal -45 ¾+ 45 mA Output Peak current I OP Duty £ 5% (t = 1/fOSC ·Duty) -450 ¾+ 450 mA Oscillation frequency f OSC Overcurrent detection by ON resistance of FET100 500 1000 kHz * 100 500 1500 kHz Timing capacitor C T ¾ 39 100 560 pF Timing resistor R T ¾ 11 24 130 k W VH terminal capacitor C VH VH terminal ¾ 0.1 1.0 mF Soft-start capacitor C S CS1, CS2 terminal ¾ 0.1 1.0 mF Short-circuit detection capacitor CSCP CSCP terminal ¾ 0.1 1.0 mF Reference voltage output capacitor C REF VREF terminal ¾ 0.1 1.0 mF Operating ambient temperature Ta ¾- 30 +25 +85 °C

n ELECTRICAL CHARACTERISTICS (VCC = VCCO = 12 V, VREF = 0 mA, T a = +25 °C) (Continued) Parameter Symbol Pin No Conditions Value Unit Min Typ Max 1.Reference voltage block [REF] Output voltage VREF 17 Ta = +25 °C 4.95 5.00 5.05 V Output voltage temperature variation DV REF / VREF 17 Ta = 0 °C to +85 °C ¾ 0.5* ¾% Input stability Line 17 VCC = 7 V to 19 V ¾ 31 0 m V Load stability Load 17 VREF = 0 mA to -1 mA ¾ 11 0 m V Short-cuircuit output current IOS 17 VREF = 1 V -50 -25 -12 mA 2.Under voltage lockout protection circuit block [UVLO] Threshold voltage VTLH 17 VREF = 2.6 2.8 3.0 V VTHL 17 VREF = 2.4 2.6 2.8 V Hysteresis width VH 17 ¾¾ 0.2 * ¾ V 3.Short-circuit detection block [SCP Logic] Threshold voltage VTH 8 ¾ 0.68 0.73 0.78 V Input source current ICSCP 8 ¾- 1.4 -1.0 -0.6 mA Reset voltage V RST 17 VREF = 2.4 2.6 2.8 V 4.Short-circuit detection block [SCP Comp] Threshold voltage V TH 8 ¾ 2.8 3.1 3.4 V 5.Triangular wave oscillator block [OSC] Oscillation frequency f OSC 13 CT = 100 pF, RT = 24 kW 450 500 550 kHz Frequency temperature variation DfOSC / fOSC

13 T a = 0 °C to +85 °C ¾ 1* ¾%

6.Soft- start block [CS1, CS2] Charge current ICS 11, 14 CS1 = CS2 = 0 V -14 -10 -6 mA 7.Error amplifier bolck [Error Amp1, Error Amp2] Threshold voltage V TH 9, 16 FB1 = FB2 = 2 V 1.227 1.240 1.253 V Input bias current IB 10, 15 -INE1 = -INE2 = 0 V -120 -30 ¾ nA Voltage gain A V 9, 16 DC ¾ 100* ¾ dB

(Continued) (VCC = VCCO = 12 V, VREF = 0 mA, T a = +25 °C) *: Standard design value. Parameter Symbol Pin No. Conditions Value Unit Min Typ Max 8.Error amplifier bolck [Error Amp1, Error Amp2] Frequency bandwidth BW 9, 16 A V = 0 dB ¾ 1.6* ¾ MHz Output voltage VOH 9, 16 ¾ 4.7 4.9 ¾ V VOL 9, 16 ¾¾ 40 200 mV Output source current ISOURCE 9, 16 FB1 = FB2 = 2 V ¾- 2 -1m A Output sink current ISINK 9, 16 FB1 = FB2 = 2 V 150 200 ¾m A 9.PWM comparator block [PWM Comp.1, PWM Comp.2] Threshold voltage VT0 6, 19 Duty cycle = 0 % 1.4 1.5 ¾ V VT100 6, 19 Duty cycle = Dtr ¾ 2.5 2.6 V Input current I DTC 6, 19 DTC1 = DTC2 = 0.4 V -2.0 -0.6 ¾m A 10.Overcurrent protection circuit block [OCP1, OCP2] ILIM terminal input current ILIM 5, 20 RT = 24 kW , CT = 100 pF 99 110 121 mA Offset voltage V IO 5, 20 ¾¾ 1 * ¾ mV 11.Bias voltage block [VH]Output voltage V H 2 VCC = VCCO = 7 V to 19 V VH = 0 mA to 30 mA VCC - 5.5 VCC - 5.0 VCC - 4.5 V 12.Output block [Drive1, Drive2] Output source current ISOURCE 3, 22 OUT1 to OUT4 = 7 V , Duty £ 5 % (t = 1/fOSC ·Duty) ¾- 300 ¾ mA Output sink current ISINK 3, 22 OUT1 to OUT4 = 12 V , Duty £ 5 % (t = 1/fOSC ·Duty) ¾ 350 ¾ mA Output ON resistor R OH 3, 22 OUT1 = OUT2 = -45 mA ¾ 8.0 12.0 W R OL 3, 22 OUT1 = OUT2 = 45 mA ¾ 6.5 9.7 W 13.Control block [CTL] CTL input voltage VIH 24 IC Active mode 2 ¾ 19 V VIL 24 IC Standby mode 0 ¾ 0.8 V Input current ICTLH 24 CTL = 5 V ¾ 50 100 mA ICTLL 24 CTL = 0 V ¾¾ 1 mA 14.General Standby current I CCS 1, 17 CTL = 0 V ¾ 01 0 mA Power supply current ICC 1, 17 CTL = 5 V ¾ 4.0 6.0 mA

(Continued) Ta = +25 °C CTL = 5 V 0 5 10 15 20 Ta = +25 °C CTL = 5 V VREF = 0 mA 0 5 10 15 20 Ta = +25 °C VCC = 12 V CTL = 5 V 0 5 10 15 20 25 30 35 VCC = 12 V CTL = 5 V VREF = 0 mA 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -40 -20 0 20 40 60 80 100 Ta = +25 °C VCC = 12 V VREF = 0 mA 500 400 300 200 100 0 5 10 15 20 ICTL VREF Power supply current ICC (mA) Reference voltage VREF (V) Power Supply Current vs. Power Supply VoltageReference Voltage vs. Power Supply Voltage Power supply voltage VCC (V) Power supply voltage VCC (V) Reference Voltage vs. Ambient Temperature Reference voltage VREF (V) Ambient temperature Ta (°C) Reference voltage DVREF (%) Reference Voltage vs. Ambient Temperature Ambient temperature Ta (°C) CTL terminal current ICTL (mA) CTL terminal Current vs. CTL terminal Voltage CTL terminal voltage VCTL (V) Reference voltage VREF (V)

(Continued) Ta = +25 °C VCC = 12 V CTL = 5 V CT = 39 pF 10000 1000 100 CT = 100 pFCT = 220 pF CT = 560 pF 1 10 100 1000 Ta = +25 °C VCC = 12 V CTL = 5 V RT = 11 kW 10000 1000 100 RT = 24 kW RT = 68 kWRT = 130 kW 10 100 1000 1000 0 Ta = +25 °C VCC = 12 V CTL = 5 V RT = 47 kW 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 0 200 400 600 800 1000 1200 16001400 VCC = 12 V CTL = 5 V RT = 24 kW CT = 100 pF 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 -40 -20 0 20 40 60 80 100 VCC = 12 V CTL = 5 V RT = 24 kW CT = 100 pF 560 540 520 500 480 460 440 -40 -20 0 20 40 60 80 100 Triangular Wave Upper and Lower Limit Voltage vs. Ambient Temperature Triangular wave upper and lower limit voltage VCT (V) Ambient temperature Ta ( °C) Triangular Wave Oscillation Frequency vs. Timing Resistor Triangular wave oscillation frequency fOSC (kHz) Timing resistor RT (kW ) Triangular Wave Oscillation Frequency vs. Timing Capacitor Triangular wave oscillattion frequency fOSC (kHz) Timing capacitor CT (pF) Triangular Wave Oscillation Frequency vs. Ambient Temperature Triangular wave oscillation frequency fOSC (kHz) Ambient temperature Ta ( °C) Triangular wave upper and lower limit voltage VCT (V) Triangular Wave Upper and Lower Limit Voltage vs. Triangular Wave Oscillation Frequency Triangular wave oscillation frequency fOSC (kHz) Ta = +25 °C CTL = 5 V RT = 24 kW CT = 100 pF 560 540 520 500 480 460 440 0 5 10 15 20 Triangular Wave Oscillation Frequency vs. Power supply voltage Triangular wave oscillation frequency fOSC (kHz) Power supply voltage VCC (V) Upper Lower Upper Lower

(Continued) (15) (14) (16) IN OUT Error Amp1 (Error Amp2) 1 mF 1.24 V 10 kW 2.4 kW 240 kW 10 kW -10 -20 -30 -40 180 -90 -180 100 1 k 10 k 100 k 1 M 10 M Ta = +25 °C VCC = 12 V AV j 1000 800 600 400 200 740 -40 -20 0 20 40 60 80 100 Error Amplifier, Gain, Phase vs. Frequency Gain AV (dB) Phase f (deg) Frequency f (Hz) Power Dissipation vs. Ambient Temperature Power dissipation PD (mW) Ambient temperature Ta ( °C)

  1. DC/DC Converter Functions (1) Reference voltage block (REF) The reference voltage circuit generates a temperature-compensated reference voltage (5.0 V T yp) from the voltage supplied from the power supply terminal (pin 7). The voltage is used as the reference voltage for the IC’s internal circuitry. The reference voltage can supply a load current of up to 1 mA to an external device through the VREF terminal (pin 17). (2) Triangular-wave oscillator block (OSC) The triangular wave oscillator incorporates a timing capacitor and a timing resistor connected respectively to the CT terminal (pin 13) and RT terminal (pin 12) to generate triangular oscillation waveform amplitude of 1.5 V to 2.5 V . The triangular waveforms are input to the PWM comparator in the IC. (3) Error amplifier block (Error Amp1, Error Amp2) The error amplifier detects the DC/DC converter output voltage and outputs PWM control signals. In addition, an arbitrary loop gain can be set by connecting a feedback resistor and capacitor from the output terminal to inverted input terminal of the error amplifier, enabling stable phase compensation to the system. Also, it is possible to prevent rush current at power supply start-up by connecting a soft-start capacitor with the CS1 terminal (pin 11) and CS2 terminal (pin 14) which are the non-inverted input terminal for Error Amp. The use of Error Amp for soft-start detection makes it possible for a system to operate on a fixed soft-start time that is independent of the output load on the DC/DC converter. (4) PWM comparator block (PWM Comp.) The PWM comparator is a voltage-to-pulse width modulator that controls the output duty depending on the input/ output voltage. The comparator keeps output transistor on while the error amplifier output voltage remain higher than the triangular wave voltage. (5) Output block The output block is in the totem pole configuration, capable of driving an external P-channel MOS FET . (6) Bias voltage block (VH) This bias voltage circuit outputs V CC - 5 V(T yp) as minimum potential of the output circuit. In standby mode, this circuit outputs the potential equal to VCC .
  1. Control Function When CTL terminal (pin 24) is “L” level, IC becomes the standby mode. The power supply current is 10 mA (Max) at the standby mode. On/Off Setting Conditions 3. Protective Functions (1) Timer-latch overcurrent protection circuit block (OCP) The timer-latch overcurrent protection circuit is actuated upon completion of the soft-start period. When an overcurrent flows, the circuit detects the increase in the voltage between the FET’s drain and source using the external FET ON resistor, actuates the timer circuit, and starts charging the capacitor C SCP con-nected to the CSCP terminal (pin 8). If the overcurrent remains flowing beyond the predetermined period of time, latch is set and OUT terminlas (pin 3,22) of each channel are fixed at “H” level. And the circuit sets the latch to turn off the external FET . The detection current value can be set by resistor R LIM1 connected between the FET’s drain and the ILIM1 terminal (pin 5) and resistor RLIM2 connected between the drain and the ILIM2 terminal (pin 20). Changing connection enables to detect overcurrent at current sense resistor. T o reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal (pin 6) to the “L” level to lower the VREF terminal (pin 17) voltage to 2.4 V (Min) or less. (See “1. Setting Timer- Latch Overcurrent Protection Detection Current” in “n ABOUT TIMER-LA TCH PROTECTION CIRCUIT”.) (2) Timer-latch short-circuit protection circuit (SCP Logic, SCP Comp.) The short-circuit detection comparator (SCP Comp.) detects the output voltage level of Error Amp, and if the error amp output voltage of any channel falls below the short-circuit detection voltage (3.1 V T yp), the timer circuits are actuated to start charging the external capacitor C SCP connected to the CSCP terminal (pin 8). When the capacitor voltage reaches about 0.73 V , the circuit is turned off the output transistor and sets the dead time to 100 %. T o reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal (pin 24) to the “L” level to lower the VREF terminal (pin 17) voltage to 2.4 V (Min) or less. (See “2. Setting Time Constant for Timer-Latch Short-Circuit Protection Circuit” in “n ABOUT TIMER-LA TCH PROTECTION CIR- CUIT”.) (3) Under voltage lockout protection circuit (UVLO) The transient state or a momentary decrease in supply voltage, which occurs when the power supply is turned on, may cause the IC to malfunction, resulting in breakdown or degradation of the system. T o prevent such malfunctions, under voltage lockout protection circuit detects a decrease in internal reference voltage with respect to the power supply voltage, turns off the output transistor, and sets the dead time to 100% while holding the CSCP terminal (pin 8) at the “L” level. The circuit restores the output transistor to normal when the supply voltage reaches the threshold voltage of the undervoltage lockout protection circuit. (4) Protection circuit operating function table This table refers to output condition when protection circuit is operating. CTL Power L OFF (Standby) H ON (Operating) Operating circuit CS1 CS2 OUT1 OUT2 Overcurrent protection circuit L L H H Short-circuit protection circuit L L H H Under-voltage lockout L L H H

n SETTING THE OUTPUT VOLTAGE n SETTING THE TRIANGULAR OSCILLATION FREQUENCY The triangular oscillation frequency is determined by the timing capacitor (CT) connected to the CT terminal (pin 13), and the timing resistor (RT) connected to the RT terminal (pin 12). Moreover, it shifts more greatly than the caluculated values according to the constant of timing resistor (RT) when the triangular wave oscillation frequency exceeds 1 MHz. Therefore, set it referring to “T riangular Wave Oscillation Frequency vs. Timing Resistor” and “T riangular Wave Oscillation Frequency vs. Timing Capacitor” in “n TYPICAL CHARACTERISTICS”. T riangular oscillation frequency : f OSC 14(CS2) CS1 (-INE2) -INE1 VO 1.24 V Error Amp 1.24 VO (V) = (R1 + R2)

  • Output Voltage Setting Circuit fOSC (kHz) := 1200000 C T (pF) •R T (kW )

n SETTING THE SOFT-START AND DISCHARGE TIMES T o prevent rush currents when the IC is turned on, you can set a soft-start by connecting soft-start capacitors (CS1 and CS2) to the CS1 terminal (pin 11) for channel 1 and the CS2 terminal (pin 14) for channel 2, respectively. When CTL terminal (pin 24) goes to “H” level and IC starts (VCC ‡ UVLO threshold voltage), the external soft- start capacitors (CS1 and CS2) connected to CS1 and CS2 terminals are charged at 10 mA. The error amplifier output (FB1 (pin 9) , FB2 (pin 16) ) is determined by comparison between the lower one of the potentials at two non-inverted input terminals (1.24 V , CS1 terminal voltages) and the inverted input terminal voltage (-INE1 (pin 10) voltage, -INE2 (pin 15) voltage). The FB1 (FB2) terminal voltage is decided for the soft-start period by the comparison between 1.24 V in an internal reference voltage and the voltages of the CS1 (CS2) terminal. The DC/DC converter output voltage rises in proportion to the CS1 (CS2) terminal voltage as the soft-start capacitor connected to the CS1 (CS2) terminal is charged. The soft-start time is obtained from the following formula: Soft-start time: ts (time to output 100%) S (mF) t := 5 V := 1.24 V := 0 V CS1 (CS2) terminal voltage Error Amp block -INE1 (-INE2) voltage Soft-start time (ts)

(-INE2) CS1 (CS2) C S1 (CS2) -INE1 10 mA FB1 (FB2) VREFVO Error Amp UVLO 1.24 V L priority CH ON/OFF signal L : ON, H : OFF

  • Soft-Start Circuit

n TREATMENT WITHOUT USING CS TERMINAL When not using the soft-start function, open the CS1 terminal (pin 11) and the CS2 terminal (pin 14) .

11 CS1 14CS2

“OPEN”“OPEN”

  • Without Setting Soft-Start Time

n ABOUT TIMER-LATCH PROTECTION CIRCUIT 1. Setting Timer-Latch Overcurrent Protection Detection Current The overcurrent protection circuit is actuated upon completion of the soft-start period. When an overcurrent flows, the circuit detects the increase in the voltage between the FET’s drain and source using the external FET ON resistor (R ON ), actuates the timer circuit, and starts charging the capacitor CSCP connected to the CSCP terminal (pin 8). If the overcurrent remains flowing beyond the predetermined period of time, the circuit sets the latch to fix OUT terminals (pin 3, 22) at “H” level and turn off the external FET . The detection current value can be set by the resistors (R LIM1 and RLIM2) connected between the FET’s drain and the ILIM1 terminal (pin 5) and between the drain and the ILIM2 terminal (pin 20), respectively. The internal current (ILIM) can be set by the timing resistor (RT) connected to the RT terminal (pin 12). Time until activating timer circuit and setting latch is equal to short-circuit detection time in "2. Setting Time Constant for Timer-Latch Short-Circuit Protection Circuit". Internal current value: I LIM Detection current value: IOCP R LIM : Overcurrent detection resistor R ON : External FET ON resistor VIN : Input voltage VO : DC/DC converter output voltage fOSC : Oscillation frequency L : Coil inductance T o reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal (pin 24) to the "L" level to lower the VREF terminal (pin 17) voltage to 2.4 V (Min) or less. ILIM (mA) := 2700 R T (kW ) IOCP (A) := ILIM(A) · RLIM(W ) R ON (W ) (VIN(V) - VO (V)) · VO (V) 2 · VIN(V) · fOSC (Hz) · L(H)---- CSCP Current Protection Logic (1 mA) VREF UVLO S Latch R ILIM1 (RLIM) (ILIM2) VS1 (VS2) VIN Q1 L VO Each Channel Drive

  • Overcurrent detection circuit

Overcurrent Protection Circuit: Range of Operation When an overcurrent flow occurs, if the increased voltage between the drain and source of the FET is detected by means of the external FET (Q1) resistor, operational stability is lost when the external FET (Q1) ON interval determined by the oscillation frequency, input voltage, and output voltage falls below 450 ns. Therefore, the circuit should be used within a range that ensures that the ON interval does not fall below 450ns, according to the following formula. If the ON interval of the external FET (Q1) is below 450ns, we recommend the use of an overcurrent detection resistor RS to detect overcurrent, as shown below. This example shows the range of operation of the overcurrent detection function with a setting of Vo = 3.3V . ON interval 450 (ns) ‡ V O (V) VIN (V) · fOSC (Hz) ILIM1 (ILIM2) VS1 (VS2) VIN ErrAmp (Rs) 1600 1400 1200 1000 800 400 200 6 8 10 12 14 VCC (V) fOSC (kHz) 16 18 20 Overcurrent Detection Function Operating Range VO = set to 3.3 V Operation Range

  • Method to detect by current when external FET(Q1) is turned on Connect to RS when using RS ILIM1 (ILIM2) VS1 (VS2) VIN R S ErrAmp 1600 1400 1200 1000 800 600 400 200 6 8 10 12 14 VCC (V) fOSC (kHz) 16 18 20 Overcurrent Detection Function Operating Range VO = set to 3.3 V Operation Range
  • Method to detect by mean current
  1. Setting Time Constant for Timer-Latch Short-Circuit Protection Circuit Each channel uses the short-circuit detection comparator (SCP Comp.) to always compare the error amplifier¢s output level to the reference voltage (3.1 V T yp). While DC/DC converter load conditions are stable on all channels, the short-circuit detection comparator output remains at “L” level, and the CSCP terminal (pin 8) is held at “L” level. If the load condition on a channel changes rapidly due to a short-circuit of the load, causing the output voltage to drop, the output of the short-circuit detection comparator goes to “H” level. This causes the external short- circuit protection capacitor C SCP connected to the CSCP terminal to be charged at 1 mA. Short-circuit detection time (tSCP ) tSCP (s) := 0.73 · CSCP (mF) When the capacitor CSCP is charged to the threshold voltage (VTH := 0.73 V), the latch is set and the external FET is turned off (dead time is set to 100%). At this time, the latch input is closed and the CSCP terminal is held at “L” level. If a short-circuit is detected on either of the two channels, both channels are shut off. When the power supply is turned on back or VREF terminal (pin 17) voltage is less than 2.4 V (Min) by setting CTL terminal (pin 24) to “L” level, the latch is released. VO (-INE2) -INE1 (FB2) FB1 CSCP Error Amp SCP Comp. (3.1 V) (1.24 V) (1 mA) VREF UVLO S Latch R To each channel Drive
  • Timer-latch short-circuit protection circuit

n TREATMENT WITHOUT USING CSCP TERMINAL When not using the timer-latch short-circuit protection circuit, connect the CSCP terminal (pin 8) to GND with the shortest distance. n RESETTING THE LATCH OF EACH PROTECTION CIRCUIT When the overcurrent, or short-circuit protection circuit detects each abnormality, it sets the latch to fix the output at the "L" level. T o reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal (pin 24) to the "L" level to lower the VREF terminal (pin 17) voltage to 2.4 V (Min) or less.

8 CSCP

  • Treatment without using CSCP

1.24 V

17 VREF

77.8 kW 24.8 kW CTL GND kW 104 kW CSX VCC GND VREF (5.0 V) RT GND (3.1 V) 1.35 V VCC CSCP 2 kW GND VREF (5.0 V) 8 CT GND (3.1 V) -INEX CSX GND VCC VREF (5.0 V) FBX1.24 V ILIMX GND GNDO VCCO VSX VCC DTCX GND VCC FBX CT VCC GND VCCO VH GNDO X : Each channel No. ÆÆReference voltage blockææ ÆÆ Control blockææ ÆÆ Soft-start blockææ ÆÆShort-circuit detection blockææ ÆÆTriangular wave oscillator block (RT) ææ ÆÆTriangular wave oscillator (CT) blockææ ÆÆError amplifier block (CH1, CH2) ææ ÆÆOvercurrent protection circuit blockææ ÆÆPWM comparator block (CH1, CH2) ææ ÆÆOutput block (CH1, CH2) ææ O GNDO VCCO 1 VH ÆÆBias voltage blockææ

A B B + + A + + R10R11 68 kW 220 kW C16 0.1 mF C12 1000 pF C14 1000 pF C21 1000 pF 150 kW 56 kW R15R16 R14 68 kW 220 kW R13C17 0.1 mF 13 kW100 kW VIN (7 V to 19 V) 24 kW 100 pF C20 0.1 mF C10 0.1 mF mF 82 mF mF C11 0.1 mF 2.7 kW Q2 L2 VO 2 (3.3 V) 15 mF mF 82 mF mF 2.7 kW Q1 L1 V O 1 (5.0 V) 15 mF -INE1 CS1 FB1 DTC1 -INE2 CS2 FB2 DTC2 CSCP 12 13 1817 RT CT GNDVREF CTL VCC GNDO VH ILIM2 VS2 OUT2 ILIM1 VS1 OUT1 VCCO 10 mA 1.24 V 1.24 V 3.1 V SCP Comp. SCP Logic UVLO OSC VREF Bias Voltage Current Protection Logic Current Protection Logic IO = 200 mA at VCCO = 12 V IO = 200 mA at VCCO = 12 V VR1 VH VCC - 5 V 1.24 V 2.5 V 1.5 V 5.0 V bias Power ON/OFF CTL 10 mA Pch Drive2 Pch Drive1 PWM Comp.1 PWM Comp.2 Error Amp2 Error Amp1 CH1 CH2 Step- down Step- down L priority L priority L priority L priority H priority accuracy ± 1% UVLO release at OCP at SCP Charging current (1 /K6DA) Error Amp Reference Error Amp Power Supply CH1 ON/OFF signal (Hiz : ON, L : OFF) CH2 ON/OFF signal (Hiz : ON, L : OFF) H : ON (Power ON) L : OFF (Standby mode) V TH = 1.4 V

Note : TOSHIBA : TOSHIBA Corporation ROHM : ROHM Co., Ltd SANYO : SANYO Electric Co., Ltd. TDK : TDK Corporation SUMIDA : SUMIDA Electric Co., Ltd. ssm : SUSUMU Co., Ltd. COMPONENT ITEM SPECIFICA TION VENDOR P ARTS No. Q1, Q2 Pch FET VDS = -30 V, ID = -6 A TOSHIBA TPC8102 D1, D2 Diode VF = 0.42 V (Max) , at IF = 3 A ROHM RB0530L-30 L1, L2 Inductor 15 mH 3.6 A, 50 m W SUMIDA CDRH104R-150 C2, C6 C3, C7 C4, C8 C10, C11, C20 C12, C14, C21 C16, C17 Ceramics Condenser OS-CON TM Ceramics Condenser OS-CON TM Ceramics Condenser Ceramics Condenser Ceramics Condenser 100 pF 10 mF 10 mF 82 mF 0.1 mF 1000 pF 0.1 mF 50 V 20 V 25 V 6.3 V 50 V 50 V 50 V TDK SANYO TDK SANYO TDK TDK TDK C1608CH1H101J 20SVP10M C3225JF1E106Z 6SVP82M C1608JB1H104K C1608JB1H102K C1608JB1H104K R4, R5 R8, R13 R9, R14 R10 R11 R15 R16 Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor 24 kW 2.7 kW 220 kW 68 kW 150 kW 56 kW 100 kW 13 kW 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % ssm ssm ssm ssm ssm ssm ssm ssm RR0816P-243-D RR0816P-272-D RR0816P-224-D RR0816P-683-D RR0816P-154-D RR0816P-563-D RR0816P-104-D RR0816P-133-D

  • Pch MOS FET The P-ch MOSFET for switching use should be rated for at least 20% more than the maximum input voltage. T o minimize continuity loss, use a FET with low RDS(ON) between the drain and source. For high input voltage and high frequency operation, on/off-cycle switching loss will be higher so that power dissipation must be considered. In this application, the T oshiba TPC8102 is used. Continuity loss, on/off switching loss, and total loss are deter- mined by the following formulas. The selection must ensure that peak drain current does not exceed rated values, and also must be in accordance with overcurrent detection levels. Continuity loss : P C On-cycle switching loss : PS (ON) Off-cycle switching loss : PS (OFF) T otal loss : PT PT = PC + PS (ON) + PS (OFF) Example: Using the T oshiba TPC8102 CH1 Input voltage V IN (Max) = 19 V, output voltage VO = 5 V, drain current ID = 3 A, Oscillation frequency fOSC = 500 kHz, L = 15 mH, drain-source on resistance RDS (ON) := 50 mW , tr = tf := 100 ns. Drain current (Max) : ID (Max) Drain current (Min) : ID (Min) PC = ID 2 · RDS (ON) · Duty PS (ON) = VD (Max) · ID · tr · fOSC PS (OFF) = VD (Max) · ID (Max) · tf · fOSC ID (Max) = IO + VIN - VO ton2L = 3 + 19 - 5 · 1 · 0.2632 · 15 · 10-6 500 · 103 := 3.25 (A) ID (Min) = IO - VIN - VO ton2L = 3 - 19 - 5 · 1 · 0.2632 · 15 · 10-6 500 · 103 := 2.75 (A)

The above power dissipation figures for the TPC8102 are satisfied with ample margin at 2.4 W (T a = +25 °C) . CH2 Input voltage VIN (Max) = 19 V output voltage VO = 3.3 V, drain current ID = 3 A, Oscillation frequency fOSC = 500 kHz, L = 15 mH, drain-source on resistance RDS (ON) := 50 mW , tr = tf := 100 ns. Drain current (Max) : ID (Max) Drain current (Min) : ID (Min) PC = ID 2 · RDS (ON) · Duty = 3 2 · 0.05 · 0.263 := 0.118 W PS (ON) = VD (Max) · ID · tr · fOSC = 19 · 3 · 100 · 10-9 · 500 · 103 := 0.475 W PS (OFF) = VD (Max) · ID (Max) · tf · fOSC = 19 · 3.25 · 100 · 10-9 · 500 · 103 := 0.515 W PT = PC + PS (ON) + PS (OFF) := 1.108 W ID (Max) = IO + VIN - VO ton2L = 3 + 19 - 3.3 · 1 · 0.1742 · 15 · 10-6 500 · 103 := 3.18 (A) ID (Min) = IO - VIN - VO ton2L = 3 - 19 - 3.3 · 1 · 0.1742 · 15 · 10-6 500 · 103 := 2.82 (A)

The above power dissipation figures for the TPC8102 are satisfied with ample margin at 2.4 W (T a = +25 °C) .

  • Inductors In selecting inductors, it is of course essential not to apply more current than the rated capacity of the inductor, but also to note that the lower limit for ripple current is a critical point that if reached will cause discontinuous operation and a considerable drop in efficiency. This can be prevented by choosing a higher inductance value, which will enable continuous operation under light loads. Note that if the inductance value is too high, however, direct current resistance (DCR) is increased and this will also reduce efficiency. The inductance must be set at the point where efficiency is greatest. Note also that the DC superimposition characteristics become worse as the load current value approaches the rated current value of the inductor, so that the inductance value is reduced and ripple current increases, causing loss of efficiency. The selection of rated current value and inductance value will vary depending on where the point of peak efficiency lies with respect to load current. Inductance values are determined by the following formulas. The L value for all load current conditions is set so that the peak to peak value of the ripple current is 1/2 the load current or less. Inductance value : L P C = ID 2 · RDS (ON) · Duty := 0.078 W PS (ON) = VD (Max) · ID · tr · fOSC = 19 · 3 · 100 · 10-9 · 500 · 103 := 0.475 W PS (OFF) = VD (Max) · ID (Max) · tf · fOSC = 19 · 3.18 · 100 · 10-9 · 500 · 103 := 0.504 W PT = PC + PS (ON) + PS (OFF) := 1.057 W L ‡ 2 (VIN - VO ) tonIO

Example: CH1 CH2 Inductance values derived from the above formulas are values that provide sufficient margin for continuous operation at maximum load current, but at which continuous operation is not possible at light loads. It is therefore necessary to determine the load level at which continuous operation becomes possible. In this application, the Sumida CDRH104R-150 is used. At 15 mH, the load current value under continuous operating conditions is determined by the following formula. Load current value under continuous operating conditions : I O Example: Using the CDRH104R-150 15 mH (allowable tolerance –30% ) , rated current = 3.6 A CH1 CH2 L ‡ 2 (VIN - VO ) tonIO ‡ 2 · (19 - 5) · 1 · 0.263IO 500 · 103 ‡ 4.91 mH L ‡ 2 (VIN - VO ) tonIO ‡ 2 · (19 - 3.3) · 1 · 0.174IO 500 · 103 ‡ 3.64 mH IO ‡ VO toff2L IO ‡ VO toff2L ‡ 5 · 1 · (1 - 0.263) 2 · 15 · 10-6 500 · 103 ‡ 245.7 mA IO ‡ VO toff2L ‡ 3.3 1 · (1 - 0.174) 2 · 15 · 10-6 500 · 103 ‡ 181.7 mA

T o determine whether the current through the inductor is within rated values, it is necessary to determine the peak value of the ripple current as well as the peak-to-peak values of the ripple current that affect the output ripple voltage. The peak value and peak-to-peak value of the ripple current can be determined by the following formulas. Peak value : I L Peak-to-peak value : DIL Example: Using the CDRH104R-150 15 mH (allowable tolerance –30% ) , rated current = 3.6 A Peak value: CH1 CH2 Peak-to-peak value: CH1 CH2 IL ‡ IO + VIN - VO ton2L DIL = VIN - VO tonL IL ‡ IO + VIN - VO ton2L ‡ 3 + 19 - 5 1 · 0.2632 · 15 · 10-6 500 · 103 ‡ 3.25 A IL ‡ IO + VIN - VO ton2L ‡ 3 + 19 - 3.3 · 1 · 0.1742 · 15 · 10-6 500 · 103 ‡ 3.18 A DIL = VIN - VO tonL = 19 - 5 1 · 0.26315 · 10-6 500 · 103 = 0.491 A DIL = VIN - VO tonL = 19 - 3.3 · 1 · 0.17415 · 10-6 500 · 103 = 0.364 A

  • Flyback diode The flyback diode is generally used as a Shottky barrier diode (SBD) when the reverse voltage to the diode is less than 40V . The SBD has the characteristics of higher speed in terms of faster reverse recovery time, and lower forward voltage, and is ideal for achieving high efficiency. As long as the DC reverse voltage is sufficiently higher than the input voltage, the average current flowing through the diode is within the average output current level, and peak current is within peak surge current limits, there is no problem. In this application the Rohm RB053L-30 is used. The diode average current and diode peak current can be calculated by the following formulas. Diode mean current : I Di Diode peak current : IDip Example: Using the Rohm RB053L-30 VR (DC reverse voltage) = 30 V, average output voltage = 3.0 A, peak surge current = 70 A, VF (forward voltage) = 0.42 V, IF = 3.0 A CH1 CH2 CH1 CH2 I Di ‡ IO · (1 - VO ) VIN IDip ‡ (IO + VO toff) 2L ID i ‡ IO · (1 - VO ) VIN ‡ 3 · (1 - 0.263) ‡ 2.21 A ID i ‡ IO · (1 - VO ) VIN ‡ 3 · (1 - 0.174) ‡ 2.48 A ID ip ‡ (IO + VO toff) 2L ‡ 3.24 A ID ip ‡ (IO + VO toff) 2L ‡ 3.18 A
  • Smoothing Capacitor The smoothing capacitor is an indispensable element for reducing ripple voltage in output. In selecting a smooth- ing capacitor it is essential to consider equivalent series resistance (ESR) and allowable ripple current. Higher ESR means higher ripple voltage, so that to reduce ripple voltage it is necessary to select a capacitor with low ESR. However, the use of a capacitor with low ESR can have substantial effects on loop phase characteristics, and therefore requires attention to system stability. Care should also be taken to use a capacity with sufficient margin for allowable ripple current. This application uses the (OS-CON TM ) 6SVP82M made by Sanyo. The ESR, capacitance value, and ripple current can be calculated from the following formulas. Equivalent Series Resistance : ESR Capacitance value : CL Ripple current : ICLrms Example: Using the 6SVP82M Rated voltage = 6.3 V, ESR = 50 mW , maximum allowable ripple current = 1570 mArms Equivalent series resistance CH1 ESR £ DVO - 1 DIL 2pfCL C L DIL 2pf (DVO - DIL · ESR) ICLrms ‡ (VIN - VO ) ton 2Ö3L ESR £ DVO - 1 DIL 2pfCL £ 0.050 - 1 0.491 2 p · 500 · 103 · 82 · 10-6 £ 98.0 mW

ESR £ DV O - 1 DIL 2pfCL £ 0.033 - 1 0.364 2 p · 500 · 103 · 82 · 10-6 £ 86.8 mW C L ‡ DIL 2pf (DVO - DIL · ESR) ‡ 0.491 ‡ 6.14 mF C L ‡ DIL 2pf (DVO - DIL · ESR) ‡ 0.364 ‡ 7.83 mF ICLrms ‡ (VIN - VO ) ton 2Ö3L ‡ (19 - 5) · 0.263 2Ö3 · 15 · 10-6 · 500 · 103 ‡ 141.7 mArms ICLrms ‡ (VIN - VO ) ton 2Ö3L 2Ö3 · 15 · 10-6 · 500 · 103 ‡ 105.1 mArms

(Continued) Vin = 7 V Vin = 10 V Vin = 19 V Vin = 12 V 100 10 m 100 m 1 10 Vin = 7 V Vin = 10 V Vin = 19 V Vin = 12 V 100 10 m 100 m 1 10 TOTAL efficiency h (% ) Input voltage VIN (V) TOTAL Efficiency vs. Input Voltage Each CH efficiency h (% ) Input voltage VIN (V) Each CH Efficiency vs. Input Voltage Ta = +25 °C

5 V Output

SW1 = OFF SW2 = ON Ta = +25 °C

3.3 V Output

SW1 = ON SW2 = OFF

(Continued) VG (V) V S (V) t (ms) Ta = +25 °C VIN = 12 V CTL = 5 V VO = 5 V RL = 1.67 W 0123456789 1 0 VG (V) V S (V) t (ms) Ta = +25 °C VIN = 12 V CTL = 5 V VO = 3.3 V RL = 1.1 W 0123456789 1 0 Switching Wave Form (CH1) Switching Wave Form (CH2)

  • ••• Printed circuit board ground lines should be set up with consideration for common impedance.
  • ••• Take appropriate static electricity measures.
  • Containers for semiconductor materials should have anti-static protection or be made of conductive material.
  • After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.
  • Work platforms, tools, and instruments should be properly grounded.
  • Working personnel should be grounded with resistance of 250 kW to 1 MW between body and ground.
  • ••• Do not apply negative voltages. The use of negative voltages below –0.3 V may create parasitic transistors on LSI lines, which can cause abnormal operation. n ORDERING INFORMATION Part number Package Remarks MB39A104PFV 24-pin plastic SSOP (FPT-24P-M03)

(FPT-24P-M03) Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) MAX) . Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. Dimensions in mm (inches) Note : The values in parentheses are reference values. C 2003 FUJITSU LIMITED F24018S-c-4-5 0.10(.004) 11 2 1324 0.65(.026) –0.07 +0.08 0.24 .009 +.003 –.003 M0.13(.005) INDEX 0.17±0.03 (.007±.001) "A" 0.25(.010) 0.10±0.10 (.004±.004) (Stand off) Details of "A" part (Mounting height)1.25 +0.20 –0.10 –.004 +.008 .049 0~8˚ 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.10(.004)

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