6PAIC3101IRHBRG4

TLV320AIC3101 TI

Document overview

• Manufacturer or author: Provided By digicamel.com
• PDF pages: 99

Technical content

Sample & Buy T echnical Documents Tools & Software Support & Community TLV320AIC3101 SLAS520E –FEBRUARY 2007–REVISED DECEMBER 2014 TLV320AIC3101Low-PowerStereoAudioCodecforPortableAudio/Telephony

1 Features • Extensive Modular Power Control

• Power Supplies: 1• Stereo Audio DAC – Analog: 2.7 V–3.6 V.– 102-dBA Signal-to-Noise Ratio – Digital Core: 1.525 V–1.95 V– 16/20/24/32-Bit Data – Digital I/O: 1.1 V–3.6 V– Supports Sample Rates From 8 kHz to 96 kHz
• Package: 5-mm × 5-mm 32-Pin QFN– 3D/Bass/Treble/EQ/De-Emphasis Effects – Flexible Power Saving Modes and 2 ApplicationsPerformance are Available
• Digital Cameras• Stereo Audio ADC
• Smart Cellular Phones– 92-dBA Signal-to-Noise Ratio – Supports Sample Rates From 8 kHz to 96 kHz 3 Description– Digital Signal Processing and Noise Filtering The TLV320AIC3101 is a low-power stereo audioAvailable During Record codec with stereo headphone amplifier, as well as
• Six Audio Input Pins multiple inputs and outputs that are programmable in single-ended or fully differential configurations.– One Stereo Pair of Single-Ended Inputs Extensive register-based power control is included,– One Stereo Pair of Fully Differential Inputs enabling stereo 48-kHz DAC playback as low as 14
• Six Audio Output Drivers mW from a 3.3-V analog supply, making it ideal for portable battery-powered audio and telephony– Stereo Fully Differential or Single-Ended applications.Headphone Drivers – Fully Differential Stereo Line Outputs The record path of the TLV320AIC3101 contains integrated microphone bias, digitally controlled stereo– Stereo 8-Ω, 500-mW/Channel Speaker Drive microphone preamplifier, and automatic gain controlCapability (AGC), with mix/mux capability among the multiple• Low Power: 14-mW Stereo 48-kHz Playback With analog inputs. Programmable filters are available 3.3-V Analog Supply during record which can remove audible noise that can occur during optical zooming in digital cameras.• Ultralow-Power Mode With Passive Analog The playback path includes mix/mux capability fromBypass the stereo DAC and selected inputs, through• Programmable Input/Output Analog Gains programmable volume controls, to the various• Automatic Gain Control (AGC) for Record outputs.
• Programmable Microphone Bias Level Device Information(1)
• Programmable PLL for Flexible Clock Generation PART NUMBER PACKAGE BODY SIZE (NOM)• I2C Control Bus TLV320AIC3101 VQFN (32) 5.00 mm x 5.00 mm• Audio Serial Data Bus Supports I2S, Left/Right- (1) For all available packages, see the orderable addendum atJustified, DSP, and TDM Modes the end of the datasheet.

4 Simplified Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

SLAS520E –FEBRUARY 2007–REVISED DECEMBER 2014 www.ti.com Table of Contents

5 Revision History

Changes from Revision D (December 2008) to Revision E Page

• Added the Device information table, ESD Ratings table, Applications and Implementation section, Layout section,

2 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Product Folder Links: TLV320AIC3101

www.ti.com SLAS520E –FEBRUARY 2007–REVISED DECEMBER 2014

6 Description (continued)

The TLV320AIC3101 contains four high-power output drivers as well as two fully differential output drivers. The high-power output drivers are capable of driving a variety of load configurations, including up to four channels of single-ended 16-Ω headphones using ac-coupling capacitors, or stereo 16-Ω headphones in a capless output configuration. In addition, pairs of drivers can be used to drive 8-Ω speakers in a BTL configuration at 500 mW per channel. The stereo audio DAC supports sampling rates from 8 kHz to 96 kHz and includes programmable digital filtering in the DAC path for 3D, bass, treble, midrange effects, speaker equalization, and de-emphasis for 32-kHz, 44.1- kHz, and 48-kHz sample rates. The stereo audio ADC supports sampling rates from 8 kHz to 96 kHz and is preceded by programmable gain amplifiers or AGC that can provide up to 59.5-dB analog gain for low-level microphone inputs. The TLV320AIC3101 provides an extremely high range of programmability for both attack (8–1,408 ms) and for decay (0.05–22.4 seconds). This extended AGC range allows the AGC to be tuned for many types of applications. For battery saving applications where neither analog nor digital signal processing are required, the device can be put in a special analog signal passthrough mode. This mode significantly reduces power consumption, as most of the device is powered down during this passthrough operation. The serial control bus supports the I2C protocol, whereas the serial audio data bus is programmable for I2S, left/right-justified, DSP, or TDM modes. A highly programmable PLL is included for flexible clock generation and support for all standard audio rates from a wide range of available MCLKs, varying from 512 kHz to 50 MHz, with special attention paid to the most-popular cases of 12-MHz, 13-MHz, 16-MHz, 19.2-MHz, and 19.68-MHz system clocks. The TLV320AIC3101 operates from an analog supply of 2.7 V–3.6 V, a digital core supply of 1.525 V–1.95 V, and a digital I/O supply of 1.1 V–3.6 V. The device is available in a 5-mm × 5-mm 32-pin QFN package.

7 Device Comparison Table

TLV320AIC3101 Low-Power Stereo CODEC with 6 Inputs, 6 Outputs, Speaker/HP Amp and Enhanced Digital Effects TLV320AIC3104 Same as TLV320AIC3101, but without Speaker Amp. TLV320AIC3105 Same as TLV320AIC3101, but with all inputs Single-ended. TLV320AIC3106 Same as TLV320AIC3101, but with 10 Inputs and 7 Outputs. TLV320AIC3107 Same as TLV320AIC3101, but with 7 Inputs, 6 Outputs and Integrated Mono Class-D Amplifier Copyright © 2007–2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TLV320AIC3101

RIGHT_LOM HPRCOM RIGHT_LOP DRVSS LEFT_LOM HPLCOM LEFT_LOP HPLOUT A VSS2 DRVDD A VDD A VSS1 TLV320AIC3101 SLAS520E –FEBRUARY 2007–REVISED DECEMBER 2014 www.ti.com

8 Pin Configuration and Functions

(Bottom View) NOTE: Connect device thermal pad to DRVSS. Pin Functions PIN

DESCRIPTION

NAME NO. I/O AVDD 25 — Analog DAC voltage supply, 2.7 V–3.6 V AVSS1 17 — Analog ADC ground supply, 0 V AVSS2 26 — Analog DAC ground supply, 0 V BCLK 2 I/O Audio serial data bus bit clock input/output DIN 4 I Audio serial data bus data input DOUT 5 O Audio serial data bus data output DRVDD 18 — Analog ADC and output driver voltage supply, 2.7 V–3.6 V DRVDD 24 — Analog output driver voltage supply, 2.7 V–3.6 V DRVSS 21 — Analog output driver ground supply, 0 V DVDD 32 — Digital core voltage supply, 1.525 V–1.95 V DVSS 6 — Digital core / I/O ground supply, 0 V HPLCOM 20 O High-power output driver (left – or multifunctional) HPLOUT 19 O High-power output driver (left +) HPRCOM 22 O High-power output driver (right – or multifunctional) HPROUT 23 O High-power output driver (right +) IOVDD 7 — Digital I/O voltage supply, 1.1 V–3.6 V LEFT_LOM 28 O Left line output (–) LEFT_LOP 27 O Left line output (+) MCLK 1 I Master clock input MIC1LM/LINE1LM 11 I Left input – (diff only) MIC1LP/LINE1LP 10 I Left input 1 (SE) or left input + (diff) MIC1RM/LINE1RM 13 I Right input – (diff only) MIC1RP/LINE1RP 12 I Right input 1 (SE) or right input + (diff) MIC2L/LINE2L/MICDET 14 I Left input 2 (SE); can support microphone detection

4 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Product Folder Links: TLV320AIC3101

www.ti.com SLAS520E –FEBRUARY 2007–REVISED DECEMBER 2014 Pin Functions (continued) PIN NAME NO. I/O MIC2R/LINE2R 16 I Right input 2 (SE) MICBIAS 15 O Microphone bias voltage output RESET 31 I Reset RIGHT_LOM 30 O Right line output (–) RIGHT_LOP 29 O Right line output (+) SCL 8 I/O I2C serial clock input SDA 9 I/O I2C serial data input/output WCLK 3 I/O Audio serial data bus word clock input/output Copyright © 2007–2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TLV320AIC3101

SLAS520E –FEBRUARY 2007–REVISED DECEMBER 2014 www.ti.com

9 Specifications

9.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) (2) MIN MAX UNIT AVDD to AVSS, DRVDD to DRVSS –0.3 3.9 V AVDD to DRVSS –0.3 3.9 V Input voltage IOVDD to DVSS –0.3 3.9 V DVDD to DVSS –0.3 2.5 V AVDD to DRVDD –0.1 0.1 V Digital input voltage to DVSS –0.3 IOVDD + 0.3 V Analog input voltage to AVSS –0.3 AVDD + 0.3 V Operating temperature –40 85 °C Junction temperature, TJ 105 °C Storage temperature, Tstg –65 105 °C Power dissipation 0.5 W (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) ESD complicance tested to EIA/JESD22-A114-B and passed.

9.2 ESD Ratings

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V(ESD) Electrostatic discharge VCharged-device model (CDM), per JEDEC specification JESD22- ±1500C101(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

9.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT AVDD, DRVDD1/2(1) Analog supply voltage 2.7 3.3 3.6 V DVDD(1) Digital core supply voltage 1.525 1.8 1.95 V IOVDD(1) Digital I/O supply voltage 1.1 1.8 3.6 V VI Analog full-scale 0-dB input voltage (DRVDD1 = 3.3 V) 0.707 VRMS Stereo line output load resistance 10 kΩ Stereo headphone output load resistance 16 Ω Digital output load capacitance 10 pF TA Operating free-air temperature –40 85 °C (1) Analog voltage values are with respect to AVSS1, AVSS2, DRVSS; digital voltage values are with respect to DVSS.

6 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Product Folder Links: TLV320AIC3101

www.ti.com SLAS520E –FEBRUARY 2007–REVISED DECEMBER 2014

9.4 Thermal Information

THERMAL METRIC(1) UNIT

32 PINS

RθJA Junction-to-ambient thermal resistance 32.1 RθJC(top) Junction-to-case (top) thermal resistance 23.0 RθJB Junction-to-board thermal resistance 6.0 °C/W ψJT Junction-to-top characterization parameter 0.3 ψJB Junction-to-board characterization parameter 6.0 RθJC(bot) Junction-to-case (bottom) thermal resistance 1.4 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

9.5 Electrical Characteristics

At 25°C, AVDD_DAC = DRVDD = IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48 kHz, 16-bit audio data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AUDIO ADC Input signal level Single-ended 0.707 VRMS SNR Signal-to-noise ratio (1) (2) A-weighted, fS = 48 ksps, 0-dB PGA gain, inputs ac-shorted to ground 80 92 dB Dynamic range (1) (2) fS = 48 ksps; 0-dB PGA gain; 1-kHz, –60-dB full-scale input signal 93 dB THD Total harmonic distortion fS = 48 ksps; 0-dB PGA gain; 1-kHz, –2-dB full-scale input signal –89 –75 dB 217-Hz signal applied to DRVDD 55 PSRR Power-supply rejection ratio dB 1-kHz signal applied to DRVDD 44 Input channel separation 1-kHz, –2-dB full-scale signal, MIC1L to MIC1R –71 dB Gain error fS = 48 ksps; 0-dB PGA gain; 1-kHz, –2-dB full-scale input signal 0.82 dB ADC programmable-gain 1-kHz input tone 59.5 dBamplifier maximum gain ADC programmable-gain 0.5 dBamplifier step size MIC1L/MIC1R inputs routed to single ADC 20input mix attenuation = 0 dB MIC1L/MIC1R inputs routed to single ADC 80input mix attenuation = 12 dB MIC2L/MIC2R inputs routed to single ADC 20input mix attenuation = 0 dB Input resistance kΩ MIC2L/MIC2R inputs routed to single ADC 80input mix attenuation = 12 dB MIC3L/MIC3R inputs routed to single ADC 20input mix attenuation = 0 dB MIC3L/MIC3R inputs routed to single ADC 80input mix attenuation = 12 dB Input resistance 80 kΩ Input capacitance MIC1/LINE1 inputs 10 pF Input level control minimum 0 dBattenuation setting Input level control maximum 12 dBattenuation setting Input level control attenuation 1.5 dBstep size ANALOG PASSTHROUGH MODE MIC1/LIN1 to LINEOUT 330Input-to-output switchRDS(on) Ωresistance MIC2/LIN2 to LINEOUT 330 (1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer. (2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values. Copyright © 2007–2014, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TLV320AIC3101

SLAS520E –FEBRUARY 2007–REVISED DECEMBER 2014 www.ti.com Electrical Characteristics (continued) At 25°C, AVDD_DAC = DRVDD = IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48 kHz, 16-bit audio data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SIGNAL LEVEL, DIFFERENTIAL SNR Signal-to-noise ratio A-weighted, fS = 48 ksps, 0 dB PGA gain, inputs ac-shorted to ground 92 dB THD Total harmonic distortion fS = 48 kHz; 0-dB PGA gain, 1-kHz, –2-dB full-scale input signal –94 dB ADC DIGITAL DECIMATION FILTER, fS = 48 kHz From 0 to 0.39 fS ±0.1 At 0.4125 fS –0.25 Filter gain At 0.45 fS –3 dB At 0.5 fS –17.5 From 0.55 fS to 64 fS –75 Filter group delay 17/fS s MICROPHONE BIAS Programmable setting = 2 V 2 Programmable setting = 2.5 V 2.3 2.455 2.7Bias voltage V DRVDD –Programmable setting = DRVDD 0.24 Current sourcing Programmable setting = 2.5 V 4 mA AUDIO DAC – DIFFERENTIAL LINE OUTPUT, RLOAD = 10 kΩ 1.414 VRMS0-dB input full-scale signal, output common-mode setting = 1.35 V,Full-scale output voltage output volume control = 0 dB 4 VPP A-weighted, fS = 48 kHz, output volume control = 0 dB, no input signal,Signal-to-noise ratio (3) 90 102 dBreferenced to full-scale input level A-weighted, fS = 48 kHz, –60-dB input full-scale signal, output volumeDynamic range 97 dBcontrol = 0 dB, output common-mode setting = 1.35 V fS = 48 kHz; 0-dB, 1-kHz input full-scale signal; output volume controlTotal harmonic distortion –95 –75 dB= 0 dB; output common-mode setting = 1.35 V 217-Hz signal applied to DRVDD, AVDD_DAC 78 PSRR Power-supply rejection ratio dB 1-kHz signal applied to DRVDD, AVDD_DAC 80 DAC channel separation 0-dB full-scale input signal between left and right lineout 86 dB DAC interchannel gain 1-kHz input, 0-dB gain 0.1 dBmismatch 0-dB, 1-kHz input full-scale signal; output volume control = 0 dB;DAC gain error –0.2 dBoutput common-mode setting = 1.35 V; fS = 48 kHz AUDIO DAC – SINGLE ENDED LINE OUTPUT, RLOAD = 10 kΩ 0-dB input full-scale signal, output common-mode setting = 1.35 V,Full-scale output voltage 0.707 VRMSoutput volume control = 0 dB A-weighted, fS = 48 kHz, output volume control = 0 dB, no input signal,SNR Signal-to-noise ratio 97 dBoutput common-mode setting = 1.35 V fS = 48 kHz; 0-dB, 1-kHz input full-scale signal; output volume controlTHD Total harmonic distortion –84 dB= 0 dB; output common-mode setting = 1.35 V 0-dB, 1-kHz input full-scale signal; output volume control = 0 dB;DAC gain error 0.55 dBoutput common-mode setting = 1.35 V; fS = 48 kHz AUDIO DAC – SINGLE-ENDED HEADPHONE OUTPUT, RLOAD = 16 Ω 0-dB input full-scale signal, output common-mode setting = 1.35 V,Full-scale output voltage 0.707 VRMSoutput volume control = 0 dB A-weighted, fS = 48 kHz, output volume control = 0 dB, no input signal, 96referenced to full-scale input level SNR Signal-to-noise ratio dB A-weighted, fS = 48 kHz, output volume control = 0 dB, no input signal, 97referenced to full-scale input level, 50% DAC current-boost mode A-weighted, fS = 48 kHz, –60-dB input full-scale signal, output volumeDynamic range 91 dBcontrol = 0 dB, output common-mode setting = 1.35 V fS = 48 kHz, 0-dB input full-scale signal, output volume control = 0 dB,THD Total harmonic distortion –71 –65 dBoutput common-mode setting = 1.35 V (3) Unless otherwise noted, all measurements use output common-mode voltage setting of 1.35 V, 0-dB output level control gain, 16-Ω single-ended load.

8 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Product Folder Links: TLV320AIC3101

www.ti.com SLAS520E –FEBRUARY 2007–REVISED DECEMBER 2014 Electrical Characteristics (continued) At 25°C, AVDD_DAC = DRVDD = IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48 kHz, 16-bit audio data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 217-Hz signal applied to DRVDD, AVDD_DAC 43 PSRR Power-supply rejection ratio dB 1-kHz signal applied to DRVDD, AVDD_DAC 41 DAC channel separation Right headphone out 89 dB 0-dB, 1-kHz input full-scale signal; output volume control = 0 dB;DAC gain error –0.85 dBoutput common-mode setting = 1.35 V; fS = 48 kHz AUDIO DAC – DIFFERENTIAL SPEAKER OUTPUT, RLOAD = 8 Ω 0-dB input full-scale signal, output common-mode setting = 1.35 V,Full-scale output voltage 1.4142 VRMSoutput volume control = 0 dB A-weighted, fS = 48 kHz, output volume control = 0 dB, no input signal,SNR Signal-to-noise ratio 86 dBoutput common-mode setting = 1.35 V fS = 48 kHz, 0-dB input full-scale signal, output volume control = 0 dB,THD Total harmonic distortion –70 dBoutput common-mode setting = 1.35 V fS = 48 kHz, 0-dB input full-scale signal, output volume control = 0 dB,DAC gain error –1 dBoutput common-mode setting = 1.35 V DAC DIGITAL INTERPOLATION – FILTER fS = 48 kHz Pass band 0 0.45 fS Hz Pass-band ripple ±0.06 dB Transition band 0.45 fS 0.55 fS Hz Stop band 0.55 fS 7.5 fS Hz Stop-band attenuation 65 dB Group delay 21/fS s STEREO HEADPHONE DRIVER – AC-COUPLED OUTPUT CONFIGURATION (3) 0-dB gain to high-power outputs. Output common-mode voltage0-dB full-scale output voltage 0.707 VRMSsetting = 1.35 V First option 1.35 Programmable output Second option 1.5common-mode voltage V(applicable to line outputs Third option 1.65 also) Fourth option 1.8 Maximum programmable 9 dBoutput level control gain Programmable output level 1 dBcontrol gain step size RL = 32 Ω 15 PO Maximum output power mW RL = 16 Ω 30 Signal-to-noise ratio(4) A-weighted 94 dB –77 1-kHz output, PO = 5 mW, RL = 32 Ω 0.014 –76 1-kHz output, PO = 10 mW, RL = 32 Ω 0.016 Total harmonic distortion dB% –73 1-kHz output, PO = 10 mW, RL = 16 Ω 0.022 –71 1-kHz output, PO = 20 mW, RL = 16 Ω 0.028 Channel separation 1-kHz, 0-dB input 90 dB Power supply rejection ratio 217 Hz, 100 mVpp on AVDD, DRVDD1/2 48 dB Mute attenuation 1-kHz output 107 dB (4) Ratio of output level with a 1-kHz full-scale input, to the output level playing an all-zero signal, measured A-weighted over a 20-Hz to 20- kHz bandwidth. Copyright © 2007–2014, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: TLV320AIC3101

SLAS520E –FEBRUARY 2007–REVISED DECEMBER 2014 www.ti.com Electrical Characteristics (continued) At 25°C, AVDD_DAC = DRVDD = IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48 kHz, 16-bit audio data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL I/O 0.3VIL Input low level –0.3 VIOVDD 0.7IOVDD > 1.6 V IOVDDVIH Input high level (5) V IOVDD ≤ 1.6 V 1.1 0.1VOL Output low level VIOVDD 0.8VOH Output high level VIOVDD CURRENT CONSUMPTION – DRVDD = AVDD_DAC = IOVDD = 3.3 V, DVDD = 1.8 V IDRVDD + IAVDD_DAC 0.1 RESET held low μA IDVDD 0.2 IDRVDD + IAVDD_DAC 2.15 Mono ADC record, fS = 8 ksps, I2S slave, AGC off, no signal IDVDD 0.48 IDRVDD + IAVDD_DAC 4.1 Stereo ADC record, fS = 8 ksps, I2S slave, AGC off, no signal IDVDD 0.62 IDRVDD + IAVDD_DAC 4.31(6) Stereo ADC record, fS = 48 ksps, I2S slave, AGC off, no signalIDVDD 2.45(6) IDRVDD + IAVDD_DAC 3.5Stereo DAC playback to lineout, analog mixer bypassed, fS = 48 ksps, I2S slaveIDVDD 2.3 IIN mA IDRVDD + IAVDD_DAC 4.9 Stereo DAC playback to lineout, fS = 48 ksps, I2S slave, no signal IDVDD 2.3 IDRVDD + IAVDD_DAC 6.7Stereo DAC playback to stereo single-ended headphone, fS = 48 ksps, I2S slave, no signalIDVDD 2.3 IDRVDD + IAVDD_DAC 3.11 Stereo linein to stereo lineout, no signal IDVDD 0 IDRVDD + IAVDD_DAC 1.4 Extra power when PLL enabled IDVDD 0.9 IDRVDD + IAVDD_DAC 28All blocks powered down. Headset detection enabled, headset not μAinsertedIDVDD 2 (5) When IOVDD < 1.6 V, minimum VIH is 1.1 V. (6) Additional power is consumed when the PLL is powered.

10 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Product Folder Links: TLV320AIC3101

www.ti.com SLAS520E –FEBRUARY 2007–REVISED DECEMBER 2014

9.6 Timing Requirements: Audio Data Serial Interface(1)

IOVDD = 1.1 V IOVDD = 3.3 V PARAMETER UNIT MIN MAX MIN MAX I2S/LJF/RJF Timing in Master Mode td(WS) ADWS/WCLK delay time 50 15 ns td(DO-WS) ADWS/WCLK to DOUT delay time 50 20 ns td(DO-BCLK) BCLK to DOUT delay time 50 15 ns ts(DI) DIN setup time 10 6 ns th(DI) DIN hold time 10 6 ns tr Rise time 30 10 ns tf Fall time 30 10 ns DSP Timing in Master Mode td(WS) ADWS/WCLK delay time 50 15 ns td(DO-BCLK) BCLK to DOUT delay time 50 15 ns ts(DI) DIN setup time 10 6 ns th(DI) DIN hold time 10 6 ns tr Rise time 30 10 ns tf Fall time 30 10 ns I2S/LJF/RJF Timing in Slave Mode tH(BCLK) BCLK high period 70 35 ns tL(BCLK) BCLK low period 70 35 ns ts(WS) ADWS/WCLK setup time 10 6 ns th(WS) ADWS/WCLK hold time 10 6 ns td(DO-WS) ADWS/WCLK to DOUT delay time (for LJF Mode only) 50 35 ns td(DO-BCLK) BCLK to DOUT delay time 50 20 ns ts(DI) DIN setup time 10 6 ns th(DI) DIN hold time 10 6 ns tr Rise time 8 4 ns tf Fall time 8 4 ns DSP Timing in Slave Mode tH(BCLK) BCLK high period 70 35 ns tL(BCLK) BCLK low period 70 35 ns ts(WS) ADWS/WCLK setup time 10 8 ns th(WS) ADWS/WCLK hold time 10 8 ns td(DO-BCLK) BCLK to DOUT delay time 50 20 ns ts(DI) DIN setup time 10 6 ns th(DI) DIN hold time 10 6 ns tr Rise time 8 4 ns tf Fall time 8 4 ns (1) All timing specifications are measured at characterization but not tested at final test. Copyright © 2007–2014, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TLV320AIC3101

All specifications at 25°C, DVDD = 1.8 V. Figure 1. I2S/LJF/RJF Timing in Master Mode Figure 2. DSP Timing in Master Mode

12 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

t (WS)h t (WS)h t (BCLK)L t (DO-BCLK)d t (DI)S t (BCLK)H t (DI)h t (WS)S t (WS)S T0145-02 WCLK BCLK SDOUT SDIN t (WS)h t (BCLK)H t (DO-BCLK)d t (DO-WS)d t (DI)S t (BCLK)L t (DI)h t (WS)S TLV320AIC3101 www.ti.com SLAS520E –FEBRUARY 2007–REVISED DECEMBER 2014 I2S/LJF/RJF Timing in Slave Mode DSP Timing in Slave Mode Copyright © 2007–2014, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: TLV320AIC3101

9.7 Typical Characteristics

Figure 4. THD vs Headphone Power, CaplessFigure 3. THD vs Headphone Power, AC-Coupled Figure 5. DAC to Line Output FFT Plot Figure 6. Line Input to ADC FFT Plot Figure 7. THD vs Speaker Power, 8 Ω Load Figure 8. ADC SNR vs PGA Gain Setting, –65-dBFS Input

14 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Figure 9. ADC Gain Error vs PGA Gain Setting Figure 10. MICBIAS Output Voltage vs AVDD Figure 11. MICBIAS Output Voltage vs Ambient Temperature

10 Parameter Measurement Information

All parameters are measured according to the conditions described in the Specifications section.

SLAS520E –FEBRUARY 2007–REVISED DECEMBER 2014 www.ti.com

11 Detailed Description

11.1 Overview

The TLV320AIC3101 is a highly flexible, low-power, stereo audio codec with extensive feature integration, intended for applications in smartphones, PDAs, and portable computing, communication, and entertainment applications. Available in a 5-mm × 5-mm, 32-lead QFN, the product integrates a host of features to reduce cost, board space, and power consumption in space-constrained, battery-powered, portable applications. The TLV320AIC3101 consists of the following blocks:

• Stereo audio multibit delta-sigma DAC (8 kHz–96 kHz)
• Stereo audio multibit delta-sigma ADC (8 kHz–96 kHz)
• Programmable digital audio effects processing (3-D, bass, treble, midrange, EQ, notch filter, de-emphasis)
• Four audio inputs
• Four high-power audio output drivers (headphone drive capability)
• Four high-power audio output drivers (headphone/speaker drive capability)
• Two fully differential line output drivers
• Fully programmable PLL
• Headphone/headset jack detection available as register status bit

16 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Product Folder Links: TLV320AIC3101

Audio Serial Bus Interface I2C Serial Control Bus Bias/ Reference MICBIAS SCL SDA RESET Voltage Supplies Audio ClockGeneration MCLK LINE2L PGA 0/+59.5dB 0.5dBSteps ADC + + +VCM VCM DACL VolumeControl Effects DIN DOUT BCLK WCLK DINL DINR DOUTL DOUTR MIC2R/LINE2R LINE2R ADC PGA 0/+59.5dB 0.5dBSteps DACR VolumeControl Effects AGC AGC SW-D2 SW-D1 SW-D3 SW-D4 DVDD DRVDD DRVDD DRVSS DVSS IOVDD A VSS_ADC A VDD_DAC A VSS_DAC HPROUTHPRCOMHPLCOMHPLOUT LEFT_LOP LEFT_LOM LINE1LPLINE2LP LINE1LM LINE1RM SW-L0SW-L1SW-L2 SW-L4SW-L3 SW-R4SW-R3 RIGHT_LOP RIGHT_LOM LINE1RPLINE2RP SW-R0SW-R1SW-R2 B0151-01 MIC1RP/LINE1RPMIC1RM/LINE1RM LINE1RP LINE1RM MIC1LP/LINE1LPMIC1LM/LINE1LM LINE1LP LINE1LM MIC2L/LINE2L/ MICDET TLV320AIC3101 www.ti.com SLAS520E –FEBRUARY 2007–REVISED DECEMBER 2014

11.2 Functional Block Diagram

Copyright © 2007–2014, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: TLV320AIC3101

SLAS520E –FEBRUARY 2007–REVISED DECEMBER 2014 www.ti.com

11.3 Feature Description

11.3.1 Hardware Reset

The TLV320AIC3101 requires a hardware reset after power up for proper operation. After all power supplies are at their specified values, the RESET pin must be driven low for at least 10 ns. If this reset sequence is not performed, the TLV320AIC3101 may not respond properly to register reads/writes.

11.3.2 Digital Audio Data Serial Interface

Audio data is transferred between the host processor and the TLV320AIC3101 via the digital audio data serial interface. The audio bus of the TLV320AIC3101 can be configured for left- or right-justified, I2S, DSP, or TDM modes of operation, where communication with standard telephony PCM interfaces is supported within the TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits. In addition, the word clock (WCLK) and bit clock (BCLK) can be independently configured in either master or slave mode, for flexible connectivity to a wide variety of processors. The word clock (WCLK) is used to define the beginning of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the selected ADC and DAC sampling frequencies. The bit clock (BCLK) is used to clock in and out the digital audio data across the serial bus. When in master mode, this signal can be programmed in two further modes: continuous transfer mode, and 256-clock mode. In continuous transfer mode, only the minimal number of bit clocks needed to transfer the audio data are generated, so in general the number of bit clocks per frame is two times the data width. For example, if data width is chosen as 16 bits, then 32 bit clocks are generated per frame. If the bit clock signal in master mode is to be used by a PLL in another device, it is recommended that the 16-bit or 32-bit data-width selections be used. These cases result in a low-jitter bit clock signal being generated, having frequencies of 32 fS or 64 fS. In the cases of 20-bit and 24-bt data width in master mode, the bit clocks generated in each frame are not all of equal period, due to the device not having a clean 40-fS or 48-fS clock signal readily available. The average frequency of the bit clock signal is still accurate in these cases (being 40 fS or 48 fS), but the resulting clock signal has higher jitter than in the 16-bit and 32-bit cases. In 256-clock mode, a constant 256 bit clocks per frame are generated, independent of the data width chosen. The TLV320AIC3101 further includes programmability to place the DOUT line in the high-impedance state during all bit clocks when valid data is not being sent. By combining this capability with the ability to program at what bit clock in a frame the audio data begins, time-division multiplexing (TDM) can be accomplished, resulting in multiple codecs able to use a single audio serial data bus. When the digital audio data serial interface is powered down while configured in master mode, the pins associated with the interface are put into a high-impedance state.

11.3.2.1 Right-Justified Mode

In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling edge of word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding the rising edge of the word clock.

18 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Product Folder Links: TLV320AIC3101

Figure 12. Right-Justified Serial Data Bus Mode Operation

11.3.2.2 Left-Justified Mode

the rising edge of the word clock. Figure 13. Left-Justified Serial Data Bus Mode Operation

11.3.2.3 I2S Mode

the rising edge of the word clock. Figure 14. I2S Serial Data Bus Mode Operation

11.3.2.4 DSP Mode

immediately followed by the right-channel data. Each data bit is valid on the falling edge of the bit clock. Figure 15. DSP Serial Data Bus Mode Operation

20 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

11.3.2.5 TDM Data Transfer

data on the bus except where it is expected, based on the programmed offset. Figure 16 for the two cases. Figure 16. DSP Mode and Left-Justified Mode, Showing the

11.3.3 Audio Data Converters

different sampling rates in various combinations, which are described further as follows.

D7–D4 equal to the value of bits D3–D0 in register 2, on page 0.

11.3.3.1 Audio Clock Generation

which can be obtained in a variety of manners from an external clock signal applied to the device. A more detailed diagram of the audio clock section of the TLV320AIC3101 is shown in Figure 17. Figure 17. Audio Clock Generation Processing input can also be used to generate the internal audio master clock.

22 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

www.ti.com SLAS520E –FEBRUARY 2007–REVISED DECEMBER 2014 Feature Description (continued) A primary concern is proper operation of the codec at various sample rates with the limited MCLK frequencies available in the system. This device includes a highly programmable PLL to accommodate such situations easily. The integrated PLL can generate audio clocks from a wide variety of possible MCLK inputs, with particular focus paid to the standard MCLK rates already widely used. When the PLL is disabled, fS(ref) = CLKDIV_IN/(128 × Q) Where Q = 2, 3, … , 17 CLKDIV_IN can be MCLK or BCLK, selected by register 102, bits D7–D6. as high as 50 MHz, and fS(ref) should fall within 39 kHz to 53 kHz, inclusive. When the PLL is enabled, fS(ref) = (PLLCLK_IN × K × R)/(2048 × P), where P = 1, 2, 3,… , 8 R = 1, 2, … , 16 K = J.D D = 0000, 0001, 0002, 0003, … , 9998, 9999 PLLCLK_IN can be MCLK or BCLK, selected by Page 0, register 102, bits D5–D4 P, R, J, and D are register programmable. J is the integer portion of K (the numbers to the left of the decimal point), while D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of precision). Examples: If K = 8.5, then J = 8, D = 5000 If K = 7.12, then J = 7, D = 1200 If K = 14.03, then J = 14, D = 0300 If K = 6.0004, then J = 6, D = 0004 When the PLL is enabled and D = 0000, the following conditions must be satisfied to meet specified performance:

2 MHz ≤ ( PLLCLK_IN/P ) ≤ 20 MHz

80 MHz ≤ (PLLCLK _IN × K × R/P ) ≤ 110 MHz

4 ≤ J ≤ 55 When the PLL is enabled and D≠0000, the following conditions must be satisfied to meet specified performance:

10 MHz ≤ PLLCLK _IN/P ≤ 20 MHz

80 MHz ≤ PLLCLK _IN × K × R/P ≤ 110 MHz

4 ≤ J ≤ 11 R = 1 Example: MCLK = 12 MHz and fS(ref) = 44.1 kHz Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264 Example: MCLK = 12 MHz and fS(ref) = 48 kHz Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920 Copyright © 2007–2014, Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Links: TLV320AIC3101

Table 1. Typical MCLK Rates

11.3.3.2 Stereo Audio ADC

provides sufficient antialiasing filtering without requiring additional external components.

24 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

H(z)/C0043N0 /C0041N1 /C0032z/C00421 32768 /C0042D1 /C0032z/C00421 TLV320AIC3101 www.ti.com SLAS520E –FEBRUARY 2007–REVISED DECEMBER 2014 The ADC is preceded by a programmable gain amplifier (PGA), which allows analog gain control from 0 dB to 59.5 dB in steps of 0.5 dB. The PGA gain changes are implemented with an internal soft-stepping algorithm that only changes the actual volume level by one 0.5-dB step every one or two ADC output samples, depending on the register programming (see page 0, registers 19 and 22). This soft-stepping ensures that volume control changes occur smoothly with no audible artifacts. On reset, the PGA gain defaults to a mute condition, and on power down, the PGA soft-steps the volume to mute before shutting down. A read-only flag is set whenever the gain applied by PGA equals the desired value set by the register. The soft-stepping control can also be disabled by programming a register bit. When soft stepping is enabled, the audio master clock must be applied to the part after the ADC power-down register is written to ensure the soft-stepping to mute has completed. When the ADC power-down flag is no longer set, the audio master clock can be shut down.

11.3.3.2.1 Stereo Audio ADC High-Pass Filter

Often in audio applications it is desirable to remove the dc offset from the converted audio data stream. The TLV320AIC3101 has a programmable first-order high-pass filter which can be used for this purpose. The digital filter coefficients are in 16-bit format and therefore use two 8-bit registers for each of the three coefficients, N0, N1, and D1. The transfer function of the digital high-pass filter is of the form: (1) Programming the left channel is done by writing to page 1, registers 65–70, and the right channel is programmed by writing to page 1, registers 71–76. After the coefficients have been loaded, these ADC high-pass filter coefficients can be selected by writing to page 0, register 107, bits D7–D6, and the high-pass filter can be enabled by writing to page 0, register 12, bits D7–D4.

11.3.3.2.2 Automatic Gain Control (AGC)

An automatic gain control (AGC) circuit is included with the ADC and can be used to maintain nominally constant output signal amplitude when recording speech signals (it can be fully disabled if not desired). This circuitry automatically adjusts the PGA gain as the input signal becomes overly loud or very weak, such as when a person speaking into a microphone moves closer or farther from the microphone. The AGC algorithm has several programmable settings, including target gain, attack and decay time constants, noise threshold, and maximum PGA gain applicable that allow the algorithm to be fine-tuned for any particular application. The algorithm uses the absolute average of the signal (which is the average of the absolute value of the signal) as a measure of the nominal amplitude of the output signal. Note that completely independent AGC circuitry is included with each ADC channel with entirely independent control over the algorithm from one channel to the next. This is attractive in cases where two microphones are used in a system, but may have different placement in the end equipment and require different dynamic performance for optimal system operation. The target level represents the nominal output level at which the AGC attempts to hold the ADC output signal level. The TLV320AIC3101 allows programming of eight different target levels, which can be programmed from –5.5 dB to –24 dB relative to a full-scale signal. Because the device reacts to the signal absolute average and not to peak levels, it is recommended that the target level be set with enough margin to avoid clipping at the occurrence of loud sounds. The attack time determines how quickly the AGC circuitry reduces the PGA gain when the input signal is too loud. It can be varied from 7 ms to 1,408 ms. The extended right-channel attack time can be programmed by writing to page 0, register 103, and the left channel is programmed by writing to page 0, register 105. The decay time determines how quickly the PGA gain is increased when the input signal is too low. It can be varied in the range from 0.05 s to 22.4 s. The extended right-channel decay time can be programmed by writing to page 0, register 104, and the left channel is programmed by writing to page 0, register 106. Copyright © 2007–2014, Texas Instruments Incorporated Submit Documentation Feedback 25 Product Folder Links: TLV320AIC3101

any practical AGC decay time that is needed by the system. Table 2. AGC Decay Time Restriction threshold flag is set, the status of gain applied by the AGC and the saturation flag should be ignored. programmed noise threshold. It can be programmed from 0 dB to 59.5 dB in steps of 0.5 dB.

26 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Figure 18. Typical Operation of the AGC Algorithm During Speech Recording fS(ref) in practice, then the time constants would not be correct. any practical AGC decay time that is needed by the system.

11.3.3.3 Stereo Audio DAC

fS(ref) rate of 44.1 kHz, the digital delta-sigma modulator always operates at a rate of 5.6448 MHz.

11.3.3.3.1 Digital Audio Processing for Playback

should be loaded to implement standard de-emphasis filters are given in Table 3. Table 3. De-Emphasis Coefficients for Common Audio Sampling Rates (1) The 48-kHz coefficients listed in Table 3 are used as defaults. RB2 filters refer to the first and second right-channel biquad filters, respectively. Figure 19. Structure of Digital Effects Processing for Independent Channel Processing coefficients are represented by 16-bit, 2s-complement numbers with values ranging from –32,768 to 32,767.

28 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Table 4. Default Digital Effects Processing Filter Coefficients, differentiation from other systems using the same device. Figure 20. Architecture of the Digital Audio Processing When 3-D Effects are Enabled It is recommended that the digital effects filters should be disabled while the filter coefficients are being modified. effects can be entirely avoided.

11.3.3.3.2 Digital Interpolation Filter

SLAS520E –FEBRUARY 2007–REVISED DECEMBER 2014 www.ti.com

11.3.3.3.3 Delta-Sigma Audio DAC

The stereo audio DAC incorporates a third-order multibit delta-sigma modulator followed by an analog reconstruction filter. The DAC provides high-resolution, low-noise performance, using oversampling and noise shaping techniques. The analog reconstruction filter design consists of a six-tap analog FIR filter followed by a continuous time RC filter. The analog FIR operates at a rate of 128 fS(ref) (6.144 MHz when fS(ref) = 48 kHz, 5.6448 MHz when fS(ref) = 44.1 kHz). Note that the DAC analog performance may be degraded by excessive clock jitter on the MCLK input. Therefore, care must be taken to keep jitter on this clock to a minimum.

11.3.3.3.4 Audio DAC Digital Volume Control

The audio DAC includes a digital volume control block which implements a programmable digital gain. The volume level can be varied from 0 dB to –63.5 dB in 0.5-dB steps, in addition to a mute bit, independently for each channel. The volume level of both channels can also be changed simultaneously by the master volume control. Gain changes are implemented with a soft-stepping algorithm, which only changes the actual volume by one step per input sample, either up or down, until the desired volume is reached. The rate of soft-stepping can be slowed to one step per two input samples through a register bit. Because of soft-stepping, the host does not know when the DAC has been actually muted. This may be important if the host wishes to mute the DAC before making a significant change, such as changing sample rates. In order to help with this situation, the device provides a flag back to the host via a read-only register bit that alerts the host when the part has completed the soft-stepping and the actual volume has reached the desired volume level. The soft-stepping feature can be disabled through register programming. If soft-stepping is enabled, the MCLK signal should be kept applied to the device until the DAC power-down flag is set. When this flag is set, the internal soft-stepping process and power-down sequence is complete, and the MCLK can then be stopped if desired. The TLV320AIC3101 also includes functionality to detect when the user switches on or off the de-emphasis or digital audio processing functions, to first (1) soft-mute the DAC volume control, (2) change the operation of the digital effects processing, and (3) soft-unmute the part. This avoids any possible pop/clicks in the audio output due to instantaneous changes in the filtering. A similar algorithm is used when first powering up or powering down the DAC. The circuit begins operation at power up with the volume control muted, then soft-steps it up to the desired volume level. At power down, the logic first soft-steps the volume down to a mute level, then powers down the circuitry.

11.3.3.3.5 Increasing DAC Dynamic Range

The TLV320AIC3101 allows trading off dynamic range with power consumption. The DAC dynamic range can be increased by writing to page 0, register 109, bits D7–D6. The lowest DAC current setting is the default, and the dynamic range is displayed in the datasheet table. Increasing the current can increase the DAC dynamic range by up to 1.5 dB.

11.3.3.3.6 Analog Output Common-Mode Adjustment

The output common-mode voltage and output range of the analog output are determined by an internal band-gap reference, in contrast to other codecs that may use a divided version of the supply. This scheme is used to reduce the coupling of noise that may be on the supply (such as 217-Hz noise in a GSM cellphone) into the audio signal path. However, due to the possible wide variation in analog supply range (2.7 V–3.6 V), an output common-mode voltage setting of 1.35 V, which would be used for a 2.7 V supply case, would be overly conservative if the supply is actually much larger, such as 3.3 V or 3.6 V. In order to optimize device operation, the TLV320AIC3101 includes a programmable output common-mode level, which can be set by register programming to a level most appropriate to the actual supply range used by a particular customer. The output common-mode level can be varied among four different values, ranging from 1.35 V (most appropriate for low supply ranges, near 2.7 V) to 1.8 V (most appropriate for high supply ranges, near 3.6 V). Note that there is also some limitation on the range of DVDD voltage as well in determining which setting is most appropriate.

30 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Product Folder Links: TLV320AIC3101

Table 5. Appropriate Settings

11.3.3.3.7 Audio DAC Power Control

11.3.4 Audio Analog Inputs

effectively muxed to each ADC PGA channel. By selecting to turn on multiple sets of switches per operational amplifier at a time, mixing can also be achieved. signal should not exceed 2 Vp-p (single-ended). settings used by the ADC PGA for soft-stepping. mixing of the signals LINE1R, LINE2R, LINE1L, MIC3L, and MIC3R. Figure 21. Left-Channel, Single-Ended Analog Input Mixing Configuration

11.3.5 Analog Fully Differential Line Output Drivers

Figure 23. This design includes extensive capability to adjust signal levels independently before any mixing occurs, beyond that already provided by the PGA gain and the DAC digital volume control. Figure 22. Architecture of the Output Stage Leading to the Fully Differential Line Output Drivers

32 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Figure 23. Detail of the Volume Control and Mixing Function Shown in Figure 19 and Figure 31 the fullscale output range of the device.

11.3.6 Analog High-Power Output Drivers

configuration between two driver outputs.

1. Driving up to two fully differential output signals
2. Driving up to four single-ended output signals
3. Driving two single-ended output signals, with one or two of the remaining drivers driving a fixed VCM level,
4. Driving one or two 8-Ω speakers connected BTL between pairs of driver output pins
5. Driving stereo headphones in single-ended configuration with two drivers, while the remaining two drivers are

standard volume control, but instead is included for additional fullscale output signal level control. multiple output drivers simultaneously, and if mixing of the DAC output with other analog signals is not needed. Figure 24. Architecture of the Output Stage Leading to the High-Power Output Drivers from instantaneous up to 4 s, using page 0, register 42.

34 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

www.ti.com SLAS520E –FEBRUARY 2007–REVISED DECEMBER 2014 When these output drivers are powered down, they can be placed into a variety of output conditions based on register programming. If lowest-power operation is desired, then the outputs can be placed into a high- impedance state, and all power to the output stage is removed. However, this generally results in the output nodes drifting to rest near the upper or lower analog supply, due to small leakage currents at the pins. This then results in a longer delay requirement to avoid output artifacts during driver power on. In order to reduce this required power-on delay, the TLV320AIC3101 includes an option for the output pins of the drivers to be weakly driven to the VCM level they would normally rest at when powered with no signal applied. This output VCM level is determined by an internal band-gap voltage reference, and thus results in extra power dissipation when the drivers are in power down. However, this option provides the fastest method for transitioning the drivers from power down to full-power operation without any output artifact introduced. The device includes a further option that falls between the other two— although it requires less power drawn while the output drivers are in power down, it also takes a slightly longer delay to power up without artifact than if the band-gap reference is kept alive. In this alternate mode, the powered-down output driver pin is weakly driven to a voltage of approximately half the DRVDD1/2 supply level using an internal voltage divider. This voltage does not match the actual VCM of a fully powered driver, but due to the output voltage being close to its final value, a much shorter power-up delay time setting can be used and still avoid any audible output artifacts. These output voltage options are controlled in page 0, register 42. The high-power output drivers can also be programmed to power up first with the output level (gain) control in a highly attenuated state; then the output driver automatically reduces the output attenuation slowly to reach the programmed output gain. This capability is enabled by default but can be enabled in page 0, register40.

11.3.7 Input Impedance and VCM Control

The TLV320AIC3101 includes several programmable settings to control analog input pins, particularly when they are not selected for connection to an ADC PGA. The default option allows unselected inputs to be put into a high-impedance state, such that the input impedance seen looking into the device is extremely high. Note, however, that the pins on the device do include protection diode circuits connected to AVDD and AVSS. Thus, if any voltage is driven onto a pin approximately one diode drop (~0.6 V) above AVDD or one diode drop below AVSS, these protection diodes begin conducting current, resulting in an effective impedance that no longer appears as a high-impedance state. Another programmable option for unselected analog inputs is to weakly hold them at the common-mode input voltage of the ADC PGA (which is determined by an internal band-gap voltage reference). This is useful to keep the ac-coupling capacitors connected to analog inputs biased up at a normal dc level, thus avoiding the need for them to charge up suddenly when the input is changed from being unselected to selected for connection to an ADC PGA. This option is controlled in page 0, registers 20 and 23. The user should ensure this option is disabled when an input is selected for connection to an ADC PGA or selected for the analog input bypass path, because it can corrupt the recorded input signal if left operational when an input is selected. In most cases, the analog input pins on the TLV320AIC3101 should be ac-coupled to analog input sources, the only exception to this generally being if an ADC is being used for dc voltage measurement. The ac-coupling capacitor causes a high-pass filter pole to be inserted into the analog signal path, so the size of the capacitor must be chosen to move that filter pole sufficiently low in frequency to cause minimal effect on the processed analog signal. The input impedance of the analog inputs when selected for connection to an ADC PGA varies with the setting of the input level control, starting at approximately 20 kΩ with an input level control setting of 0 dB, and increasing to approximately 80 kΩ when the input level control is set at –12 dB. For example, using a 0.1-μF ac-coupling capacitor at an analog input results in a high-pass filter pole of 80 Hz when the 0-dB input level control setting is selected.

11.3.8 MICBIAS Generation

The TLV320AIC3101 includes a programmable microphone bias output voltage (MICBIAS), capable of providing output voltages of 2 V or 2.5 V (both derived from the on-chip band-gap voltage) with 4-mA output current drive. In addition, the MICBIAS may be programmed to be switched to AVDD directly through an on-chip switch, or it can be powered down completely when not needed, for power savings. This function is controlled by register programming in page 0, register 25. Copyright © 2007–2014, Texas Instruments Incorporated Submit Documentation Feedback 35 Product Folder Links: TLV320AIC3101

11.3.9 Short-Circuit Output Protection

short-circuit protection or not, and then decide whether to program the device to power down the output drivers. clear the short-circuit flag.

11.3.10 Jack/Headset Detection

to program the output driver common-mode level at a 1.35-V or 1.5-V level. Figure 25. Configuration of Device for Jack Detection Using a Pseudo-Differential (Capless) Headphone this mode, the device cannot accurately determine if the inserted headphone is a mono or stereo headphone.

36 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

SLAS520E –FEBRUARY 2007–REVISED DECEMBER 2014 www.ti.com

11.4 Device Functional Modes

11.4.1 Bypass Path Mode

The TLV320AIC3101 is a versatile device designed for low-power applications. In some cases, only a few features of the device are required. For these applications, the unused stages of the device must be powered down to save power and an alternate route should be used. This is called a bypass path. The bypass path modes let the device to save power by turning off unused stages, like ADC, DAC and PGA.

11.4.1.1 Analog Input Bypass Path Functionality

The TLV320AIC3101 includes the additional ability to route some analog input signals past the integrated data converters, for mixing with other analog signals and then direct connection to the output drivers. This capability is useful in a cellphone, for example, when a separate FM radio device provides a stereo analog output signal that needs to be routed to headphones. The TLV320AIC3101 supports this in a low-power mode by providing a direct analog path through the device to the output drivers, while all ADCs and DACs can be completely powered down to save power. When programmed correctly, the device can pass the LINE2L and LINE2R signals directly to the output stage.

11.4.1.2 ADC PGA Signal Bypass Path Functionality

In addition to the input bypass path described previously, the TLV320AIC3101 also includes the ability to route the ADC PGA output signals past the ADC, for mixing with other analog signals and then direct connection to the output drivers. These bypass functions are described in more detail in the sections on output mixing and output driver configurations.

11.4.1.3 Passive Analog Bypass During Power Down

Programming the TLV320AIC3101 to passive analog bypass occurs by configuring the output stage switches for passthrough. This is done by opening switches SW-L0, SW-L3, SW-R0, and SW-R3 and closing either SW-L1 or SW-L2 and SW-R1 or SW-R2. See Figure 28. Programming this mode is done by writing to page 0, register 108. Connecting the MIC1LP/LINE1LP input signal to the LEFT_LOP pin is done by closing SW-L1 and opening SW- L0; this action is done by writing a 1 to page 0, register 108, bit D0. Connecting the MIC2LP/LINE2LP input signal to the LEFT_LOP pin is done by closing SW-L2 and opening SW-L0; this action is done by writing a 1 to page 0, register 108, bit D2. Connecting the MIC1LM/LINE1LM input signal to the LEFT_LOM pin is done by closing SW-L4 and opening SW-L3; this action is done by writing a 1 to page 0, register 108, bit D1. Connecting the MIC1RP/LINE1RP input signal to the RIGHT_LOP pin is done by closing SW-R1 and opening SW-R0; this action is done by writing a 1 to page 0, register 108, bit D4. Connecting the MIC2RP/LINE2RP input signal to the RIGHT_LOP pin is done by closing SW-R2 and opening SW-R0; this action is done by writing a 1 to page 0, register 108, bit D6. Connecting MIC1RM/LINE1RM input signal to the RIGHT_LOM pin is done by closing SW-R4 and opening SW-R3; this action is done by writing a 1 to page 0, register 108, bit D5. A diagram of the passive analog bypass mode configuration is shown in Figure 28. In general, connecting two switches to the same output pin should be avoided, as this error shorts two input signals together, and would likely cause distortion of the signal as the two signals are in contention. Poor frequency response would also likely occur.

38 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Product Folder Links: TLV320AIC3101

Figure 28. Passive Analog Bypass Mode Configuration

11.4.2 Digital Audio Processing for Record Path

down.) This record-only path can be seen in Figure 29.

Figure 29. Record-Only Mode With Digital Processing Path Enabled

11.5 Programming

11.5.1 I2C Control Interface

devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.

40 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Figure 30. I2C Interface Timing from a slave, the slave drives the data line; when a master sends to a slave, the master drives the data line. Under normal circumstances the master drives the clock line. HIGH to LOW. A STOP condition is when the clock line is HIGH and the data line goes from LOW to HIGH. Every byte transmitted on the I2C bus, whether it is address or data, is acknowledged with an acknowledge bit. to acknowledge this to the slave. It then sends a clock pulse to clock the bit. present at that address to pull the line LOW.

START condition is issued while the bus is active, it is called a repeated START condition. command with a slave-address byte of 00h. Figure 31. I2C Write Figure 32. I2C Read increment mode. So in the next eight clocks, the data on SDA is treated as data for the next incremental register. 8 clocks the data of the next incremental register.

11.5.2 I2C Bus Debug in a Glitched System

the detector can be disabled by writing to page 0, register 107, bit D2.

42 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

11.6 Register Maps

8-bit sequence 0x01 to register 0, the page control register, to change the active page from page 0 to page 1. control register, all further read/write operations to addresses 1 to 127 access page-0 registers again. with D7 referring to the most-significant bit of each register, and D0 referring to the least-significant bit. Table 6. Page 0/Register 0: Page Select Register the registers instead of using software reset. Table 7. Page 0/Register 1: Software Reset Register D6–D0 W 000 0000 Reserved. Do not write to these bits. Table 8. Page 0/Register 2: Codec Sample Rate Select Register 1011–1111: Reserved. Do not write these sequences.

Table 8. Page 0/Register 2: Codec Sample Rate Select Register (continued) 1011–1111 : Reserved. Do not write these sequences. Table 9. Page 0/Register 3: PLL Programming Register A

44 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Table 10. Page 0/Register 4: PLL Programming Register B 0000 00: Reserved. Do not write this sequence. Table 11. Page 0/Register 5: PLL Programming Register C(1) these registers that would result in a D value outside the valid range. LSB of the value changes, both registers should be written. Table 12. Page 0/Register 6: PLL Programming Register D these registers that would result in a D value outside the valid range. D1–D0 R 00 Reserved, write only zeros to these bits. Table 13. Page 0/Register 7: Codec Data-Path Setup Register This register setting controls timers related to the AGC time constants. 0: ADC dual-rate mode is disabled. 1: ADC dual-rate mode is enabled. Note: ADC dual-rate mode must match DAC dual-rate mode. 0: DAC dual-rate mode is disabled. 1: DAC dual-rate mode is enabled. 00: Left-DAC data path is off (muted). 01: Left-DAC data path plays left-channel input data. 10: Left-DAC data path plays right-channel input data. 11: Left-DAC data path plays mono mix of left- and right-channel input data. 00: Right-DAC data path is off (muted). 01: Right-DAC data path plays right-channel input data. 10: Right-DAC data path plays left-channel input data. 11: Right-DAC data path plays mono mix of left- and right-channel input data. D0 R/W 0 Reserved. Only write zero to this register.

Table 14. Page 0/Register 8: Audio Serial Data Interface Control Register A 0: BCLK is an input (slave mode). 1: BCLK is an output (master mode). 0: WCLK is an input (slave mode). 1: WCLK is an output (master mode). 0: Do not place DOUT in high-impedance state when valid data is not being sent. 1: Place DOUT in high-impedance state when valid data is not being sent. D3 R/W 0 Reserved. Do not write to this bit. D1–D0 R/W 00 Reserved. Only write 00 to these bits. Table 15. Page 0/Register 9: Audio Serial Data Interface Control Register B 00: Serial data bus uses I2S mode. 01: Serial data bus uses DSP mode. 10: Serial data bus uses right-justified mode. 11: Serial data bus uses left-justified mode. This register only has effect when bit clock is programmed as an output. 1: Re-sync stereo DAC with codec interface if the group delay changes by more than ±DAC (fS/4). 1: Re-sync stereo ADC with codec interface if the group delay changes by more than ±ADC (fS/4). 0: Re-sync is done without soft-muting the channel (ADC/DAC). 1: Re-sync is done by internally soft-muting the channel (ADC/DAC).

46 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Table 16. Page 0/Register 10: Audio Serial Data Interface Control Register C mode. In 256-clock mode, the maximum offset is 242 for I2S/LJF/RJF and 241 for DSP modes. Table 17. Page 0/Register 11: Audio Codec Overflow Flag Register register bit is reset to 0 after it is read. 0: No overflow has occurred. 1: An overflow has occurred. register bit is reset to 0 after it is read. 0: No overflow has occurred. 1: An overflow has occurred. register bit is reset to 0 after it is read. 0: No overflow has occurred. 1: An overflow has occurred. register bit is reset to 0 after it is read. 0: No overflow has occurred. 1: An overflow has occurred.

Table 18. Page 0/Register 12: Audio Codec Digital Filter Control Register Table 19. Page 0/Register 13: Reserved D7–D0 R/W 0000 0000 Reserved. Write only 0000 0000 to this register.

48 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Table 20. Page 0/Register 14: Headset/Button Press Detection Register B Note: Do not set bits D6 and D3 both high at the same time. D5 R 0 Reserved. Write only zero to this bit. 0: A headset has not been detected. 1: A headset has been detected. Note: Do not set bits D6 and D3 both high at the same time. 0: A stereo pseudodifferential output configuration is not being used. 1: A stereo pseudodifferential output configuration is being used. D2–D0 R 000 Reserved. Write only zeros to these bits. (1) Do not set D6 and D3 to 1 simultaneously. Table 21. Page 0/Register 15: Left-ADC PGA Gain Control Register 0: The left-ADC PGA is not muted. 1: The left-ADC PGA is muted. Table 22. Page 0/Register 16: Right-ADC PGA Gain Control Register 0: The right ADC PGA is not muted. 1: The right ADC PGA is muted.

Table 23. Page 0/Register 17: MIC2L/R to Left-ADC Control Register 1001–1110: Reserved. Do not write these sequences. 1111: MIC2L/LINE2L is not connected to the left-ADC PGA. 1001–1110: Reserved. Do not write these sequences. 1111: MIC2R/LINE2R is not connected to the left-ADC PGA. Table 24. Page 0/Register 18: MIC2/LINE2 to Right-ADC Control Register 1001–1110: Reserved. Do not write these sequences. 1111: MIC2L/LINE2L is not connected to the right-ADC PGA. 1001–1110: Reserved. Do not write these sequences. 1111: MIC2R/LINE2R is not connected to right-ADC PGA.

50 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Table 25. Page 0/Register 19: MIC1LP/LINE1LP to Left-ADC Control Register 0: MIC1LP/LINE1LP is configured in single-ended mode. 1: MIC1LP/LINE1LP and MIC1LM/LINE1LM are configured in fully differential mode. 1001–1110: Reserved. Do not write these sequences. 1111: LINE1L is not connected to the left-ADC PGA. 0: Left-ADC channel is powered down. 1: Left-ADC channel is powered up. 10–11: Left-ADC PGA soft-stepping is disabled. Table 26. Page 0/Register 20: Left Channel Analog Inputs to CM Connection Register D1–D0 00 Reserved. Write only 00. Table 27. Page 0/Register 21: MIC1RP/LINE1RP to Left-ADC Control Register 0: MIC1RP/LINE1RP is configured in single-ended mode. 1: MIC1RP/LINE1RP and MIC1RM/LINE1RM are configured in fully differential mode. 1001–1110: Reserved. Do not write these sequences. 1111: LINE1R is not connected to the left-ADC PGA. D2–D0 R 000 Reserved. Write only zeros to these bits.

Table 28. Page 0/Register 22: MIC1RP/LINE1RP to Right-ADC Control Register 0: MIC1RP/LINE1RP is configured in single-ended mode. 1: MIC1RP/LINE1RP and MIC1RM/LINE1RM are configured in fully differential mode. 1001–1110: Reserved. Do not write these sequences. 1111: LINE1R is not connected to the right-ADC PGA. 0: Right-ADC channel is powered down. 1: Right-ADC channel is powered up. 10–11: Right-ADC PGA soft-stepping is disabled. Table 29. Page 0/Register 23: Right Channel Analog Inputs to CM Connection Register D1–D0 00 Reserved. Write only 00. Table 30. Page 0/Register 24: MIC1LP/LINE1LP to Right-ADC Control Register 0: MIC1LP/LINE1LP is configured in single-ended mode. 1: MIC1LP/LINE1LP and MIC1LM/LINE1LM are configured in fully differential mode. 1001–1110: Reserved. Do not write these sequences. 1111: LINE1L is not connected to the right-ADC PGA. D2–D0 R 000 Reserved. Write only zeros to these register bits.

52 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Table 31. Page 0/Register 25: MICBIAS Control Register 00: MICBIAS output is powered down. 01: MICBIAS output is powered to 2 V. 10: MICBIAS output is powered to 2.5 V. D5–D3 R 000 Reserved. Write only zeros to these bits. D2–D0 R XXX Reserved. Write only zeros to these bits. Table 32. Page 0/Register 26: Left-AGC Control Register A These time constants(1) are not accurate when double-rate audio mode is enabled. These time constants(1) are not accurate when double-rate audio mode is enabled. (1) Time constants are valid when DRA is not enabled. The values would change if DRA is enabled. Table 33. Page 0/Register 27: Left-AGC Control Register B D0 R/W 0 Reserved. Write only zero to this register bit. Table 34. Page 0/Register 28: Left-AGC Control Register C

Table 34. Page 0/Register 28: Left-AGC Control Register C (continued) 0: Left-AGC clip stepping is disabled. 1: Left-AGC clip stepping is enabled. Table 35. Page 0/Register 29: Right-AGC Control Register A These time constants are not accurate when double-rate audio mode is enabled. These time constants are not accurate when double-rate audio mode is enabled. Table 36. Page 0/Register 30: Right-AGC Control Register B D0 R/W 0 Reserved. Write only zero to this register bit.

54 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Table 37. Page 0/Register 31: Right-AGC Control Register C 0: Right-AGC clip stepping is disabled. 1: Right-AGC clip stepping is enabled. Table 38. Page 0/Register 32: Left-AGC Gain Register Table 39. Page 0/Register 33: Right-AGC Gain Register

Table 40. Page 0/Register 34: Left-AGC Noise Gate Debounce Register These times(1) are not accurate when double-rate audio mode is enabled. These times(1) are not accurate when double-rate audio mode is enabled. (1) Time constants are valid when DRA is not enabled. The values change when DRA is enabled. Table 41. Page 0/Register 35: Right-AGC Noise Gate Debounce Register These times(1) are not accurate when double-rate audio mode is enabled. These times(1) are not accurate when double-rate audio mode is enabled. (1) Time constants are valid when DRA is not enabled. The values would change when DRA is enabled.

56 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Table 42. Page 0/Register 36: ADC Flag Register 0: Applied gain and programmed gain are not the same. 0: Left ADC is in a power-down state. 1: Left ADC is in a power-up state. 0: Signal power is greater than or equal to noise threshold. 1: Signal power is less than noise threshold. 0: Left AGC is not saturated. 0: Applied gain and programmed gain are not the same. 0: Right ADC is in a power-down state. 1: Right ADC is in a power-up state. 0: Signal power is greater than or equal to noise threshold. 1: Signal power is less than noise threshold. 0: Right AGC is not saturated. Table 43. Page 0/Register 37: DAC Power and Output Driver Control Register 0: Left DAC is not powered up. 0: Right DAC is not powered up. 00: HPLCOM is configured as differential of HPLOUT. 01: HPLCOM is configured as constant VCM output. 10: HPLCOM is configured as independent single-ended output. 11: Reserved. Do not write this sequence. D3–D0 R 000 Reserved. Write only zeros to these bits. Table 44. Page 0/Register 38: High-Power Output Driver Control Register D7–D6 R 00 Reserved. Write only zeros to these bits. 000: HPRCOM is configured as differential of HPROUT. 001: HPRCOM is configured as constant VCM output. 010: HPRCOM is configured as independent single-ended output. 011: HPRCOM is configured as differential of HPLCOM. 100: HPRCOM is configured as external feedback with HPLCOM as constant VCM output. 101–111: Reserved. Do not write these sequences. 0: Short-circuit protection on all high-power output drivers is disabled. 1: Short-circuit protection on all high-power output drivers is enabled.

Table 44. Page 0/Register 38: High-Power Output Driver Control Register (continued) 0: If short-circuit protection is enabled, it limits the maximum current to the load. D0 R 0 Reserved. Write only zero to this bit. Table 45. Page 0/Register 39: Reserved Register D7–D0 R 0000 0000 Reserved. Do not write to this register. Table 46. Page 0/Register 40: High-Power Output Stage Control Register D5–D2 R/W 0000 Reserved. Write only zeros to these bits. 10: Output soft-stepping is disabled. 11: Reserved. Do not write this sequence. Table 47. Page 0/Register 41: DAC Output Switching Control Register 00: Left-DAC output selects DAC_L1 path. 01: Left-DAC output selects DAC_L3 path to left line output driver. 10: Left-DAC output selects DAC_L2 path to left high-power output drivers. 11: Reserved. Do not write this sequence. 00: Right-DAC output selects DAC_R1 path. 01: Right-DAC output selects DAC_R3 path to right line output driver. 10: Right-DAC output selects DAC_R2 path to right high-power output drivers. 11: Reserved. Do not write this sequence. D3–D2 R/W 00 Reserved. Write only zeros to these bits. 00: Left- and right-DAC channels have independent volume controls. 01: Left-DAC volume follows the right-DAC digital volume control register. 10: Right-DAC volume follows the left-DAC digital volume control register. 11: Left- and right-DAC channels have independent volume controls (same as 00).

58 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Table 48. Page 0/Register 42: Output Driver Pop Reduction Register 1100–1111: Reserved. Do not write these sequences. 0: Weakly driven output common-mode voltage is generated from resistor divider off the AVDD supply. 1: Weakly driven output common-mode voltage is generated from band-gap reference. D0 R/W 0 Reserved. Write only zero to this bit. Table 49. Page 0/Register 43: Left-DAC Digital Volume Control Register 0: The left-DAC channel is not muted. 1: The left-DAC channel is muted. Table 50. Page 0/Register 44: Right-DAC Digital Volume Control Register 0: The right-DAC channel is not muted. 1: The right-DAC channel is muted.

11.7 Output Stage Volume Controls

0.5-dB step programmability over most of the gain range, with steps increasing slightly at the lowest attenuations. Table 51 lists the detailed gain versus programmed setting for this basic volume control. Table 51. Output Stage Volume Control Settings and Gains Table 52. Page 0/Register 45: Reserved Register D7–D0 R/W 0000 0000 Reserved. Do not write to this register.

60 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Table 53. Page 0/Register 46: PGA_L to HPLOUT Volume Control Register 0: PGA_L is not routed to HPLOUT. 1: PGA_L is routed to HPLOUT. For 7-bit register setting versus analog gain values, see Table 51. Table 54. Page 0/Register 47: DAC_L1 to HPLOUT Volume Control Register 0: DAC_L1 is not routed to HPLOUT. 1: DAC_L1 is routed to HPLOUT. For 7-bit register setting versus analog gain values, see Table 51. Table 55. Page 0/Register 48: Reserved Register D7–D0 R/W 0000 0000 Reserved. Do not write to this register. Table 56. Page 0/Register 49: PGA_R to HPLOUT Volume Control Register 0: PGA_R is not routed to HPLOUT. 1: PGA_R is routed to HPLOUT. For 7-bit register setting versus analog gain values, see Table 51. Table 57. Page 0/Register 50: DAC_R1 to HPLOUT Volume Control Register 0: DAC_R1 is not routed to HPLOUT. 1: DAC_R1 is routed to HPLOUT. For 7-bit register setting versus analog gain values, see Table 51. Table 58. Page 0/Register 51: HPLOUT Output Level Control Register 1010–1111: Reserved. Do not write these sequences.

Table 58. Page 0/Register 51: HPLOUT Output Level Control Register (continued) 0: HPLOUT is weakly driven to a common-mode when powered down. 1: HPLOUT is high-impedance when powered down. 0: All programmed gains to HPLOUT have been applied. 1: Not all programmed gains to HPLOUT have been applied yet. 0: HPLOUT is not fully powered up. 1: HPLOUT is fully powered up. Table 59. Page 0/Register 52: Reserved Register D7–D0 R/W 0000 0000 Reserved. Do not write to this register. Table 60. Page 0/Register 53: PGA_L to HPLCOM Volume Control Register 0: PGA_L is not routed to HPLCOM. 1: PGA_L is routed to HPLCOM. For 7-bit register setting versus analog gain values, see Table 51. Table 61. Page 0/Register 54: DAC_L1 to HPLCOM Volume Control Register 0: DAC_L1 is not routed to HPLCOM. 1: DAC_L1 is routed to HPLCOM. For 7-bit register setting versus analog gain values, see Table 51. Table 62. Page 0/Register 55: Reserved Register D7–D0 R/W 0000 0000 Reserved. Do not write to this register. Table 63. Page 0/Register 56: PGA_R to HPLCOM Volume Control Register 0: PGA_R is not routed to HPLCOM. 1: PGA_R is routed to HPLCOM. For 7-bit register setting versus analog gain values, see Table 51. Table 64. Page 0/Register 57: DAC_R1 to HPLCOM Volume Control Register 0: DAC_R1 is not routed to HPLCOM. 1: DAC_R1 is routed to HPLCOM.

62 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Table 64. Page 0/Register 57: DAC_R1 to HPLCOM Volume Control Register (continued) For 7-bit register setting versus analog gain values, see Table 51. Table 65. Page 0/Register 58: HPLCOM Output Level Control Register 1010–1111: Reserved. Do not write these sequences. 0: HPLCOM is weakly driven to a common mode when powered down. 1: HPLCOM is high-impedance when powered down. 0: All programmed gains to HPLCOM have been applied. 1: Not all programmed gains to HPLCOM have been applied yet. 0: HPLCOM is not fully powered up. 1: HPLCOM is fully powered up. Table 66. Page 0/Register 59: Reserved Register D7–D0 R/W 0000 0000 Reserved. Do not write to this register. Table 67. Page 0/Register 60: PGA_L to HPROUT Volume Control Register 0: PGA_L is not routed to HPROUT. For 7-bit register setting versus analog gain values, see Table 51. Table 68. Page 0/Register 61: DAC_L1 to HPROUT Volume Control Register 0: DAC_L1 is not routed to HPROUT. 1: DAC_L1 is routed to HPROUT. For 7-bit register setting versus analog gain values, see Table 51. Table 69. Page 0/Register 62: Reserved Register D7–D0 R/W 0000 0000 Reserved. Do not write to this register.

Table 70. Page 0/Register 63: PGA_R to HPROUT Volume Control Register 0: PGA_R is not routed to HPROUT. 1: PGA_R is routed to HPROUT. For 7-bit register setting versus analog gain values, see Table 51. Table 71. Page 0/Register 64: DAC_R1 to HPROUT Volume Control Register 0: DAC_R1 is not routed to HPROUT. 1: DAC_R1 is routed to HPROUT. For 7-bit register setting versus analog gain values, see Table 51. Table 72. Page 0/Register 65: HPROUT Output Level Control Register 1010–1111: Reserved. Do not write these sequences. 0: HPROUT is weakly driven to a common mode when powered down. 1: HPROUT is high-impedance when powered down. 0: All programmed gains to HPROUT have been applied. 1: Not all programmed gains to HPROUT have been applied yet. 0: HPROUT is not fully powered up. 1: HPROUT is fully powered up. Table 73. Page 0/Register 66: Reserved Register D7–D0 R/W 0000 0000 Reserved. Do not write to this register. Table 74. Page 0/Register 67: PGA_L to HPRCOM Volume Control Register 0: PGA_L is not routed to HPRCOM. 1: PGA_L is routed to HPRCOM. For 7-bit register setting versus analog gain values, see Table 51.

64 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Table 75. Page 0/Register 68: DAC_L1 to HPRCOM Volume Control Register 0: DAC_L1 is not routed to HPRCOM. 1: DAC_L1 is routed to HPRCOM. For 7-bit register setting versus analog gain values, see Table 51. Table 76. Page 0/Register 69: Reserved Register D7–D0 R/W 0000 0000 Reserved. Do not write to this register. Table 77. Page 0/Register 70: PGA_R to HPRCOM Volume Control Register 0: PGA_R is not routed to HPRCOM. 1: PGA_R is routed to HPRCOM. For 7-bit register setting versus analog gain values, see Table 51. Table 78. Page 0/Register 71: DAC_R1 to HPRCOM Volume Control Register 0: DAC_R1 is not routed to HPRCOM. 1: DAC_R1 is routed to HPRCOM. For 7-bit register setting versus analog gain values, see Table 51. Table 79. Page 0/Register 72: HPRCOM Output Level Control Register 1010–1111: Reserved. Do not write these sequences. 0: HPRCOM is weakly driven to a common mode when powered down. 1: HPRCOM is high-impedance when powered down. 0: All programmed gains to HPRCOM have been applied. 1: Not all programmed gains to HPRCOM have been applied yet. 0: HPRCOM is not fully powered up. 1: HPRCOM is fully powered up.

Table 80. Page 0/Registers 73–78: Reserved D7–D0 R 0000 0000 Reserved. Do not write to these registers. Table 81. Page 0/Register 79: Reserved D7–D0 R 0000 0010 Reserved. Do not write to this register. Table 82. Page 0/Register 80: Reserved D7–D0 R 0000 0000 Reserved. Do not write to this register. Table 83. Page 0/Register 81: PGA_L to LEFT_LOP/M Volume Control Register 0: PGA_L is not routed to LEFT_LOP/M. 1: PGA_L is routed to LEFT_LOP/M. For 7-bit register setting versus analog gain values, see Table 51. Table 84. Page 0/Register 82: DAC_L1 to LEFT_LOP/M Volume Control Register 0: DAC_L1 is not routed to LEFT_LOP/M. 1: DAC_L1 is routed to LEFT_LOP/M. For 7-bit register setting versus analog gain values, see Table 51. Table 85. Page 0/Register 83: Reserved Register D7–D0 R/W 0000 0000 Reserved. Do not write to this register. Table 86. Page 0/Register 84: PGA_R to LEFT_LOP/M Volume Control Register 0: PGA_R is not routed to LEFT_LOP/M. 1: PGA_R is routed to LEFT_LOP/M. For 7-bit register setting versus analog gain values, see Table 51. Table 87. Page 0/Register 85: DAC_R1 to LEFT_LOP/M Volume Control Register 0: DAC_R1 is not routed to LEFT_LOP/M. 1: DAC_R1 is routed to LEFT_LOP/M. For 7-bit register setting versus analog gain values, see Table 51.

66 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Table 88. Page 0/Register 86: LEFT_LOP/M Output Level Control Register 1010–1111: Reserved. Do not write these sequences. D2 R 0 Reserved. Do not write to this register bit. 0: All programmed gains to LEFT_LOP/M have been applied. 1: Not all programmed gains to LEFT_LOP/M have been applied yet. 0: LEFT_LOP/M is not fully powered up. 1: LEFT_LOP/M is fully powered up. Table 89. Page 0/Register 87: Reserved Register D7–D0 R/W 0000 0000 Reserved. Do not write to this register. Table 90. Page 0/Register 88: PGA_L to RIGHT_LOP/M Volume Control Register 0: PGA_L is not routed to RIGHT_LOP/M. 1: PGA_L is routed to RIGHT_LOP/M. For 7-bit register setting versus analog gain values, see Table 51. Table 91. Page 0/Register 89: DAC_L1 to RIGHT_LOP/M Volume Control Register 0: DAC_L1 is not routed to RIGHT_LOP/M. 1: DAC_L1 is routed to RIGHT_LOP/M. For 7-bit register setting versus analog gain values, see Table 51. Table 92. Page 0/Register 90: Reserved Register D7–D0 R/W 0000 0000 Reserved. Do not write to this register. Table 93. Page 0/Register 91: PGA_R to RIGHT_LOP/M Volume Control Register 0: PGA_R is not routed to RIGHT_LOP/M. 1: PGA_R is routed to RIGHT_LOP/M. For 7-bit register setting versus analog gain values, see Table 51.

Table 94. Page 0/Register 92: DAC_R1 to RIGHT_LOP/M Volume Control Register 0: DAC_R1 is not routed to RIGHT_LOP/M. 1: DAC_R1 is routed to RIGHT_LOP/M. For 7-bit register setting versus analog gain values, see Table 51. Table 95. Page 0/Register 93: RIGHT_LOP/M Output Level Control Register 1010–1111: Reserved. Do not write these sequences. D2 R 0 Reserved. Do not write to this register bit. 0: All programmed gains to RIGHT_LOP/M have been applied. 1: Not all programmed gains to RIGHT_LOP/M have been applied yet. 0: RIGHT_LOP/M is not fully powered up. 1: RIGHT_LOP/M is fully powered up. Table 96. Page 0/Register 94: Module Power Status Register 0: Left DAC is not fully powered up. 1: Left DAC is fully powered up. 0: Right DAC is not fully powered up. 1: Right DAC is fully powered up. D5 R 0 Reserved. Write only 0 to this bit. 0: LEFT_LOP/M output driver is powered down. 1: LEFT_LOP/M output driver is powered up. 0: RIGHT_LOP/M is not fully powered up. 1: RIGHT_LOP/M is fully powered up. 0: HPLOUT Driver is not fully powered up. 1: HPLOUT Driver is fully powered up. 0: HPROUT Driver is not fully powered up. 1: HPROUT Driver is fully powered up. D0 R 0 Reserved. Do not write to this bit.

68 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Table 97. Page 0/Register 95: Output Driver Short-Circuit Detection Status Register 0: HPLCOM is not fully powered up. 1: HPLCOM is fully powered up. 0: HPRCOM is not fully powered up. 1: HPRCOM is fully powered up. D1–D0 R 00 Reserved. Do not write to these bits. Table 98. Page 0/Register 96: Sticky Interrupt Flags Register D3 R 0 Reserved. Do not write to this bit. 0: No headset insertion/removal is detected. 1: Headset insertion/removal is detected. 0: Left ADC signal power is greater than or equal to noise threshold for left AGC. 1: Left ADC signal power is less than noise threshold for left AGC. 0: Right ADC signal power is greater than or equal to noise threshold for right AGC. 1: Right ADC signal power is less than noise threshold for right AGC. Table 99. Page 0/Register 97: Real-Time Interrupt Flags Register

Table 99. Page 0/Register 97: Real-Time Interrupt Flags Register (continued) D3 R 0 Reserved. Do not write to this bit. 0: No headset insertion/removal is detected. 1: Headset insertion/removal is detected. 0: Left ADC signal power is greater than noise threshold for left AGC. 1: Left ADC signal power lower than noise threshold for left AGC. 0: Right ADC signal power is greater than noise threshold for right AGC. 1: Right ADC signal power is lower than noise threshold for right AGC. Table 100. Page 0/Register 98–100: Reserved Registers D7–D0 R 0000 0000 Reserved. Do not write to these registers. Table 101. Page 0/Register 101: Clock Register D7–D1 R 0000 000 Reserved. Write only zeros to these bits. Table 102. Page 0/Register 102: Clock Generation Control Register D3–D0 R/W 0010 Reserved. Write only 0010 to these bits.

70 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Table 103. Page 0/Register 103: Left-AGC New Programmable Attack Time Register 0: Attack time for the left AGC is generated from page 0, register 26. 1: Attack time for the left AGC is generated from this register. D1–D0 R/W 00 Reserved. Write only zeros to these bits. Table 104. Page 0/Register 104: Left-AGC New Programmable Decay Time Register(1) 0: Decay time for the left AGC is generated from page 0, register 26. 1: Decay time for the left AGC is generated from this register. D1–D0 R/W 00 Reserved. Write only zeros to these bits.

Table 105. Page 0/Register 105: Right-AGC New Programmable Attack Time Register 0: Attack time for the right AGC is generated from page 0, register 29. 1: Attack time for the right AGC is generated from this register. D1–D0 R/W 00 Reserved. Write only zeros to these register bits. Table 106. Page 0/Register 106: Right-AGC New Programmable Decay Time Register(1) 0: Decay time for the right AGC is generated from page 0, register 29. 1: Decay time for the right AGC is generated from this register. D1–D0 R/W 00 Reserved. Write only zeros to these bits.

72 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Table 107. Page 0/Register 107: New Programmable ADC Digital Path and I2C Bus Condition Register 0: Default coefficients are used when ADC high pass is enabled. 1: Programmable coefficients are used when ADC high pass is enabled. 0: Default coefficients are used when ADC high pass is enabled. 1: Programmable coefficients are used when ADC high pass is enabled. 0: No additional programmable filters other than the HPF are used for the ADC. 1: The programmable filter is connected to ADC output, if both DACs are powered down. 0: Internal logic is enabled to detect an I2C bus error, and clears the bus error condition. 1: Internal logic is disabled to detect an I2C bus hang. D1 R 0 Reserved. Write only zero to this bit. 0: I2C bus hang is not detected. 1: I2C bus hang is detected. This bit is cleared by reading this register. Table 108. Page 0/Register 108: Passive Analog Signal Bypass Selection During Power Down Register(1) D7 R/W 0 Reserved. Write only zero to this bit. 1: Signal is routed by a switch to RIGHT_LOP. 1: Signal is routed by a switch to RIGHT_LOM. 1: Signal is routed by a switch to RIGHT_LOP. D3 R/W 0 Reserved. Write only zero to this bit. 1: Signal is routed by a switch to LEFT_LOP. 1: Signal is routed by a switch to LEFT_LOM. 1: Signal is routed by a switch to LEFT_LOP. occur on the circuitry that feeds these two input pins of this device. Table 109. Page 0/Register 109: DAC Quiescent Current Adjustment Register D5–D0 R/W 00 0000 Reserved. Write only zeros to these bits.

Table 110. Page 0/Register 110–127: Reserved Registers D7–D0 R 0000 0000 Reserved. Do not write to these registers. Table 111. Page 1/Register 0: Page Select Register D7–D1 X 0000 000 Reserved. Write only zeros to these bits . read/writes. This register has the same functionality on page 0 and page 1. Table 112. Page 1/Register 1: Left-Channel Audio Effects Filter N0 Coefficient MSB Register(1) complement integer, with possible values ranging from –32,768 to 32,767. register. Even if only the MSB or LSB of the coefficient changes, both registers should be written in this sequence. Table 113. Page 1/Register 2: Left-Channel Audio Effects Filter N0 Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 114. Page 1/Register 3: Left-Channel Audio Effects Filter N1 Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 115. Page 1/Register 4: Left-Channel Audio Effects Filter N1 Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 116. Page 1/Register 5: Left-Channel Audio Effects Filter N2 Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767.

74 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Table 117. Page 1/Register 6: Left-Channel Audio Effects Filter N2 Coefficient LSB complement integer, with possible values ranging from –32,768 to 32,767. Table 118. Page 1/Register 7: Left-Channel Audio Effects Filter N3 Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 119. Page 1/Register 8: Left-Channel Audio Effects Filter N3 Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 120. Page 1/Register 9: Left-Channel Audio Effects Filter N4 Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 121. Page 1/Register 10: Left-Channel Audio Effects Filter N4 Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 122. Page 1/Register 11: Left-Channel Audio Effects Filter N5 Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 123. Page 1/Register 12: Left-Channel Audio Effects Filter N5 Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 124. Page 1/Register 13: Left-Channel Audio Effects Filter D1 Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767.

Table 125. Page 1/Register 14: Left-Channel Audio Effects Filter D1 Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 126. Page 1/Register 15: Left-Channel Audio Effects Filter D2 Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 127. Page 1/Register 16: Left-Channel Audio Effects Filter D2 Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 128. Page 1/Register 17: Left-Channel Audio Effects Filter D4 Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 129. Page 1/Register 18: Left-Channel Audio Effects Filter D4 Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 130. Page 1/Register 19: Left-Channel Audio Effects Filter D5 Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 131. Page 1/Register 20: Left-Channel Audio Effects Filter D5 Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 132. Page 1/Register 21: Left-Channel De-Emphasis Filter N0 Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767.

76 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Table 133. Page 1/Register 22: Left-Channel De-Emphasis Filter N0 Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 134. Page 1/Register 23: Left-Channel De-Emphasis Filter N1 Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 135. Page 1/Register 24: Left-Channel De-Emphasis Filter N1 Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 136. Page 1/Register 25: Left-Channel De-Emphasis Filter D1 Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 137. Page 1/Register 26: Left-Channel De-Emphasis Filter D1 Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 138. Page 1/Register 27: Right-Channel Audio Effects Filter N0 Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 139. Page 1/Register 28: Right-Channel Audio Effects Filter N0 Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 140. Page 1/Register 29: Right-Channel Audio Effects Filter N1 Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767.

Table 141. Page 1/Register 30: Right-Channel Audio Effects Filter N1 Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 142. Page 1/Register 31: Right-Channel Audio Effects Filter N2 Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 143. Page 1/Register 32: Right-Channel Audio Effects Filter N2 Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 144. Page 1/Register 33: Right-Channel Audio Effects Filter N3 Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 145. Page 1/Register 34: Right-Channel Audio Effects Filter N3 Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 146. Page 1/Register 35: Right-Channel Audio Effects Filter N4 Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 147. Page 1/Register 36: Right-Channel Audio Effects Filter N4 Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 148. Page 1/Register 37: Right-Channel Audio Effects Filter N5 Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767.

78 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Table 149. Page 1/Register 38: Right-Channel Audio Effects Filter N5 Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 150. Page 1/Register 39: Right-Channel Audio Effects Filter D1 Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 151. Page 1/Register 40: Right-Channel Audio Effects Filter D1 Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 152. Page 1/Register 41: Right-Channel Audio Effects Filter D2 Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 153. Page 1/Register 42: Right-Channel Audio Effects Filter D2 Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 154. Page 1/Register 43: Right-Channel Audio Effects Filter D4 Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 155. Page 1/Register 44: Right-Channel Audio Effects Filter D4 Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 156. Page 1/Register 45: Right-Channel Audio Effects Filter D5 Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767.

Table 157. Page 1/Register 46: Right-Channel Audio Effects Filter D5 Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 158. Page 1/Register 47: Right-Channel De-Emphasis Filter N0 Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 159. Page 1/Register 48: Right-Channel De-Emphasis Filter N0 Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 160. Page 1/Register 49: Right-Channel De-Emphasis Filter N1 Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 161. Page 1/Register 50: Right-Channel De-Emphasis Filter N1 Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 162. Page 1/Register 51: Right-Channel De-Emphasis Filter D1 Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 163. Page 1/Register 52: Right-Channel De-Emphasis Filter D1 Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 164. Page 1/Register 53: 3-D Attenuation Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767.

80 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Table 165. Page 1/Register 54: 3-D Attenuation Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 166. Page 1/Register 55–64: Reserved Registers D7–D0 R 0000 0000 Reserved. Do not write to these registers. Table 167. Page 1/Register 65: Left-Channel ADC High-Pass Filter N0 Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 168. Page 1/Register 66: Left-Channel ADC High-Pass Filter N0 Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 169. Page 1/Register 67: Left-Channel ADC High-Pass Filter N1 Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 170. Page 1/Register 68: Left-Channel ADC High-Pass Filter N1 Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 171. Page 1/Register 69: Left-Channel ADC High-Pass Filter D1 Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 172. Page 1/Register 70: Left-Channel ADC High-Pass Filter D1 Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767.

Table 173. Page 1/Register 71: Right-Channel ADC High-Pass Filter N0 Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 174. Page 1/Register 72: Right-Channel ADC High-Pass Filter N0 Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 175. Page 1/Register 73: Right-Channel ADC High-Pass Filter N1 Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 176. Page 1/Register 74: Right-Channel ADC High-Pass Filter N1 Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 177. Page 1/Register 75: Right-Channel ADC High-Pass Filter D1 Coefficient MSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 178. Page 1/Register 76: Right-Channel ADC High-Pass Filter D1 Coefficient LSB Register complement integer, with possible values ranging from –32,768 to 32,767. Table 179. Page 1/Registers 77–127: Reserved Registers D7–D0 R 0000 0000 Reserved. Do not write to these registers.

82 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

www.ti.com SLAS520E –FEBRUARY 2007–REVISED DECEMBER 2014 NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

12.1 Application Information

The TLV320AIC3101 is a highly integrated low-power stereo audio codec with integrated stereo speaker/headphone/ line amplifier, as well as multiple inputs and outputs that are programmable in single-ended or fully differential configurations. Pairs of high power drivers can be used to drive 8-Ω speakers in BTL configuration. All the features of the TLV320AIC3101 are accessed by programmable registers. External processor with I2C protocol is required to control the device. It is good practice to perform a hardware reset after initial power up to ensure that all registers are in their default states. Extensive register-based power control is included, enabling stereo 48-kHz DAC playback as low as 14-mW from a 3.3-V analog supply, making it ideal for portable battery-powered audio and telephony applications. Copyright © 2007–2014, Texas Instruments Incorporated Submit Documentation Feedback 83 Product Folder Links: TLV320AIC3101

0.1 F/c109

0.47 F/c109

1 F/c109

220 F/c109

1 F/c109 1 F

12.2 Typical Application

12.2.1 AC-Coupled Headphone Output With Separate Line Outputs and External Speaker Amplifier

differential stereo line output. Figure 33. Typical Connections for AC-Coupled Headphone Output With Separate Line Outputs and

84 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

12.2.1.1 Design Requirements

For this design example, use the parameters shown in Table 180. Table 180. Design Parameters

12.2.1.2 Detailed Design Procedure

Using the Typical Application Schematic as a guide, integrate the hardware into the system. section, integrate the device and its supporting components into the system PCB file.

• For questions and support go to the E2E forums (e2e.ti.com). If it is necessary to deviate from the recommended layout, visit the E2E forum to request a layout review. Determining sample rate and Master clock frequency is required since powering up the device as all internal timing is derived from the master clock. Refer to the Figure 17 in order to get more information of how to configure correctly the required clocks for the device. As the TLV320AIC3101 is designed for low-power applications, when powered up, the device has several features powered down. A correct routing of the TLV320AIC3101 signals is achieved by a correct setting of the device registers, powering up the required stages of the device and configuring the internal switches to follow a desired route. For more information of the device configuration and programming, refer to the TLV320AIC3101 technical documents section in ti.com (http://www.ti.com/product/TLV320AIC3101/technicaldocuments). Copyright © 2007–2014, Texas Instruments Incorporated Submit Documentation Feedback 85 Product Folder Links: TLV320AIC3101

12.2.1.3 Application Curves

Figure 35. THD vs Headphone Power, CaplessFigure 34. THD vs Headphone Power, AC-Coupled Figure 36. THD vs Speaker Power, 8 Ω Load

86 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

100 F/c109

12.2.2 Connections With Headphone and External Speaker Driver in Cell Phone Application

Figure 37. Typical Connections With Headphone and External Speaker Driver in Cell Phone Application

12.2.2.1 Design Requirements

See Analog Fully Differential Line Output Drivers section for the design requirements.

12.2.2.2 Detailed Design Procedure

See Analog Fully Differential Line Output Drivers section for the design requirements.

12.2.2.3 Application Curves

See Analog Fully Differential Line Output Drivers section for the application curves.

13 Power Supply Recommendations

sequence provides the most robust operation. up second. The digital supply DVDD should be powered up last. Keep RESET low until all supplies are stable. The analog supplies should be greater than or equal to DVDD at all times. Figure 38. TLV320AIC3101 Power Supply Sequencing Table 181. TLV320AIC3101 Power Supply Sequencing

88 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

14 Layout

14.1 Layout Guidelines

PCB design is made considering the application, and the review is specific for each system requirements. However, general considerations can optimize the system performance.

• The TLV320AIC3101 thermal pad should be connected to analog output driver ground using multiple VIAS to minimize impedance between the device and ground.
• Analog and digital grounds should be separated to prevent possible digital noise from affecting the analog performance of the board.
• The TLV320AIC3101 requires the decoupling capacitors to be placed as close as possible to the device power supply terminals.
• If possible, route the differential audio signals differentially on the PCB. This is recommended to get better noise immunity.

14.2 Layout Example

Figure 39. Layout Schematic

SLAS520E –FEBRUARY 2007–REVISED DECEMBER 2014 www.ti.com

15 Device and Documentation Support

15.1 Trademarks

All trademarks are the property of their respective owners.

15.2 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

15.3 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

16 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

90 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated

Product Folder Links: TLV320AIC3101

www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) 6PAIC3101IRHBRG4 Active Production VQFN (RHB) | 32 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 AC3101I 6PAIC3101IRHBRG4.A Active Production VQFN (RHB) | 32 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 AC3101I TLV320AIC3101IRHBR Active Production VQFN (RHB) | 32 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 AC3101I TLV320AIC3101IRHBR.A Active Production VQFN (RHB) | 32 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 AC3101I TLV320AIC3101IRHBT Active Production VQFN (RHB) | 32 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 AC3101I TLV320AIC3101IRHBT.A Active Production VQFN (RHB) | 32 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 AC3101I (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 7-Oct-2025 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 6PAIC3101IRHBRG4 VQFN RHB 32 2500 346.0 346.0 33.0 TLV320AIC3101IRHBR VQFN RHB 32 2500 346.0 346.0 33.0 TLV320AIC3101IRHBT VQFN RHB 32 250 210.0 185.0 35.0 Pack Materials-Page 2

www.ti.com GENERIC PACKAGE VIEW Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. VQFN - 1 mm max heightRHB 32 PLASTIC QUAD FLATPACK - NO LEAD5 x 5, 0.5 mm pitch 4224745/A

www.ti.com PACKAGE OUTLINE C 32X 0.3 0.2 3.45 0.1 32X 0.5 0.3

1 MAX

(0.2) TYP 0.05 0.00 28X 0.5 3.5 2X 3.5 A 5.1 4.9 B 5.1 4.9 (0.1) VQFN - 1 mm max heightRHB0032E PLASTIC QUAD FLATPACK - NO LEAD 4223442/B 08/2019 PIN 1 INDEX AREA 0.08 C SEATING PLANE 8 17 9 16 32 25 (OPTIONAL) PIN 1 ID

0.1 C A B

0.05 C EXPOSED THERMAL PAD

33 SYMM

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 3.000 SEE SIDE WALL DETAIL 20.000 SIDE WALL DETAIL OPTIONAL METAL THICKNESS

www.ti.com EXAMPLE BOARD LAYOUT (1.475)

0.07 MIN

0.07 MAX

32X (0.25) 32X (0.6) ( 0.2) TYP VIA 28X (0.5) (4.8) (4.8) (1.475) ( 3.45) (R0.05) TYP VQFN - 1 mm max heightRHB0032E PLASTIC QUAD FLATPACK - NO LEAD 4223442/B 08/2019 SYMM 9 16 2532 SYMM LAND PATTERN EXAMPLE SCALE:18X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METAL SOLDER MASK OPENINGSOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN 32X (0.6) 32X (0.25) 28X (0.5) (4.8) (4.8) 4X ( 1.49) (0.845) (0.845)(R0.05) TYP VQFN - 1 mm max heightRHB0032E PLASTIC QUAD FLATPACK - NO LEAD 4223442/B 08/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 33: 75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X SYMM 9 16 2532

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2025, Texas Instruments Incorporated