6A595

6A595 ALLEGRO

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Data Sheet26185.121 8-BIT SERIAL-INPUT, DMOS POWER DRIVER The A6A595KA and A6A595KLB combine an 8-bit CMOS shift register and accompanying data latches, control circuitry, and DMOS power driver outputs. Power driver applications include relays, sole- noids, and other medium-current or high-voltage peripheral power loads. The serial-data input, CMOS shift register and latches allow direct interfacing with microprocessor-based systems. Serial-data input rates are over 5 MHz. Use with TTL may require appropriate pull-up resistors to ensure an input logic high. A CMOS serial-data output enables cascade connections in appli- cations requiring additional drive lines. The A6A595 DMOS open-drain outputs are capable of sinking up to 500 mA. All of the output drivers are disabled (the DMOS sink drivers turned off) by the OUTPUT ENABLE input high. The A6A595KA is furnished in a 20-pin dual in-line plastic package. The A6A595KLB is furnished in a 24-lead wide-body, small- outline plastic batwing package (SOIC) with gull-wing leads. Copper lead frames, reduced supply current requirements, and low on-state resistance allow both devices to sink 150 mA from all outputs continu- ously, to ambient temperatures over 85°C.

FEATURES

I 50 V Minimum Output Clamp Voltage I 350 mA Output Current (all outputs simultaneously) I 1 Ω Typical rDS(on) I Internal Short-Circuit Protection I Low Power Consumption I Replacements for TPIC6A595N and TPIC6A595DW 6A595 ADVANCE INFORMATION (Subject to change without notice) March 22, 2000 Always order by complete part number: Part Number Package R θJA RθJC RθJT A6A595KA 20-pin DIP55 °C/W 25 °C/W — A6A595KLB 24-lead SOIC 55 °C/W — 6 °C/W ABSOLUTE MAXIMUM RATINGS at TA = 25°C Output Drain Current, Single-Pulse Avalanche Energy, Input Voltage Range, Package Power Dissipation, Operating Temperature Range, Storage Temperature Range, * Each output, all outputs on. † Pulse duration ≤ 100 µs, duty cycle ≤ 2%. Caution: These CMOS devices have input static protection (Class 3) but are still susceptible to damage if exposed to extremely high static electrical charges. LATCHES REGISTER SERIAL DATA IN REGISTER CLEAR OUT3 VDD STROBE CLOCK CLK ST Dwg. PP-029-15 OUT2 OUTPUT ENABLE OE LOGIC GROUND CLR POWER GROUND POWER GROUND POWER GROUND POWER GROUND OUT5 OUT4 OUT6 OUT7 OUT1 OUT0 SERIAL DATA OUT LOGIC SUPPLY REGISTER LATCHES A6A595KA (DIP)

8-BIT SERIAL-INPUT, DMOS POWER DRIVER

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 2000, Allegro MicroSystems, Inc. FUNCTIONAL BLOCK DIAGRAM POWER GROUND Dwg. FP-013-6 OUT 0 OUTN POWER GROUND CLOCK SERIAL DATA IN STROBE OUTPUT ENABLE (ACTIVE LOW) SERIAL DATA OUT SERIAL-PARALLEL SHIFT REGISTER D-TYPE LATCHES VDD LOGIC SUPPLY REGISTER CLEAR (ACTIVE LOW) LOGIC GROUND CURRENT LIMIT AND CHARGE PUMP SUB Power grounds must be connected together externally. POWER GROUND POWER GROUND POWER GROUND POWER GROUND POWER GROUND POWER GROUND POWER GROUND POWER GROUND LATCHES REGISTER SERIAL DATA IN REGISTER CLEAR OUT3 VDD STROBE CLOCK CLK ST Dwg. PP-029-16A OUT2 OUTPUT ENABLE OE LOGIC GROUND CLR OUT5 OUT4 OUT6 OUT7 OUT1 OUT0 SERIAL DATA OUT LOGIC SUPPLY REGISTER LATCHES 81 7 A6A595KLB (SOIC) 50 75 100 125 150 ALLOWABLE PACKAGE POWER DISSIPATION IN WATTSTEMPERATURE IN °C Dwg. GP-049-5 SUFFIX 'LB', R = 6.0°C/WθJT R = 55°C/WθJA SUFFIX 'A', R = 25°C/WθJC

8-BIT SERIAL-INPUT, DMOS POWER DRIVER www.allegromicro.com TRUTH TABLE Shift Register Contents Serial Latch Contents Output Contents Data Clock Data Output HH R 0 R1 …R 5 R6 R6 LL R 0 R1 …R 5 R6 R6 XR 0 R1 R2 …R 6 R7 R7 XXX… XX X — R 0 R1 R2 …R 6 R7 P0 P1 P2 …P 6 P7 P7 P0 P1 P2 …P 6 P7 LP 0 P1 P2 …P 6 P7 XXX …XX H HHH…HH L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State SERIAL DATA OUT LOGIC INPUTS Dwg. EP-063-4 OUT VDD DMOS POWER DRIVER OUTPUT Dwg. EP-010-10 IN VDD Dwg. EP-063-5 OUT RECOMMENDED OPERATING CONDITIONS over operating temperature range

8-BIT SERIAL-INPUT, DMOS POWER DRIVER Worcester, Massachusetts 01615-0036 (508) 853-5000 Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units Output Breakdown V (BR)DSX IO = 1 mA 50 — — V Voltage Off-State Output I DSX VO = 40 V — 0.1 1.0 µA Current VO = 40 V, TA = 125°C— 0 . 2 5 . 0 µA Static Drain-Source rDS(on) IO = 350 mA — 1.0 1.5 Ω On-State Resistance IO = 350 mA, TA = 125°C— 1 . 7 2 . 5 Ω Source-to-Drain V SD IF = 350 mA — 1.0 — V Diode Voltage Nominal Output I O(nom) VDS(on) = 0.5 V, TA = 85°C — 350 — mA Current Output Current I O(chop) IO at which chopping starts, TC = 25°C 0.6 0.8 1.1 A Logic Input Current I IH VI = VDD ——1 . 0 µA IIL VI = 0 — — -1.0 µA SERIAL-DATA V OH IOH = -20 µA 4.9 4.99 — V Output Voltage IOH = -4 mA 4.5 4.7 — V VOL IOL = 20 µA— 0 0 . 1 V IOL = 4 mA — 0.3 0.5 V Prop. Delay Time t PLH IO = 350 mA, CL = 30 pF — 100 — ns tPHL IO = 350 mA, CL = 30 pF — 60 — ns Output Rise Time t r IO = 350 mA, CL = 30 pF — 55 — ns Output Fall Time t f IO = 350 mA, CL = 30 pF — 40 — ns Supply Current I DD(off) Outputs OFF — 0.5 5.0 mA IDD(fclk) fclk = 5 MHz, CL = 30 pF, Outputs OFF — — 1.3 mA Typical Data is at VDD = 5 V and is for design information only. NOTE — Pulse test, duration ≤100 µs, duty cycle ≤2%. ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V, tir = tif ≤ 10 ns (unless otherwise specified).

8-BIT SERIAL-INPUT, DMOS POWER DRIVER www.allegromicro.com TIMING REQUIREMENTS and SPECIFICATIONS (Logic Levels are VDD and Ground) CLOCK SERIAL DATA IN STROBE OUTPUT ENABLE OUTN Dwg. WP-029-2 50%SERIAL DATA OUT DATA DATA 50% 50% 50% C A B D E LOW = ALL OUTPUTS ENABLED pt DATA 50% pt LOW = OUTPUT ON HIGH = OUTPUT OFF OUTPUT ENABLE OUTN Dwg. WP-030-2 DATA 10% 50% PHLt PLHt HIGH = ALL OUTPUTS DISABLED 90% ft rt A. Data Active Time Before Clock Pulse B. Data Active Time After Clock Pulse D. Time Between Clock Activation NOTE – Timing is representative of a 12.5 MHz clock. Higher speeds are attainable. Serial data present at the input is transferred to the shift register on the rising edge of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. Information present at any register is transferred to the respective latch on the rising edge of the STROBE input pulse (serial-to-parallel conversion). When the OUTPUT ENABLE input is high, the output source drivers are disabled (OFF). The information stored in the latches is not affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE input low, the outputs are controlled by the state of their respective latches. LOGIC SYMBOL SRG8 R OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 SERIAL DATA OUT OUTPUT ENABLE STROBE REGISTER CLEAR SERIAL DATA IN CLOCK Dwg. FP-043-2

8-BIT SERIAL-INPUT, DMOS POWER DRIVER Worcester, Massachusetts 01615-0036 (508) 853-5000 TEST CIRCUITS Dwg. EP-066-1 OUT INPUT IO VO tav IAS = 1.0 A V(BR)DSX VO(ON) 0.11 Ω100 mH +15 V DUT Single-Pulse Avalanche Energy Test Circuit and Waveforms EAS = IAS x V(BR)DSX x tAV/2

8-BIT SERIAL-INPUT, DMOS POWER DRIVER www.allegromicro.com TERMINAL DESCRIPTIONS A6A595KA A6A595KLB (DIP) (SOIC) Terminal No. Terminal No. Terminal Name Function 1-2 1-2 OUT 2-3 Current-sinking, open-drain DMOS output terminals. 3 3 REGISTER CLEAR When (active) low, the registers are cleared (set low). 4 4 OUTPUT ENABLE When (active) low, the output drivers are enabled; when high, all output drivers are turned OFF (blanked). 5-6 5-8 POWER GROUND Reference terminal for output voltage measurements. 7 9 STROBE Data strobe input terminal; shift register data is latched on rising edge. 8 10 CLOCK Clock input terminal for data shift on rising edge. 9-12 11-14 OUT 4-7 Current-sinking, open-drain DMOS output terminals. 13 15 SERIAL DATA OUT CMOS serial-data output to the following shift register. 14 16 LOGIC GROUND Reference terminal for input voltage measurements. 15-16 17-20 POWER GROUND Reference terminal for output voltage measurements. 17 21 LOGIC SUPPLY (V DD) The logic supply voltage (typically 5 V). 18 22 SERIAL DATA IN Serial-data input to the shift-register. 19-20 23-24 OUT 0-1 Current-sinking, open-drain DMOS output terminals. NOTE —Power grounds must be connected together externally.

8-BIT SERIAL-INPUT, DMOS POWER DRIVER Worcester, Massachusetts 01615-0036 (508) 853-5000 A6A595KA Dimensions in Inches (controlling dimensions) Dimensions in Millimeters (for reference only) NOTES:1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative 3. Lead thickness is measured at seating plane or below. 0.014 0.008 0.300 BSC Dwg. MA-001-20 in 0.430 MAX 1 10 0.280 0.240 0.210 MAX 0.070 0.045 0.015 MIN 0.022 0.014 0.100 BSC 0.005 MIN 0.150 0.115 1.060 0.980 0.355 0.204 7.62 BSC Dwg. MA-001-20 mm 10.92 MAX 1 10 7.11 6.10 5.33 MAX 1.77 1.15 0.39 MIN 0.558 0.356 2.54 BSC 0.13 MIN 3.81 2.93 26.92 24.89

8-BIT SERIAL-INPUT, DMOS POWER DRIVER www.allegromicro.com A6A595KLB Dimensions in Inches (for reference only) Dimensions in Millimeters (controlling dimensions) 0° TO 8 1 2 3 0.2992 0.2914 0.6141 0.5985 0.491 0.394 0.020 0.013 0.0926 0.1043 0.0040 MIN. 0.0125 0.0091 Dwg. MA-008-25 in 0.050 BSC 24 13 NOTE 1 NOTE 3 0.050 0.016 0° TO 8 1 2 3 7.60 7.40 15.60 15.20 10.65 10.00 0.51 0.33 2.65 2.35 0.10 MIN. 0.32 0.23 Dwg. MA-008-25A mm 1.27 BSC 24 13 NOTE 1 NOTE 3 1.27 0.40 NOTES: 1. Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece. 2. Lead spacing tolerance is non-cumulative. 3. Exact body and lead configuration at vendor’s option within limits shown.

8-BIT SERIAL-INPUT, DMOS POWER DRIVER Worcester, Massachusetts 01615-0036 (508) 853-5000 The products described here are manufactured under one or more Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsi- bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.