6818

6818 ALLEGRO

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DABiC-IV , 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER Data Sheet26182.128D The A6818– devices combine a 32-bit CMOS shift register, accompanying data latches and control circuitry with bipolar sourcing outputs and pnp active pull downs. Designed primarily to drive vacuum-fluorescent displays, the 60 V and - 40 mA output ratings also allow these devices to be used in many other peripheral power driver applications. The A6818– features an increased data input rate (compared with the older UCN/UCQ5818–F) and a controlled output slew rate. The CMOS shift register and latches allow direct interfacing with micro- processor-based systems. With a 3.3 V or 5 V logic supply, typical serial-data input rates are up to 33 MHz. A CMOS serial data output permits cascade connections in applications requiring additional drive lines. Similar devices are available as the A6810– (10 bits) and A6812– (20 bits). The A6818– output source drivers are npn Darlingtons, capable of sourcing up to 40 mA. The controlled output slew rate reduces electromag- netic noise, which is an important consideration in systems that include telecommunications and/or microprocessors and to meet government emis- sions regulations. For inter-digit blanking, all output drivers can be disabled and all sink drivers turned on with a BLANKING input high. The pnp active pull-downs will sink at least 2.5 mA. Three temperature ranges are available for optimum performance in commercial (suffix S-), industrial (E-), and extended industrial (K-) applica- tions. The package style provided is the minimum-area surface-mount PLCC (suffix -EP). Copper lead frames, low logic-power dissipation, and low output-saturation voltages allow these devices to drive most multiplexed vacuum-fluorescent displays over the maximum operating temperature range. The lead (Pb) free versions have 100% matte tin leadframe plating.

FEATURES

■ Controlled Output Slew Rate ■ High-Speed Data Storage ■ 60 V Minimum ■ High Data Input Rate Output Breakdown ■ Low Output-Saturation Voltages ■ PNP Active Pull-Downs ■ Improved Replacements ■ Low-Power CMOS Logic for SN75518N, SN75518NF, and Latches UCN5818–, and UCQ5818– ABSOLUTE MAXIMUM RATINGS at TA = 25°C Continuous Output Current Range, Input Voltage Range, Package Power Dissipation, Operating Temperature Range, T A Storage Temperature Range, Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high static electrical charges. A6818xEP 6818 Part Number Pb-free Packing Ambient Temperature, T A (°C) A6818EEP – 27 pieces/tubeA6818EEP-T Yes –40 to 85A6818EEPTR – 450 pieces/13-in. reelA6818EEPTR-T Yes A6818KEP – 27 pieces/tubeA6818KEP-T Yes –40 to 125A6818KEPTR – 450 pieces/13-in. reelA6818KEPTR-T Yes A6818SEP – 27 pieces/tubeA6818SEP-T Yes –20 to 85A6818SEPTR – 450 pieces/13-in. reelA6818SEPTR-T Yes Always order by complete part number:

32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 1998, 2003 Allegro MicroSystems, Inc. A6818xEP TYPICAL OUTPUT DRIVER TYPICAL INPUT CIRCUIT 50 75 100 125 150 2.5 0.5 ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS AMBIENT TEMPERATURE IN °°°°C 2.0 1.5 1.0 Dwg. GP-025B 3.0 SUFFIX 'EP', RθJA = 54°C/W Dwg. EP-010-5 IN V DD V BB Dwg. EP-021-19 OUT N DD VBB LOAD SUPPLY SERIAL DATA IN LOGIC SUPPLY OUT 30 NC SERIAL DATA OUT OUT 1 OUT 8 OUT 29 OUT OUT 4 OUT 13 NC ST CLK OUT 16 OUT 17 CLOCK STROBE GROUND BLANKING OUT 15 Dwg. PP-059-2 OUT 14 27 28NC OUT 18 NC BLNK 17OUT V OUT 3 OUT 2 OUT 32 OUT 31 REGISTER LATCHES LATCHES REGISTER

32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER www.allegromicro.com FUNCTIONAL BLOCK DIAGRAM TRUTH TABLE Serial Shift Register Contents Serial Latch Contents Output Contents Data Clock Data Strobe Input Input I HH R 1 R 2 ... RN-2 R N-1 R N-1 LL R 1 R 2 ... RN-2 R N-1 R N-1 XR 1 R 2 R 3 ... RN-1 R N R N L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State MOS BIPOLAR OUT 1 OUT 2GROUND Dwg. FP-013-1OUT 3 OUT N CLOCK SERIAL DATA IN STROBE BLANKING SERIAL DATA OUTSERIAL-PARALLEL SHIFT REGISTER LATCHES V DD VBB LOGIC SUPPLY LOAD SUPPLY

32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER Worcester, Massachusetts 01615-0036 (508) 853-5000 ELECTRICAL CHARACTERISTICS at TA = +25°C (A6818S-) or over operating temperature range (A6818E- and A6818K-), VBB = 60 V unless otherwise noted. Limits @ VDD = 3.3 V Limits @ VDD = 5 V Output Leakage Current I CEX VOUT = 0 V — <-0.1 -15 — <-0.1 -15 µA Output Voltage V OUT(1) IOUT = -25 mA 57.5 58.3 — 57.5 58.3 — V VOUT(0) IOUT = 1 mA — 1.0 1.5 — 1.0 1.5 V Output Pull-Down Current I OUT(0) VOUT = 5 V to VBB 2.5 5.0 — 2.5 5.0 — mA Input Voltage V IN(1) 2.2 — — 3.3 — — V Input Current I IN(1) VIN = VDD — <0.01 1.0 — <0.01 1.0 µA Input Clamp Voltage V IK IIN = -200 µA — -0.8 -1.5 — -0.8 -1.5 V Serial Data Output Voltage VOUT(1) IOUT = -200 µA 2.8 3.05 — 4.5 4.75 — V VOUT(0) IOUT = 200 µA — 0.15 0.3 — 0.15 0.3 V Maximum Clock Frequency f c 10 33 — 10 33 — MHz Logic Supply Current I DD(1) All Outputs High — 0.25 0.75 — 0.3 1.0 mA IDD(0) All Outputs Low — 0.25 0.75 — 0.3 1.0 mA Load Supply Current I BB(1) All Outputs High, No Load — 4.5 9.0 — 4.5 9.0 mA IBB(0) All Outputs Low — 0.2 20 — 0.2 20 µA Blanking-to-Output Delay t dis(BQ) C L = 30 pF, 50% to 50% — 0.7 2.0 — 0.7 2.0 µs ten(BQ) C L = 30 pF, 50% to 50% — 1.8 3.0 — 1.8 3.0 µs Output Fall Time t f R L = 2.3 kΩ , CL ≤ 30 pF 2.4 — 12 2.4 — 12 µs Output Rise Time t r R L = 2.3 kΩ , CL ≤ 30 pF 2.4 — 12 2.4 — 12 µs Output Slew Rate dV/dt R L = 2.3 kΩ , CL ≤ 30 pF 4.0 — 20 4.0 — 20 V/ µs Clock-to-Serial Data Out Delay tp(CH-SQX) IOUT = ±200 µA — 50 — — 50 — ns Negative current is defined as coming out of (sourcing) the specified device terminal. Typical data is is for design information only and is at TA = +25°C.

32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER www.allegromicro.com TIMING REQUIREMENTS and SPECIFICATIONS (Logic Levels are VDD and Ground) Serial Data present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the BLANKING input be high during serial data entry. When the BLANKING input is high, the output source drivers are disabled (OFF); the pnp active pull-down sink drivers are ON. The information stored in the latches is not affected by the BLANKING input. With the BLANKING input low, the outputs are controlled by the state of their respective latches. CLOCK SERIAL DATA IN STROBE BLANKING OUT N Dwg. WP-029 50%SERIAL DATA OUT DATA DATA 10% 90% 50% 50% 50% C A B D E LOW = ALL OUTPUTS ENABLED p(STH-QL)t p(CH-SQX)t DATA p(STH-QH)t BLANKING OUT N Dwg. WP-030A DATA 10% 50% en(BQ)t dis(BQ)t HIGH = ALL OUTPUTS BLANKED (DISABLED) rt ft 50% 90% A. Data Active Time Before Clock Pulse B. Data Active Time After Clock Pulse NOTE – Timing is representative of a 10 MHz clock. Signifi- cantly higher speeds are attainable.

32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER www.allegromicro.com A6818EEP & A6818SEP Dimensions in Inches (controlling dimensions) Dimensions in Millimeters (for reference only) 1828 Dwg. MA-005-44A in 0.020 MIN 0.050 BSC 144 0.021 0.013 INDEX AREA 2 6 1729 0.695 0.685 0.032 0.026 0.319 0.291 0.319 0.291 0.180 0.165 0.695 0.685 0.656 0.650 0.656 0.650 Dwg. MA-005-44A mm 17.65 17.40 0.51 MIN 4.57 4.20 17.65 17.40 16.662 16.5101.27 BSC 0.812 0.661 144 0.533 0.331 INDEX AREA 16.662 16.510 8.10 7.39 8.10 7.39 NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative.

32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER Worcester, Massachusetts 01615-0036 (508) 853-5000 The products described here are manufactured under one or more Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsi- bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.