6812

6812 ALLEGRO

Document overview

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Technical content

Dwg. PP-029-7 OUT19 OUT18 OUT13 14 27 SERIAL DATA OUT BLANKING LOGIC SUPPLY STROBE GROUND CLOCKCLK STBLNK OUT9 OUT10 OUT12 OUT11 LATCHES REGISTER REGISTER LATCHES 32 6 SERIAL DATA IN OUT 6 OUT1 OUT4 OUT3 OUT20 OUT5 OUT 17 OUT 16 OUT15 OUT14 DDV DABiC-IV , 20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER A6812xA Data Sheet26182.126A ABSOLUTE MAXIMUM RATINGS at TA = 25°C Continuous Output Current Range, Input Voltage Range, Package Power Dissipation, Operating Temperature Range, T A Storage Temperature Range, Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high static electrical charges. The A6812– devices combine a 20-bit CMOS shift register, accompanying data latches and control circuitry with bipolar sourcing outputs and pnp active pull downs. Designed primarily to drive vacuum-fluorescent displays, the 60 V and -40 mA output ratings also allow these devices to be used in many other peripheral power driver applications. The A6812– features an increased data input rate (com- pared with the older UCN/UCQ5812-F) and a controlled output slew rate. The CMOS shift register and latches allow direct interfacing with microprocessor-based systems. With a 3.3 V or 5 V logic supply, they will operate to at least 10 MHz. A CMOS serial data output permits cascade connections in applica- tions requiring additional drive lines. Similar devices are available as the A6809– and A6810– (10 bits), A6811– (12 bits), and A6818– (32 bits). The A6812– output source drivers are npn Darlingtons, capable of sourcing up to 40 mA. The controlled output slew rate reduces electro- magnetic noise, which is an important consideration in systems that include telecommunications and/or microprocessors and to meet government emissions regulations. For inter-digit blanking, all output drivers can be disabled and all sink drivers turned on with a BLANK- ING input high. The pnp active pull-downs will sink at least 2.5 mA. Two temperature ranges are available for optimum performance in commercial (suffix S-) or industrial (suffix E-) applications. Package styles are provided for through-hole DIP (suffix -A), surface-mount SOIC (suffix -LW), or minimum-area surface-mount PLCC (suffix -EP). Copper lead frames, low logic-power dissipation, and low output-saturation voltages allow these drivers to source 25 mA from all outputs continuously to more than +43°C (suffix -LW), +61°C (suffix -EP), or +77°C (suffix -A).

FEATURES

I Controlled Output Slew Rate I High-Speed Data Storage I 60 V Minimum Output Breakdown I High Data Input Rate I PNP Active Pull-Downs Complete part number includes a suffix to identify operating temperature range (E- or S-) and package type (-A, -EP, or -LW). Always order by complete part number, e.g., A6812SLW . 681 2 I Low Output-Saturation Voltages I Low-Power CMOS Logic and Latches I Improved Replacements for TL5812–, UCN5812–, and UCQ5812–

20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000 A6812xEP A6812xLW 10 19 LOAD SUPPLY BBV OUT2 OUT7 OUT8 Dwg. PP-029-8 OUT19 OUT18 OUT13 14 27 SERIAL DATA OUT BLANKING LOGIC SUPPLY STROBE GROUND CLOCKCLK STBLNK OUT9 OUT10 OUT12 OUT11 LATCHES REGISTER REGISTER LATCHES 32 6 SERIAL DATA IN OUT6 OUT1 OUT4 OUT3 OUT20 OUT5 OUT17 OUT16 OUT15 OUT14 DDV TYPICAL INPUT CIRCUIT Dwg. EP-010-5 IN VDD 16 28 VDD Dwg. PP-059-1 OUT10 OUT20 OUT11 OUT19 REGISTER LATCHES VBBCLOCK ST CLK SERIAL DATA OUT LOAD SUPPLY SERIAL DATA IN STROBE GROUND LOGIC SUPPLY BLANKING 18OUT9 OUT1 OUT2 OUT8 OUT18 OUT12 LATCHES REGISTER 50 75 100 125 150 2.5 0.5 ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS AMBIENT TEMPERATURE IN °C 2.0 1.5 1.0 Dwg. GP-024-2 SUFFIX 'LW ', R = 66 °C/W θJA SUFFIX 'EP', R = 55 °C/W θJA SUFFIX 'A', R = 45 °C/W θJA VBB Dwg. EP-021-19 OUTN TYPICAL OUTPUT DRIVER Copyright © 2000, Allegro MicroSystems, Inc.

20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER www.allegromicro.com FUNCTIONAL BLOCK DIAGRAM TRUTH TABLE Serial Shift Register Contents Serial Latch Contents Output Contents Data Clock Data Strobe Input Input I HH R 1 R2 ... R N-2 RN-1 RN-1 LL R 1 R2 ... R N-2 RN-1 RN-1 XR 1 R2 R3 ... R N-1 RN RN L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State MOS BIPOLAR OUT 1 OUT 2GROUND Dwg. FP-013-1OUT 3 OUT N CLOCK SERIAL DATA IN STROBE BLANKING SERIAL DATA OUTSERIAL-PARALLEL SHIFT REGISTER LATCHES VDD VBB LOGIC SUPPLY LOAD SUPPLY

20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER Worcester, Massachusetts 01615-0036 (508) 853-5000 ELECTRICAL CHARACTERISTICS at TA = +25°C (A6812S-) or over operating temperature range (A6812E-), VBB = 60 V unless otherwise noted. Limits @ VDD = 3.3 V Limits @ V DD = 5 V Output Leakage Current I CEX VOUT = 0 V — <-0.1 -15 — <-0.1 -15 µA Output Voltage V OUT(1) IOUT = -25 mA 57.5 58.3 — 57.5 58.3 — V VOUT(0) IOUT = 1 mA — 1.0 1.5 — 1.0 1.5 V Output Pull-Down Current I OUT(0) VOUT = 5 V to VBB 2.5 5.0 — 2.5 5.0 — mA Input Voltage V IN(1) 2.2 —— 3.3 —— V Input Current I IN(1) VIN = VDD — <0.01 1.0 — <0.01 1.0 µA Input Clamp Voltage V IK IIN = -200 µA — -0.8 -1.5 — -0.8 -1.5 V Serial Data Output Voltage V OUT(1) IOUT = -200 µA 2.8 3.05 — 4.5 4.75 — V VOUT(0) IOUT = 200 µA — 0.15 0.3 — 0.15 0.3 V Maximum Clock Frequency f c 10* —— 10* —— MHz Logic Supply Current I DD(1) All Outputs High — 0.25 0.75 — 0.3 1.0 mA IDD(0) All Outputs Low — 0.25 0.75 — 0.3 1.0 mA Load Supply Current I BB(1) All Outputs High, No Load — 3.0 6.0 — 3.0 6.0 mA IBB(0) All Outputs Low — 0.2 20 — 0.2 20 µA Blanking-to-Output Delay t dis(BQ) CL = 30 pF, 50% to 50% — 0.7 2.0 — 0.7 2.0 µs ten(BQ) CL = 30 pF, 50% to 50% — 1.8 3.0 — 1.8 3.0 µs Output Fall Time t f RL = 2.3 kΩ, CL ≤ 30 pF 2.4 — 12 2.4 — 12 µs Output Rise Time t r RL = 2.3 kΩ, CL ≤ 30 pF 2.4 — 12 2.4 — 12 µs Output Slew Rate dV/dt R L = 2.3 kΩ, CL ≤ 30 pF 4.0 — 20 4.0 — 20 V/ µs Clock-to-Serial Data Out Delay t p(CH-SQX) IOUT = ±200 µA — 50 —— 50 — ns Negative current is defined as coming out of (sourcing) the specified device terminal. Typical data is is for design information only and is at T A = +25°C. * Operation at a clock frequency greater than the specified minimum is possible but not warranteed.

20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER www.allegromicro.com TIMING REQUIREMENTS and SPECIFICATIONS (Logic Levels are VDD and Ground) Serial Data present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the BLANKING input be high during serial data entry. When the BLANKING input is high, the output source drivers are disabled (OFF); the pnp active pull-down sink drivers are ON. The information stored in the latches is not affected by the BLANKING input. With the BLANKING input low, the outputs are controlled by the state of their respective latches. CLOCK SERIAL DATA IN STROBE BLANKING OUTN Dwg. WP-029 50%SERIAL DATA OUT DATA DATA 10% 90% 50% 50% 50% C A B D E LOW = ALL OUTPUTS ENABLED p(STH-QL)t p(CH-SQX)t DATA p(STH-QH)t BLANKING OUTN Dwg. WP-030 DATA 10% 50% en(BQ)t dis(BQ)t HIGH = ALL OUTPUTS BLANKED (DISABLED) 90% rt ft A. Data Active Time Before Clock Pulse B. Data Active Time After Clock Pulse NOTE – Timing is representative of a 10 MHz clock. Higher speeds may be attainable with increased supply voltage; operation at high temperatures will reduce the specified maximum clock frequency.

20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER Worcester, Massachusetts 01615-0036 (508) 853-5000 A6812EA & A6812SA Dimensions in Inches (controlling dimensions) Dimensions in Millimeters (for reference only) NOTES: 1. Exact body and lead configuration at vendor ’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. 4. Supplied in standard sticks/tubes of 12 devices. 1 2 3 0.250 MAX 0.070 0.030 0.015 MIN 0.022 0.014 0.015 0.008 0.600 BSC Dwg. MA-003-28 in 0.100 BSC 0.005 MIN 0.200 0.115 0.700 MAX 1.565 1.380 0.580 0.485 14.73 12.32 1 2 3 6.35 MAX 1.77 0.77 0.39 MIN 0.558 0.356 0.381 0.204 15.24 BSC Dwg. MA-003-28 mm 2.54 BSC 0.13 MIN 5.08 2.93 17.78 MAX 39.7 35.1

20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER www.allegromicro.com A6812EEP & A6812SEP (add “TR” to part number for tape and reel) Dimensions in Inches (controlling dimensions) NOTES: 1. Exact body and lead configuration at vendor ’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Supplied in standard sticks/tubes of 38 devices or add “TR” to part number for tape and reel. 18 12 0.020 MIN 0.050 BSC 128 INDEX AREA Dwg. MA-005-28A in 0.026 0.032 0.013 0.021 19 11 0.165 0.180 0.495 0.485 0.456 0.450 0.495 0.485 0.456 0.450 0.219 0.191 0.219 0.191 0.51 MIN 4.57 4.20 1.27 BSC 12.57 12.32 11.582 11.430 128 INDEX AREA Dwg. MA-005-28A mm 0.812 0.661 0.331 0.533 12.57 12.32 18 12 11.58 11.43 5.56 4.85 5.56 4.85 Dimensions in Millimeters (for reference only))

20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER Worcester, Massachusetts 01615-0036 (508) 853-5000 A6812ELW & A6812SLW (add “TR” to part number for tape and reel) Dimensions in Inches (for reference only) Dimensions in Millimeters (controlling dimensions) NOTES: 1. Exact body and lead configuration at vendor ’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Supplied in standard sticks/tubes of 27 devices or add “TR” to part number for tape and reel. 0° TO 8° 2 3 18.10 17.70 0.51 0.33 2.65 2.35 0.10 MIN. 0.32 0.23 1.27 0.40 Dwg. MA-008-28A mm 1.27 BSC 7.60 7.40 10.65 10.00 0° TO 8° 1 2 30.020 0.013 0.0040 MIN. Dwg. MA-008-28A in 0.050 BSC 28 15 0.0125 0.0091 0.050 0.016 0.2992 0.2914 0.419 0.394 0.7125 0.69690.0926 0.1043

20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER www.allegromicro.com The products described here are manufactured under one or more Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsi- bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.

20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER Worcester, Massachusetts 01615-0036 (508) 853-5000 POWER INTERFACE DRIVERS Function Output Ratings* Part Number † SERIAL-INPUT LATCHED DRIVERS 8-Bit (saturated drivers) -120 mA 50 V‡ 5895 8-Bit 350 mA 50 V 5821 8-Bit 350 mA 80 V 5822 8-Bit 350 mA 50 V‡ 5841 8-Bit 350 mA 80 V‡ 5842 8-Bit (constant-current LED driver) 75 mA 17 V 6275 8-Bit (DMOS drivers) 250 mA 50 V 6595 8-Bit (DMOS drivers) 350 mA 50 V‡ 6A595 8-Bit (DMOS drivers) 100 mA 50 V 6B595 10-Bit (active pull-downs) -25 mA 60 V 5810-F and 6809/10 12-Bit (active pull-downs) -25 mA 60 V 5811 and 6811 16-Bit (constant-current LED driver) 75 mA 17 V 6276 20-Bit (active pull-downs) -25 mA 60 V 5812-F and 6812 32-Bit (active pull-downs) -25 mA 60 V 5818-F and 6818 32-Bit 100 mA 30 V 5833 32-Bit (saturated drivers) 100 mA 40 V 5832 PARALLEL-INPUT LATCHED DRIVERS 4-Bit 350 mA 50 V‡ 5800 8-Bit -25 mA 60 V 5815 8-Bit 350 mA 50 V‡ 5801 8-Bit (DMOS drivers) 100 mA 50 V 6B273 8-Bit (DMOS drivers) 250 mA 50 V 6273 SPECIAL-PURPOSE DEVICES Unipolar Stepper Motor Translator/Driver 1.25 A 50 V‡ 5804 Addressable 8-Bit Decoder/DMOS Driver 250 mA 50 V 6259 Addressable 8-Bit Decoder/DMOS Driver 350 mA 50 V‡ 6A259 Addressable 8-Bit Decoder/DMOS Driver 100 mA 50 V 6B259 Addressable 28-Line Decoder/Driver 450 mA 30 V 6817 * Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits. Negative current is defined as coming out of (sourcing) the output. † Complete part number includes additional characters to indicate operating temperature range and package style. ‡ Internal transient-suppression diodes included for inductive-load protection.