6811

6811 ALLEGRO

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DABiC-IV , 12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER A6811xA Data Sheet26182.120 ABSOLUTE MAXIMUM RATINGS at TA = 25°C Continuous Output Current Range, Input Voltage Range, Package Power Dissipation, Operating Temperature Range, T A Storage Temperature Range, Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high static electrical charges. The A6811– devices combine a 12-bit CMOS shift register, accompanying data latches and control circuitry with bipolar sourcing outputs and pnp active pull downs. Designed primarily to drive vacuum-fluorescent displays, the 60 V and -40 mA output ratings also allow these devices to be used in many other peripheral power driver applications. The A6811– features an increased data input rate (com- pared with the older UCN/UCQ5811A) and a controlled output slew rate. The CMOS shift register and latches allow direct interfacing with microprocessor-based systems. With a 3.3 V or 5 V logic supply, typical serial-data input rates are up to 33 MHz. A CMOS serial data output permits cascade connections in applica- tions requiring additional drive lines. Similar devices are available as the A6809– and A6810– (10 bits), A6812– (20 bits), and A6818– (32 bits). The A6811– output source drivers are npn Darlingtons, capable of sourcing up to 40 mA. The controlled output slew rate reduces electro- magnetic noise, which is an important consideration in systems that include telecommunications and/or microprocessors and to meet government emissions regulations. For inter-digit blanking, all output drivers can be disabled and all sink drivers turned on with a BLANK- ING input high. The pnp active pull-downs will sink at least 2.5 mA. Two temperature ranges are available for optimum performance in commercial (suffix S-) or industrial (suffix E-) applications. Package styles are provided for through-hole DIP (suffix -A) and surface-mount SOIC or PLCC (suffix -LW or -EP). Copper lead frames, low logic- power dissipation, and low output-saturation voltages allow all devices to source 25 mA from all outputs continuously at up to 83 °C.

FEATURES

I Controlled Output Slew Rate I High-Speed Data Storage I 60 V Minimum Output Breakdown I High Data Input Rate I PNP Active Pull-Downs I Low Output-Saturation Voltages Complete part number includes a suffix to identify operating temperature range (E- or S-) and package type (-A, -EP, or -LW). Always order by complete part number, e.g., A6811SLW . SERIAL DATA OUT SERIAL DATA IN BLANKING LOGIC SUPPLY STROBE CLOCK OUT1 OUT2 OUT11 OUT12 LOAD SUPPLYBBV VDD ST GROUND CLK BLNK OUT9 OUT10 OUT3 Dwg. PP-029-5 OUT8 OUT7 OUT6 OUT5 OUT4 REGISTER LATCHES 681 1 PRELIMINARY INFORMATION (subject to change without notice) May 15, 2000 I Low-Power CMOS Logic and Latches I Improved Replacements for SN75512B, UCN5811–, and UCQ5811–

12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000 A6811xLW SERIAL DATA OUT SERIAL DATA IN BLANKING LOGIC SUPPLY STROBE CLOCK OUT1 OUT2 OUT11 OUT12 LOAD SUPPLYBBV VDD ST GROUND CLK BLNK OUT9 OUT10 OUT3 Dwg. PP-029-6 OUT8 OUT7 OUT6 OUT5 OUT4 REGISTER LATCHES Copyright © 2000, Allegro MicroSystems, Inc. A6811xEP VBB Dwg. EP-021-19 OUTN TYPICAL OUTPUT DRIVER 50 75 100 125 150 2.5 0.5 ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS AMBIENT TEMPERATURE IN °C 2.0 1.5 1.0 SUFFIX 'A', R = 55°C/WθJA Dwg. GP-024-5 SUFFIX 'EP', R = 59°C/WθJA SUFFIX 'LW', R = 70°C/WθJA 13 19 STROBE V DD Dwg. PP-059-4 OUT 5 OUT 9 OUT 1 OUT 12 V BB CLOCK GROUND LOGIC SUPPLY SERIAL DATA OUT LOAD SUPPLY SERIAL DATA IN BLANKING ST CLK BLNK OUT 6 OUT 7 OUT 8 REGISTER LATCHES Dwg. EP-010-5 IN VDD TYPICAL INPUT CIRCUIT

12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER www.allegromicro.com FUNCTIONAL BLOCK DIAGRAM TRUTH TABLE Serial Shift Register Contents Serial Latch Contents Output Contents Data Clock Data Strobe Input Input I HH R 1 R2 ... R N-2 RN-1 RN-1 LL R 1 R2 ... R N-2 RN-1 RN-1 XR 1 R2 R3 ... R N-1 RN RN L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State MOS BIPOLAR OUT 1 OUT 2GROUND Dwg. FP-013-1OUT 3 OUT N CLOCK SERIAL DATA IN STROBE BLANKING SERIAL DATA OUTSERIAL-PARALLEL SHIFT REGISTER LATCHES VDD VBB LOGIC SUPPLY LOAD SUPPLY

12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER Worcester, Massachusetts 01615-0036 (508) 853-5000 ELECTRICAL CHARACTERISTICS at TA = +25°C (A6811S-) or over operating temperature range (A6811E-), VBB = 60 V unless otherwise noted. Limits @ VDD = 3.3 V Limits @ V DD = 5 V Output Leakage Current I CEX VOUT = 0 V — <-0.1 -15 — <-0.1 -15 µA Output Voltage V OUT(1) IOUT = -25 mA 57.5 58.3 — 57.5 58.3 — V VOUT(0) IOUT = 1 mA — 1.0 1.5 — 1.0 1.5 V Output Pull-Down Current I OUT(0) VOUT = 5 V to VBB 2.5 5.0 — 2.5 5.0 — mA Input Voltage V IN(1) 2.2 —— 3.3 —— V Input Current I IN(1) VIN = VDD — <0.01 1.0 — <0.01 1.0 µA Input Clamp Voltage V IK IIN = -200 µA — -0.8 -1.5 — -0.8 -1.5 V Serial Data Output Voltage V OUT(1) IOUT = -200 µA 2.8 3.05 — 4.5 4.75 — V VOUT(0) IOUT = 200 µA — 0.15 0.3 — 0.15 0.3 V Maximum Clock Frequency f c 10 33 — 10 33 — MHz Logic Supply Current I DD(1) All Outputs High — 0.25 0.75 — 0.3 1.0 mA IDD(0) All Outputs Low — 0.25 0.75 — 0.3 1.0 mA Load Supply Current I BB(1) All Outputs High, No Load — 1.7 3.5 — 1.7 3.5 mA IBB(0) All Outputs Low — 0.2 20 — 0.2 20 µA Blanking-to-Output Delay t dis(BQ) CL = 30 pF, 50% to 50% — 0.7 2.0 — 0.7 2.0 µs ten(BQ) CL = 30 pF, 50% to 50% — 1.8 3.0 — 1.8 3.0 µs Output Fall Time t f RL = 2.3 kΩ, CL ≤ 30 pF 2.4 — 12 2.4 — 12 µs Output Rise Time t r RL = 2.3 kΩ, CL ≤ 30 pF 2.4 — 12 2.4 — 12 µs Output Slew Rate dV/dt R L = 2.3 kΩ, CL ≤ 30 pF 4.0 — 20 4.0 — 20 V/ µs Clock-to-Serial Data Out Delay t p(CH-SQX) IOUT = ±200 µA — 50 —— 50 — ns Negative current is defined as coming out of (sourcing) the specified device terminal. Typical data is is for design information only and is at T A = +25°C.

12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER www.allegromicro.com TIMING REQUIREMENTS and SPECIFICATIONS (Logic Levels are VDD and Ground) Serial Data present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the BLANKING input be high during serial data entry. When the BLANKING input is high, the output source drivers are disabled (OFF); the pnp active pull-down sink drivers are ON. The information stored in the latches is not affected by the BLANKING input. With the BLANKING input low, the outputs are controlled by the state of their respective latches. CLOCK SERIAL DATA IN STROBE BLANKING OUTN Dwg. WP-029 50%SERIAL DATA OUT DATA DATA 10% 90% 50% 50% 50% C A B D E LOW = ALL OUTPUTS ENABLED p(STH-QL)t p(CH-SQX)t DATA p(STH-QH)t BLANKING OUTN Dwg. WP-030 DATA 10% 50% en(BQ)t dis(BQ)t HIGH = ALL OUTPUTS BLANKED (DISABLED) 90% rt ft A. Data Active Time Before Clock Pulse B. Data Active Time After Clock Pulse NOTE – Timing is representative of a 10 MHz clock. Signifi- cantly higher speeds are attainable.

12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER Worcester, Massachusetts 01615-0036 (508) 853-5000 A6811EA & A6811SA Dimensions in Inches (controlling dimensions) Dimensions in Millimeters (for reference only) NOTES: 1. Exact body and lead configuration at vendor ’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. 0.014 0.008 0.300 BSC Dwg. MA-001-20 in 0.430 MAX 1 10 0.280 0.240 0.210 MAX 0.070 0.045 0.015 MIN 0.022 0.014 0.100 BSC 0.005 MIN 0.150 0.115 1.060 0.980 0.355 0.204 7.62 BSC Dwg. MA-001-20 mm 10.92 MAX 1 10 7.11 6.10 5.33 MAX 1.77 1.15 0.39 MIN 0.558 0.356 2.54 BSC 0.13 MIN 3.81 2.93 26.92 24.89

12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER www.allegromicro.com A6811EEP & A6811SEP Dimensions in Inches (controlling dimensions) Dimensions in Millimeters (for reference only) NOTES: 1. Exact body and lead configuration at vendor ’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. The products described here are manufactured under one or more Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsi- bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. 913 0.51 MIN 4.57 4.20 1.27 BSC 120 2 Dwg. MA-005-20A mm 10.03 9.78 9.042 8.890 0.812 0.661 0.533 0.331 814 9.042 8.890 10.03 9.78 INDEX AREA 4.29 3.58 4.29 3.58 913 0.020 MIN 0.180 0.165 0.050 BSC 120 2 Dwg. MA-005-20A in 0.395 0.385 0.356 0.350 0.032 0.026 0.021 0.013 814 0.356 0.350 0.395 0.385 INDEX AREA 0.169 0.141 0.169 0.141

12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER Worcester, Massachusetts 01615-0036 (508) 853-5000 A6811ELW & A6811SLW Dimensions in Inches (for reference only) Dimensions in Millimeters (controlling dimensions) NOTES: 1. Exact body and lead configuration at vendor ’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 0° TO 8° 2 30.51 0.33 0.10 MIN. Dwg. MA-008-20 mm 1.27 BSC 0.32 0.23 1.27 0.40 7.60 7.40 10.65 10.00 13.00 12.60 2.65 2.35 0° TO 8° 1 2 30.020 0.013 0.0040 MIN. 0.0125 0.0091 0.050 0.016 Dwg. MA-008-20 in 0.050 BSC 20 11 0.2992 0.2914 0.419 0.394 0.5118 0.4961 0.0926 0.1043