67997-108HLF

F2911 RENESAS

Document overview

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Technical content

Features

 Low insertion loss: 0.33dB at 1200MHz  High isolation: 53dB at 1200MHz  Supply voltage: +2.7V to +5.5V  1.8V and 3.3V compatible control logic  -40°C to +105°C operating temperature range  2mm x 2mm, 8-pin DFN package Block Diagram Figure 1. Block Diagram

Figure 2. Pin Assignments for 2mm x 2mm x 0.9mm 8-DFN – Top View Table 1. Pin Descriptions 1, 4 NC No internal connection. This pin may be connected to the exposed paddle and can be grounded. external coupling capacitor must be used. 6 VDD Power supply. Bypass to GND with capacitors as shown in the Figure 16 as close as possible to pin. 7 V1 Logic control pin. See Table 7 for proper logic setting. 8 RF2 RF2 port. Matched to 75Ω. If this pin is not 0V DC, then an external coupling capacitor must be used. multiple ground vias are also required to achieve the specified RF performance.

conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings a. TEP = Temperature at the exposed paddle (see Table 3). b. 5% duty cycle of a 4.6ms period.

Table 3. Recommended Operating Conditions b. 5% duty cycle of a 4.6ms period. Figure 3. Maximum RF Input Operating Power vs. RF Frequency (ZS = ZL = 75Ω)

© 2017 Integrated Device Technology, Inc. 5 Rev O, September 21, 2017

Electrical Characteristics

Table 4. Electrical Characteristics driven port = RF2, PIN = 0dBm, ZS = ZL = 75Ω. PCB board trace and connector losses are de-embedded unless otherwise noted. a. Items in min/max columns in bold italics are guaranteed by test (GBT). b. Items in min/max columns that are not bold italics are guaranteed by design characterization (GBDC). c. Maximum specification limit is GBT at 50MHz and 1.8GHz, and it is GBDC over the whole frequency range. d. Return loss includes mismatch effects of the Evaluation Kit PCB and RF connectors.

© 2017 Integrated Device Technology, Inc. 6 Rev O, September 21, 2017 Table 5. Electrical Characteristics driven port = RF2, PIN = 0dBm, ZS = ZL = 75Ω. PCB board trace and connector losses are de-embedded unless otherwise noted. a. Items in min/max columns in bold italics are guaranteed by test. b. Items in min/max columns not in bold italics are guaranteed by design characterization. section and Figure 3 for the maximum operating power levels. d. RF1 or RF2 driven IIP2 and IIP3 results when in the insertion loss state. e. Spurious due to on-chip negative voltage generator. Spurious fundamental = approximately 5.7MHz.

Table 6. Package Thermal Characteristics  Small signal tests done at 0dBm input power.  All temperatures are referenced to the exposed paddle. loss and effects of the PCB.

© 2017 Integrated Device Technology, Inc. 10 Rev O, September 21, 2017 Control Mode Table 7. Switch Control Truth Table

Application Information

The V1 control pin includes no internal pull-down resistors to logic LOW or pull-up resistors to logic HIGH. Power Supplies A common VDD power supply should be used for all pins requiring DC power. All supply pins should be bypassed with external capacitors to minimize noise and fast transients. Supply noise can degrade the noise figure, and fast transients can trigger ESD clamps and cause them to fail. Supply voltage change or transients should have a slew rate slower than 1 V/20µs. In addition, all control pin s should remain at 0V (± 0.3V) while the supply voltage ramps up or while it returns to zero. Control Pin Interface If a clean control signal cannot be guaranteed due to overshoot, undershoot, or ringing, etc., the following circuit at the input of the con trol pin is recommended. Figure 13. Control Pin Signal Integrity Improvement Circuit

Figure 16. Electrical Schematic

Table 8. Bill of Material (BOM)

1 Printed Circuit Board F2911EVBI IDT

© 2017 Integrated Device Technology, Inc. 14 Rev O, September 21, 2017 Evaluation Kit (EVKit) Operation External Supply Setup Set up a main power supply in the voltage range of 2.7V to 5.5V with the power supply output disabled. Connect the disabled power supply to J5 pin 1 (VCC) and ground to J5 pin 8 (GND). Logic Control Setup Using the EVKIT to set the control logic: On connector J5, connect a 2 -pin shunt from pin 3 (VCC) to pin 4 (VLOGIC). This connection allows the main power supply to power the EVKit logic control network (R1 and R2). Resistors R1 and R2 form a voltage divider to set the VIH level over the 2.7V to 5.5V supply range for manual logic control. See Table 7 for Switch Control Truth Table states. With the logic control network enabled (as noted above), pin 5 can be left open to pro vide a logic HIGH through pull-up resistor R1. To set a logic LOW for V1, connect a 2-pin shunt on J5 from pin 5 (V1) to pin 6 (GND). Note that when using the on -board R1/ R2 voltage divider, the current draw from the power supply will be higher by approximately the main power supply voltage divided by 33kΩ. Using external control logic: Remove any jumpers from connector J5. Connect the disabled external logic control to V1 (pin 5) of connector J5. See Table 7 for the Switch Control Truth Table settings. Note that even with the R1/R2 divider network disabled, R2 will still be a load (18kΩ to GND) f or an external control signal applied to V1. Turn On Procedure / Operation Setup the supplies and EVKit as noted in the External Supply Setup and Logic Control Setup sections above. Enable the power supply. If using the EVKIT to manually set the control logic: Set the logic setting to achieve the desired Table 7 configuration by placing a shunt between J5 pins 5 and 6 for a logic LOW or leave pins 5 and 6 open for a logic HIGH. If using the external control logic setup above: Enable the logic control signal. Set the logic sig nal level to achieve the desired Table 7 configuration. Note that external control logic should not be applied without the main power supply being present. Turn Off Procedure Set any external logic control to 0V. Disable the main power supply.

Figure 17. Package Outline Drawing – NBG8P3 Package

Figure 18. Recommended Land Pattern – NBG8P3 Package

© 2017 Integrated Device Technology, Inc. 17 Rev O, September 21, 2017 Marking Diagram IDTF29 11NBGP Z412AKG Line 1 and 2 are the part number. Line 3 - “Z” are for die version. Line 3 - “412” is one digit for the year and week that the part was assembled. Line 3 - “AKG” denotes the production process.

Ordering Information

Orderable Part Number Package MSL Rating Shipping Packaging Temperature F2911NBGP 2mm x 2mm x 0.9mm 8-VFQFP-N MSL1 Cut Tape -40°C to +105°C F2911NBGP8 2mm x 2mm x 0.9mm 8-VFQFP-N MSL1 Reel -40°C to +105°C F2911EVBI Evaluation Board

© 2017 Integrated Device Technology, Inc. 18 Rev O, September 21, 2017

Revision History

Revision Revision Date Description of Change Rev O 2017-Sept-21 Initial release. Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 www.IDT.com Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Tech Support www.IDT.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operati ng parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non -infringement of the intellectual property rights of others. This document is presented o nly as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the Uni ted States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For da tasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . All contents of this document are copyright of Integrated Device Technology, Inc. All rights reserved.

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