6259

6259 ALLEGRO

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Data Sheet26186.120 8-BIT ADDRESSABLE DMOS POWER DRIVER The A6259KA and A6259KLW combine a 3-to-8 line CMOS decoder and accompanying data latches, control circuitry, and DMOS outputs in a multi-functional power driver capable of storing single-line data in the addressable latches or use as a decoder or demuliplexer. Driver applications include relays, solenoids, and other medium-current or high-voltage peripheral power loads. The CMOS inputs and latches allow direct interfacing with micro- processor-based systems. Use with TTL may require appropriate pull- up resistors to ensure an input logic high. Four modes of operation are selectable with the CLEAR and ENABLE inputs. The addressed DMOS output inverts the DATA input with all unaddressed outputs remaining in their previous states. All of the output drivers are disabled (the DMOS sink drivers turned off) with the CLEAR input low and the ENABLE input high. The A6259KA/KLW DMOS open-drain outputs are capable of sinking up to 750 mA. Similar devices with reduced r DS(on) are available as the A6A259. The A6259KA is furnished in a 20-pin dual in-line plastic package. The A6259KLW is furnished in a 20-lead wide-body, small-outline plastic package (SOIC) with gull-wing leads for surface-mount applica- tions. Copper lead frames, reduced supply current requirements, and low on-state resistance allow both devices to sink 150 mA from all outputs continuously, to ambient temperatures over 85°C.

FEATURES

I 50 V Minimum Output Clamp Voltage I 250 mA Output Current (all outputs simultaneously) I 1.3 Ω Typical rDS(on) I Low Power Consumption I Replacements for TPIC6259N and TPIC6259DW 6259 ADVANCE INFORMATION (Subject to change without notice) January 24, 2000 Note that the A6259KA (DIP) and the A6259KLW (SOIC) are electrically identical and share a common terminal number assignment. LOGIC GROUND DATAS (LSB) LOGIC SUPPLY V DD POWER GROUND CLEAR OUT 7 OUT 6 OUT 5 Dwg. PP-050-2 OUT 0 OUT 1 OUT 2 OUT 3 OUT 4 10 11 POWER GROUND POWER GROUND ENABLEEN POWER GROUND LATCHES DECODER LOGIC LATCHES S 1 S (MSB)2 ABSOLUTE MAXIMUM RATINGS at TA = 25°C Output Drain Current, Single-Pulse Avalanche Energy, Input Voltage Range, Package Power Dissipation, Operating Temperature Range, Storage Temperature Range, *Each output, all outputs on. † Pulse duration ≤ 100 µs, duty cycle ≤ 2%. Caution: These CMOS devices have input static protection (Class 3) but are still susceptible to damage if exposed to extremely high static electrical charges. Always order by complete part number: Part Number Package R θJA RθJC A6259KA 20-pin DIP 55 °C/W 25 °C/W A6259KLW 20-lead SOIC 70 °C/W 17 °C/W

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 2000, Allegro MicroSystems, Inc. FUNCTION TABLE Inputs Addressed Other CLEAR ENABLE DATA OUTPUT OUTPUTs Function HL H L R Addressable HLL H R Latch H H X R R Memory LL H L H 8-Line LL L H H Demultiplexer L H X H H Clear L = Low Logic Level H = High Logic Level X = Irrelevant R = Previous State LATCH SELECTION TABLE Select Inputs Addressed S2 (MSB)S 1 S0 (LSB) OUTPUT LLL 0 LLH 1 LHL 2 LHH 3 HLL 4 HLH 5 HHL 6 HHH 7 LOGIC SYMBOL 9,0D 10,0R 4 Dwg. FP-046

19 Z10

9,1D 10,1R 9,2D 10,2R 9,3D 10,3R 9,4D 10,4R 9,5D 10,5R 9,6D 10,6R 9,7D 10,7R DMOS POWER DRIVER OUTPUTLOGIC INPUTS 50 75 100 125 150 2.5 0.5 ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS AMBIENT TEMPERATURE IN °C 2.0 1.5 1.0 Dwg. GS-004A SUFFIX 'LW', R = 70 °C/W θJA SUFFIX 'A', R 55°C/W θJA Dw g. EP-063 OUT IN Dwg. EP-010-15 VDD

www.allegromicro.com Grounds (terminals 1, 9, 10, 11, and 20) must be connected externally to a single point. V DD LOGIC SUPPLY POWER GROUND Dwg. FP-047-1 DATA CLEAR (ACTIVE LOW) ENABLE (ACTIVE LOW) OUT 0 D CLR OUT 1 D CLR OUT 2 D CLR OUT 3 D CLR OUT 4 D CLR OUT 5 D CLR OUT 6 D CLR OUT 7 D CLR (MSB) (LSB) LOGIC GROUND FUNCTIONAL BLOCK DIAGRAM

Worcester, Massachusetts 01615-0036 (508) 853-5000 Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units Logic Supply Voltage V DD Operating 4.5 5.0 5.5 V Output Breakdown V (BR)DSX IO = 1 mA 50 — — V Voltage Off-State Output I DSX VO = 40 V — 0.05 1.0 µA Current VO = 40 V, TA = 125°C — 0.15 5.0 µA Static Drain-Source rDS(on) IO = 250 mA, VDD = 4.5 V — 1.3 2.0 Ω On-State Resistance IO = 250 mA, VDD = 4.5 V, TA = 125°C— 2 . 0 3 . 2 Ω IO = 500 mA, VDD = 4.5 V (see note) — 1.3 2.0 Ω Nominal Output I O(nom) VDS(on) = 0.5 V, TA = 85°C — 250 — mA Current Logic Input Current I IH VI = VDD = 5.5 V — — 1.0 µA IIL VI = 0, VDD = 5.5 V — — -1.0 µA Prop. Delay Time t PLH IO = 250 mA, CL = 30 pF — 625 — ns tPHL IO = 250 mA, CL = 30 pF — 140 — ns Output Rise Time t r IO = 250 mA, CL = 30 pF — 650 — ns Output Fall Time t f IO = 250 mA, CL = 30 pF — 400 — ns Supply Current I DD(off) VDD = 5.5 V, Outputs OFF — 15 100 µA IDD(on) VDD = 5.5 V, Outputs ON — 150 300 µA Typical Data is at VDD = 5 V and is for design information only. NOTE — Pulse test, duration ≤ 100 µs, duty cycle ≤ 2%. ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V, tir = tif ≤ 10 ns (unless otherwise specified). RECOMMENDED OPERATING CONDITIONS over operating temperature range

www.allegromicro.com FUNCTIONAL DESCRIPTION and INPUT REQUIREMENTS Four modes of operation are selectable by controlling the CLEAR and ENABLE inputs as shown above. In the addressable-latch mode, data at the DATA input is written into the addressed transparent latch. The addressed output inverts the data input with all other outputs remaining in their previous states. In the memory mode, all outputs remain in their previous states and are unaffected by the DATA or address (S n) inputs. To prevent entering erroneus data in the latches, ENABLE should be held HIGH while the address lines are changing. In the demultiplexing/decoding mode, the addressed output inverts the data input and all other outputs are OFF. In the clear mode, all outputs are OFF and are unaf- fected by the DATA or address (S N) inputs. Given the appropriate inputs, when DATA is LOW for a given address, the output is OFF; when DATA is HIGH, the output is ON and can sink current. 50% Dwg. WP-037 ENABLE DATA 50% w(D)t su(D)t h(D)t PHLtPLHt 50% ADDRESSED OUTPUT Dwg. WP-036 10% 90% ftrt ENABLE DATA OUTPUT SWITCHING TIME DATA INPUT REQUIREMENTS Data Active Time Before Enable Data Active Time After Enable

Worcester, Massachusetts 01615-0036 (508) 853-5000 TEST CIRCUITS Dwg. EP-066-1 OUT INPUT IO VO tav IAS = 1.0 A V(BR)DSX VO(ON) 0.11 Ω100 mH +15 V DUT Single-Pulse Avalanche Energy Test Circuit and Waveforms EAS = IAS x V(BR)DSX x tAV/2

www.allegromicro.com TERMINAL DESCRIPTIONS Terminal No. Terminal Name Function 1 POWER GROUND Reference terminal for output voltage measurements (OUT 0-3). 2 LOGIC SUPPLY (V DD) The logic supply voltage (typically 5 V). 3S 0 Binary-coded output-select input, least-significant bit. 4 OUT 0 Current-sinking, open-drain DMOS output, address 000. 5 OUT 1 Current-sinking, open-drain DMOS output, address 001. 6 OUT 2 Current-sinking, open-drain DMOS output, address 010. 7 OUT 3 Current-sinking, open-drain DMOS output, address 011. 8S 1 Binary-coded output-select input. 9 LOGIC GROUND Reference terminal for input voltage measurements. 10 POWER GROUND Reference terminal for output voltage measurements (OUT 0-3). 11 POWER GROUND Reference terminal for output voltage measurements (OUT 4-7). 12 S 2 Binary-coded output-select input, most-significant bit. 13 ENABLE Mode control input; see Function Table. 14 OUT 4 Current-sinking, open-drain DMOS output, address 100. 15 OUT 5 Current-sinking, open-drain DMOS output, address 101. 16 OUT 6 Current-sinking, open-drain DMOS output, address 110. 17 OUT 7 Current-sinking, open-drain DMOS output, address 111. 18 DATA CMOS data input to the addressed output latch. When enabled, the addressed output inverts the data input (DATA = HIGH, OUTPUT = LOW). 19 CLEAR Mode control input; see Function Table.

20 POWER GROUND Reference terminal for output voltage measurements (OUT

4-7). NOTE — Grounds (terminals 1, 9, 10, 11, and 20) must be connected externally to a single point.

Worcester, Massachusetts 01615-0036 (508) 853-5000 A6259KA Dimensions in Inches (controlling dimensions) Dimensions in Millimeters (for reference only) NOTES:1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. 0.014 0.008 0.300 BSC Dwg. MA-001-20 in 0.430 MAX 1 10 0.280 0.240 0.210 MAX 0.070 0.045 0.015 MIN 0.022 0.014 0.100 BSC 0.005 MIN 0.150 0.115 1.060 0.980 0.355 0.204 7.62 BSC Dwg. MA-001-20 mm 10.92 MAX 1 10 7.11 6.10 5.33 MAX 1.77 1.15 0.39 MIN 0.558 0.356 2.54 BSC 0.13 MIN 3.81 2.93 26.92 24.89

www.allegromicro.com A6259KLW Dimensions in Inches (for reference only) Dimensions in Millimeters (controlling dimensions) 0° TO 8° 1 2 30.020 0.013 0.0040 MIN. 0.0125 0.0091 0.050 0.016 Dwg. MA-008-20 in 0.050 BSC 20 11 0.2992 0.2914 0.419 0.394 0.5118 0.4961 0.0926 0.1043 0° TO 8° 2 30.51 0.33 0.10 MIN. Dwg. MA-008-20 mm 1.27 BSC 0.32 0.23 1.27 0.40 7.60 7.40 10.65 10.00 13.00 12.60 2.65 2.35 NOTES:1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative.

Worcester, Massachusetts 01615-0036 (508) 853-5000 The products described here are manufactured under one or more Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsi- bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.