5T9304PGG

IDT5T9304 Datasheet

Document overview

• Manufacturer or author: Provided By digicamel.com
• PDF pages: 16

Technical content

Features

• Guaranteed low skew: 50ps (maximum)
• Very low duty cycle distortion: 125ps (maximum)
• Propagation delay: 1.75ns (maximum)
• Up to 450MHz operation
• Selectable inputs
• Hot insertable and over-voltage tolerant inputs
• 3.3V/2.5V LVTTL, HSTL eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML or LVDS input interface
• Selectable differential inputs to four LVDS outputs
• 2.5V VDD
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package Pin Assignment 5T9304 24-Lead TSSOP 4.4mm x 7.8mm x 1.0mm package body G Package Top View GND GND PD RESERVED VDD VDD SEL G GND VDD VDD GL

LVDS, 1:4 CLOCK BUFFER TERABUFFER™ 2 Rev A 5/13/15 5T9304 DATA SHEET Block Diagram GL G PD SEL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL

Table 1. Pin Descriptions

1. Inputs are capable of translating the following interface standards:
2. Because the gate controls are asynchronous, runt pulses are po ssible. It is the user's responsibility to either time the gate control

signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry.

1. It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain
2. The user must take precautions with any differential input interface standard being used in order to prevent instability when there is

Table 2. Pin Characteristics (TA = +25°C, F = 1.0MHz)) NOTE: This parameter is measured at characterization but not tested. 1, 12, 22 GND Power Power supply return for all power. 3 RESERVED Reserved Reserved pin. 4, 9, 16, 21 V DD Power Power supply for the device core and inputs. Q4, Q3 Output LVDS Complementary differential clock outputs. Q4, Q3 Output LVDS Differential clock outputs.

11 G Input LVTTL

outputs are asynchronously driven to the level designated by GL(2). 13, 24 A1, A2 Input Adjustable (1, 4) Clock input. A[1:2] is the "true" side of the differential clock input. Complementary clock inputs. A[1:2] is the complementary side of A[1:2].

15 GL Input LVTTL

Rev A 5/13/15 4 LVDS, 1:4 CLOCK BUFFER TERABUFFER™ 5T9304 DATA SHEET Function Tables Table 3A. Gate Control Output Table Table 3B. Input Selection Table Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Recommended Operating Range Control Output Outputs GL G Q[1:4] Q[1:4] 0 0 Toggling Toggling

01 L O W H I G H

11 H I G H L O W

0A 2 , A 2 1A 1 , A 1 Item Rating Power Supply Voltage, VDD -0.5V to +3.6V Input Voltage, VI -0.5V to +3.6V Output Voltage, VO Not to exceed 3.6V -0.5 to VDD +0.5V Storage Temperature, TSTG -65C to 150C Junction Temperature, TJ 150C Symbol Description Minimum Typical Maximum Units TA Ambient Operating Temperature 0 25 70 C VDD Internal Power Supply Voltage 2.3 2.5 2.7 V

LVDS, 1:4 CLOCK BUFFER TERABUFFER™ 5 Rev A 5/13/15 5T9304 DATA SHEET Table 4A. LVDS Power Supply DC Characteristics(1), VDD = 2.5V±0.2V, TA = 0°C to 70°C NOTE 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case conditions. NOTE 2. The true input is held LOW and the complementary input is held HIGH. Table 4B. LVCMOS/LVTTL DC Characteristics(1), VDD = 2.5V±0.2V, TA = 0°C to 70°C NOTE 1. See Recommended Operating Range table. NOTE 2. Typical values are at VDD = 2.5V, +25°C ambient. NOTE 3. For A[1:2] single-ended operation, A[1:2] is tied to a DC reference voltage. Table 4C. Differential DC Characteristics(1), VDD = 2.5V±0.2V, TA = 0°C to 70°C NOTE 1. See Recommended Operating Range table. NOTE 2. Typical values are at VDD = 2.5V, +25°C ambient. NOTE 3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new state. NOTE 4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Symbol Parameter Test Conditions Minimum Typical (2) Maximum Units IDDQ Quiescent VDD Power Supply Current VDD = Max., All Input Clocks = LOW(2); Output enabled 240 mA ITOT Total Power VDD Supply Current VDD = 2.7V; FREFERENCE Clock = 450MHz 250 mA IPD Total Power Down Supply Current PD = LOW 5 mA Symbol Parameter Test Conditions Minimum Typical (2) Maximum Units IIH Input High Current V DD = 2.7V ±5 µA IIL Input Low Current V DD = 2.7V ±5 µA VIK Clamp Diode Voltage V DD = 2.3V, IIN = -18mA -0.7 -1.2 V VIN DC Input Voltage -0.3 3.6 V VIH DC Input High Voltage 1.7 V VIL DC Input Low Voltage 0.7 V VTHI DC Input Threshold Crossing Voltage V DD/2 V VREF Single-Ended Reference Voltage (3) 3.3V LVTTL 1.65 V 2.5V LVTTL 1.25 V Symbol Parameter Test Co nditions Minimum Typical (2) Maximum Units IIH Input High Current V DD = 2.7V ±5 µA IIL Input Low Current V DD = 2.7V ±5 µA VIK Clamp Diode Voltage V DD = 2.3V, IIN = -18mA -0.7 -1.2 V VIN DC Input Voltage -0.3 3.6 V VDIF DC Differential Voltage(3) 0.1 V VCM DC Common Mode Input Voltage(4) 0.05 V DD V

Rev A 5/13/15 6 LVDS, 1:4 CLOCK BUFFER TERABUFFER™ 5T9304 DATA SHEET Table 4D. LVDS DC Characteristics(1), VDD = 2.5V±0.2V, TA = 0°C to 70°C NOTE 1. See Recommended Operating Range table. NOTE 2. Typical values are at VDD = 2.5V, +25°C ambient. Table 5A. HSTL Differential Input AC Characteristics, VDD = 2.5V±0.2V, TA = 0°C to 70°C NOTE 1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification under actual use conditions. NOTE 2. A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under actual use conditions. NOTE 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. NOTE 4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform. Table 5B. eHSTL AC Differential Input Characteristics, VDD = 2.5V±0.2V, TA = 0°C to 70°C NOTE 1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification under actual use conditions. NOTE 2. A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under actual use conditions. NOTE 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. NOTE 4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform. Symbol Parameter Test Conditions Minimum Typical (2) Maximum Units VOT(+) Differential Output Voltage for the True Binary State 247 454 mV VOT(–) Differential Output Voltage for the False Binary State 247 454 mV VOT Change in VOT Between Complementary Output States 50 mV VOS Output Common Mode Voltage (Offset Voltage) 1.125 1.2 1.375 V VOS Change in VOS Between Complementary Output States 50 mV IOS Outputs Short Circuit Current V OUT+ and VOUT– = 0V 12 24 mA IOSD Differential Outputs Short Circuit Current V OUT+ = VOUT– 61 2 m A Symbol Parameter Value Units VDIF Input Signal Swing(1) 1V VX Differential Input Signal Crossing Point(2) 750 mV DH Duty Cycle 50 % VTHI Input Timing Measurement Reference Level(3) Crossing Point V tR / tF Input Signal Edge Rate(4) 2V / n s Symbol Parameter Value Units VDIF Input Signal Swing(1) 1V VX Differential Input Signal Crossing Point(2) 900 mV DH Duty Cycle 50 % VTHI Input Timing Measurement Reference Level(3) Crossing Point V tR / tF Input Signal Edge Rate(4) 2V / n s

LVDS, 1:4 CLOCK BUFFER TERABUFFER™ 7 Rev A 5/13/15 5T9304 DATA SHEET NOTE 1. The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification under actual use conditions. NOTE 2. A 1082mV LVEPECL (2.5V) and 1880mV LVPECL (3.3V) crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under actual use conditions. NOTE 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. NOTE 4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform. Table 5D. LVDS Differential Input AC Characteristics, TA = 0°C to 70°C NOTE 1. The 400mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification under actual use conditions. NOTE 2. A 1.2V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under actual use conditions. NOTE 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. NOTE 4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform. Table 5E. AC Differential Input Characteristics(1), VDD = 2.5V±0.2V, TA = 0°C to 70°C NOTE 1. The output will not change state until the inputs have crossed and the minimum differential voltage range defined by VDIF has been met or exceeded. NOTE 2. VDIF specifies the minimum input voltage (VTR – VCP) required for switching where VTR is the “true” input level and VCP is the “complement” input level. The AC differential voltage must be achieved to guarantee switching to a new state. NOTE 3. VCM specified the maximum allowable range of (VTR + VCP) /2. Symbol Parameter Maximum Units VDIF Input Signal Swing(1) 732 mV VX Differential Input Cross Point Voltage(2) LVEPECL 1082 mV LVPECL 1880 mV DH Duty Cycle 50 % VTHI Input Timing Measurement Reference Level(3) Crossing Point V tR / tF Input Signal Edge Rate(4) 2V / n s Symbol Parameter Maximum Units VDIF Input Signal Swing(1) 400 mV VX Differential Input Cross Point Voltage(2) 1.2 V DH Duty Cycle 50 % VTHI Input Timing Measurement Reference Level(3) Crossing Point V tR / tF Input Signal Edge Rate(4) 2V / n s Symbol Parameter Minimum Typical Maximum Units VDIF AC Differential Voltage(2) 0.1 3.6 V VX Differential Input Cross Point Voltage 0.05 V DD V VCM Common Mode Input Voltage Range(3) 0.05 V DD V VIN Input Voltage -0.3 3.6 V

Rev A 5/13/15 8 LVDS, 1:4 CLOCK BUFFER TERABUFFER™ 5T9304 DATA SHEET Table 5F. AC Characteristics(1,5), VDD = 2.5V±0.2V, TA = 0°C to 70°C NOTE. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1. AC propagation measurements should not be taken within the first 100 cycles of startup. NOTE 2. Skew measured between Crosspoint of all differential output pairs under identical input and output interfaces, transitions and load conditions on any one device. NOTE 3. Skew measured is the difference between propagation delay times tp HL and tpLH of any differential output pair under identical input and output interfaces, transitions and load conditions on any one device. NOTE 4. Skew measured is the magnitude of the difference in propagation times between any single differential output pair of two devices, given identical transitions and load conditions at identical VDD levels and temperature. NOTE 5. All parameters are tested with a 50% input duty cycle. NOTE 6. Guaranteed by design but not production tested. Symbol Parameter Test Conditions Minimum Typical Maximum Units tsk(o) Same Device Output Pin-to-Pin Skew (2) 50 ps tsk(p) Pulse Skew (3) 125 ps tsk(pp) Part-to-Part Skew (4) 300 ps tpLH Propagation Delay, Low-to-High A Crosspoint to Qn, Qn Crosspoint 1.25 1.75 ns tpHL Propagation Delay, High-to-Low 1.25 1.75 ns fo Frequency Range (6) 450 MHz tPGE Output Gate Enable Crossing VTHI-to-Qn/Qn Crosspoint 3.5 ns tPGD Output Gate Enable Crossing VTHI-to-Qn/Qn Crosspoint Driven to Designated Level 3.5 ns tPWRDN PD Crossing VTHI-to-Qn = VDD, Qn = VDD 100 µS tPWRUP Output Gate Disable Crossing VTHI to Qn/Qn Driven to Designated Level 100 µS tR / tF Output Rise/Fall Time(6) 20% to 80% 125 600 ps

LVDS, 1:4 CLOCK BUFFER TERABUFFER™ 9 Rev A 5/13/15 5T9304 DATA SHEET Differential AC Timing Waveforms Output Propagation and Skew Waveforms NOTE 1: Pulse skew is calculated using the following expression: tsk(p) = |tpHL – tpLH| Note that the tpHL and tpLH shown above ae not valid measurements for this calculation because they are not taken from the same pulse. NOTE 2: AC propagation measurements should not be taken within the first 100 cycles of startup. Differential Gate Disabled/Endable Showing Runt Pulse Generation NOTE 1: As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user’s responsibility to time the G signal to avoid this problem. tPLH tPHL tSK(O) tSK(O) Qn - Qn Qm - Qm + VDIF VDIF = 0 - VDIF + VDIF VDIF = 0 - VDIF A[1:2] - A[1:2] + VDIF VDIF = 0 - VDIF 1/fo tPLH GL G Qn - Qn tPGD tPGE VIH VTHI VIL VIH VTHI VIL + VDIF VDIF = 0 - VDIF A[1:2] - A[1:2] + VDIF VDIF = 0 - VDIF

Rev A 5/13/15 10 LVDS, 1:4 CLOCK BUFFER TERABUFFER™ 5T9304 DATA SHEET Power Down Timing NOTE 1: It is recommended that outputs be disabled before entering power-down mode. It is also recommended that the outputs remain disabled until the device completes power-up after asserting PD. NOTE 2: The Power Down Timing diagram assumes that GL is HIGH. NOTE 3: It should be noted that during power-down mode, the outputs are both pulled to VDD. In the Power Down Timing diagram this is shown when Qn/Qn goes to VDIF = 0. A1 - A1 G VTHI VIH VIL Qn - Qn +VDIF VDIF=0 -VDIF +VDIF VDIF=0 -VDIF +VDIF VDIF=0 -VDIF PD A2 - A2 VTHI VIH VIL

LVDS, 1:4 CLOCK BUFFER TERABUFFER™ 11 Rev A 5/13/15 5T9304 DATA SHEET Test Circuit for Differential Input Table 6A. Differential Input Test Conditions Symbol V DD = 2.5V ± 0.2V Unit VTHI Crossing of A and A V VDD/2 D.U.T. A A Pulse Generator ~50Ω Transmission Line ~50Ω Transmission Line VIN VIN -VDD/2 Scope 50Ω 50Ω

Rev A 5/13/15 12 LVDS, 1:4 CLOCK BUFFER TERABUFFER™ 5T9304 DATA SHEET Test Circuit for DC Outputs and Power Down Tests Test Circuit for Propagation, Skew, and Gate Enable/Disable Timing Table 6B. Differential Input Test Conditions NOTE 1: Specifications only apply to “Normal Operations” test condition. The TIA/EIA specification load is for reference only. NOTE 2: The scope inputs are assumed to have a 2pF load to ground. TIA/EIA – 644 specifies 5pF between the output pair. With CL = 8pF , this gives the test circuit appropriate 5pF equivalent load. Symbol V DD = 2.5V ± 0.2V Unit CL 0(1) pF 8(1,2) pF RL 50  VDD D.U.T.A A Qn QnPulse Generator RL RL VOS VOD VDD/2 D.U.T.A A Qn QnPulse Generator 50Ω 50Ω Z = 50Ω Z = 50Ω SCOPE CL -VDD/2 CL

Table 7. Package Dimensions

Rev A 5/13/15 14 LVDS, 1:4 CLOCK BUFFER TERABUFFER™ 5T9304 DATA SHEET

Ordering Information

Table 8. Ordering Information

LVDS, 1:4 CLOCK BUFFER TERABUFFER™ 15 Rev A 5/13/15 5T9304 DATA SHEET Revision History Sheet Rev Table Page Description of Change Date A 1 Not Recommended For New Designs 5/16/13 Updated data sheet format 3/11/15 Removed NRND from the data sheet. 5/13/15

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