5CSXFC5C6U23A7

5CSEBA6U23I7 INTEL

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ID: 683694 Version: 2018.05.07

bandwidth requirements for high-volume and cost-sensitive applications. Lists the planned updates to the Cyclone V Device Handbook chapters. Table 1. Key Advantages of the Cyclone V Device Family

• Up to 40% lower power consumption than the previous generation device Improved logic integration and differentiation capabilities
• 8-input adaptive logic module (ALM)
• Up to 13.59 megabits (Mb) of embedded memory
• Variable-precision digital signal processing (DSP) blocks Increased bandwidth capacity • 3.125 gigabits per second (Gbps) and 6.144 Gbps transceivers
• Hard memory controllers Hard processor system (HPS) with integrated Arm* Cortex*-A9 MPCore* processor
• Tight integration of a dual-core Arm Cortex-A9 MPCore processor, hard IP, and an FPGA in a single Cyclone V system-on-a-chip (SoC)
• Supports over 128 Gbps peak bandwidth with integrated data coherency between the processor and the FPGA fabric Lowest system cost • Requires only two core voltages to operate
• Available in low-cost wirebond packaging
• Includes innovative features such as Configuration via Protocol (CvP) and partial reconfiguration 683694 | 2018.05.07 Send Feedback Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2015 Registered

Table 2. Summary of Features for Cyclone V Devices

• 1.1 V core voltage Packaging • Wirebond low-halogen packages
• Multiple device densities with compatible package footprints for seamless migration between different device densities
• RoHS-compliant and leaded (1)options High-performance FPGA fabric Enhanced 8-input ALM with four registers Internal memory blocks
• M10K—10-kilobits (Kb) memory blocks with soft error correction code (ECC)
• Memory logic array block (MLAB)—640-bit distributed LUTRAM where you can use up to 25% of the ALMs as MLAB memory Embedded Hard IP blocks Variable-precision DSP • Native support for up to three signal processing precision levels (three 9 x 9, two 18 x 18, or one 27 x 27 multiplier) in the same variable-precision DSP block
• 64-bit accumulator and cascade
• Embedded internal coefficient memory
• Preadder/subtractor for improved efficiency Memory controller DDR3, DDR2, and LPDDR2 with 16 and 32 bit ECC support Embedded transceiver I/O PCI Express* (PCIe*) Gen2 and Gen1 (x1, x2, or x4) hard IP with multifunction support, endpoint, and root port Clock networks • Up to 550 MHz global clock network
• Global, quadrant, and peripheral clock networks
• Clock networks that are not used can be powered down to reduce dynamic power Phase-locked loops (PLLs)
• Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB)
• Integer mode and fractional mode FPGA General-purpose I/Os (GPIOs)
• 875 megabits per second (Mbps) LVDS receiver and 840 Mbps LVDS transmitter
• 400 MHz/800 Mbps external memory interface
• On-chip termination (OCT)
• 3.3 V support with up to 16 mA drive strength Low-power high-speed serial interface
• 614 Mbps to 6.144 Gbps integrated transceiver speed
• Transmit pre-emphasis and receiver equalization
• Dynamic partial reconfiguration of individual channels HPS (Cyclone V SE, SX, and ST devices only)
• Single or dual-core Arm Cortex-A9 MPCore processor-up to 925 MHz maximum frequency with support for symmetric and asymmetric multiprocessing
• Interface peripherals—10/100/1000 Ethernet media access control (EMAC), USB 2.0 On-The-GO (OTG) controller, quad serial peripheral interface (QSPI) flash controller, NAND flash controller, Secure Digital/MultiMediaCard (SD/MMC) controller, UART, controller area network (CAN), serial peripheral interface (SPI), I2C interface, and up to 85 HPS GPIO interfaces
• System peripherals—general-purpose timers, watchdog timers, direct memory access (DMA) controller, FPGA configuration manager, and clock and reset managers
• On-chip RAM and boot ROM continued... (1) Contact Intel for availability. Cyclone V Device Overview 683694 | 2018.05.07 Cyclone V Device Overview Send Feedback

• HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight HPS-to-FPGA bridges that allow the FPGA fabric to issue transactions to slaves in the HPS, and vice versa
• FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface to the multiport front end (MPFE) of the HPS SDRAM controller
• Arm CoreSight ™ JTAG debug access port, trace port, and on-chip trace storage Configuration • Tamper protection—comprehensive design protection to protect your valuable IP investments
• Enhanced advanced encryption standard (AES) design security features
• CvP
• Dynamic reconfiguration of the FPGA
• Active serial (AS) x1 and x4, passive serial (PS), JTAG, and fast passive parallel (FPP) x8 and x16 configuration options
• Internal scrubbing (2)
• Partial reconfiguration (3) Cyclone V Device Variants and Packages

Table 3. Device Variants for the Cyclone V Device Family

applications

Cyclone V GT The FPGA industry’s lowest cost and lowest power requirement for 6.144 Gbps transceiver Cyclone V SE SoC with integrated Arm-based HPS Cyclone V SX SoC with integrated Arm-based HPS and 3.125 Gbps transceivers Cyclone V ST SoC with integrated Arm-based HPS and 6.144 Gbps transceivers Cyclone V E This section provides the available options, maximum resource counts, and package plan for the Cyclone V E devices. The information in this section is correct at the time of publication. For the latest information and to get more details, refer to the Product Selector Guide. Related Information Product Selector Guide Provides the latest information about Intel products. (2) The SEU internal scrubbing feature is available for Cyclone V E, GX, SE, and SX devices with the "SC" suffix in the part number. For device availability and ordering, contact your local Intel sales representatives. (3) The partial reconfiguration feature is available for Cyclone V E, GX, SE, and SX devices with the "SC" suffix in the part number. For device availability and ordering, contact your local Intel® sales representatives. Cyclone V Device Overview 683694 | 2018.05.07 Send Feedback Cyclone V Device Overview

Figure 1. Sample Ordering Code and Available Options for Cyclone V E Devices the part number. For device availability and ordering, contact your local Intel sales representatives. Table 4. Maximum Resource Counts for Cyclone V E Devices

Provides the number of LVDS channels in each device package. Table 5. Package Plan for Cyclone V E Devices plan for the Cyclone V GX devices. information and to get more details, refer to the Product Selector Guide. Provides the latest information about Intel products.

Figure 2. Sample Ordering Code and Available Options for Cyclone V GX Devices the part number. For device availability and ordering, contact your local Intel sales representatives. Table 6. Maximum Resource Counts for Cyclone V GX Devices

3 Gbps Transceiver 3 6 6 9 12

the number of user I/Os includes transceiver I/Os.

Provides the number of LVDS channels in each device package. Table 7. Package Plan for Cyclone V GX Devices plan for the Cyclone V GT devices. information and to get more details, refer to the Product Selector Guide. Provides the latest information about Intel products.

Figure 3. Sample Ordering Code and Available Options for Cyclone V GT Devices Table 8. Maximum Resource Counts for Cyclone V GT Devices

6 Gbps Transceiver 6 9 12

the number of user I/Os includes transceiver I/Os.

Provides the number of LVDS channels in each device package. Table 9. Package Plan for Cyclone V GT Devices Cyclone V Device Handbook Volume 2: Transceivers. Provides more information about 6 Gbps transceiver channel count.

plan for the Cyclone V SE devices. information and to get more details, refer to the Product Selector Guide. Provides the latest information about Intel products. Figure 4. Sample Ordering Code and Available Options for Cyclone V SE Devices the part number. For device availability and ordering, contact your local Intel sales representatives. 25K LE and 40K LE, and 20% static power reduction for devices with 85K LE and 110K LE.

Table 10. Maximum Resource Counts for Cyclone V SE Devices Provides the number of LVDS channels in each device package. Table 11. Package Plan for Cyclone V SE Devices I/O pins in the FPGA. Each HPS-specific pin in the FPGA may be mapped to several HPS I/Os.

plan for the Cyclone V SX devices. information and to get more details, refer to the Product Selector Guide. Provides the latest information about Intel products. Figure 5. Sample Ordering Code and Available Options for Cyclone V SX Devices the part number. For device availability and ordering, contact your local Intel sales representatives. 25K LE and 40K LE, and 20% static power reduction for devices with 85K LE and 110K LE. Table 12. Maximum Resource Counts for Cyclone V SX Devices

3 Gbps Transceiver 6 6 9 9

Provides the number of LVDS channels in each device package. Table 13. Package Plan for Cyclone V SX Devices I/O pins in the FPGA. Each HPS-specific pin in the FPGA may be mapped to several HPS I/Os. plan for the Cyclone V ST devices. information and to get more details, refer to the Product Selector Guide. the number of user I/Os includes transceiver I/Os. (9) 1 PCIe Hard IP Block in U672 package.

Provides the latest information about Intel products. Figure 6. Sample Ordering Code and Available Options for Cyclone V ST Devices Table 14. Maximum Resource Counts for Cyclone V ST Devices

6.144 Gbps Transceiver 9 9

the number of user I/Os includes transceiver I/Os.

Provides the number of LVDS channels in each device package. Table 15. Package Plan for Cyclone V ST Devices

• The HPS I/O counts are the number of I/Os in the HPS and does not correlate with the number of HPS- specific I/O pins in the FPGA. Each HPS-specific pin in the FPGA may be mapped to several HPS I/Os.
• Transceiver counts shown are for transceiver ≤5 Gbps . 6 Gbps transceiver channel count support depends on the package and channel usage. For more information about the 6 Gbps transceiver channel count, refer to the Cyclone V Device Handbook Volume 2: Transceivers. Member Code F896 (31 mm) FPGA GPIO HPS I/O XCVR D5 288 181 9 (11) D6 288 181 9 (11) Related Information 6.144-Gbps Support Capability in Cyclone V GT Devices, Cyclone V Device Handbook Volume 2: Transceivers Provides more information about 6 Gbps transceiver channel count. (11) If you require CPRI (at 4.9152 Gbps) and PCIe Gen2 transmit jitter compliance, Intel recommends that you use only up to seven full-duplex transceiver channels for CPRI, and up to six full-duplex channels for PCIe Gen2. The CMU channels are not considered full-duplex channels. Cyclone V Device Overview 683694 | 2018.05.07 Send Feedback Cyclone V Device Overview

Figure 7. Vertical Migration Capability Across Cyclone V Device Packages and Densities have the same dedicated pins, configuration pins, and power pins. are not shown in the Intel Quartus Prime software Pin Migration View. Intel Quartus Prime software Pin Planner. Cyclone V devices use a 28 nm ALM as the basic building block of the logic fabric. and achieve an even higher design packing capability than previous generations.

Figure 8. ALM for Cyclone V Devices Lists the embedded memory capacity for each device.

• Configurable to support signal processing precisions ranging from 9 x 9, 18 x 18 and 27 x 27 bits natively
• A 64-bit accumulator
• A hard preadder that is available in both 18- and 27-bit modes
• Cascaded output adders for efficient systolic finite impulse response (FIR) filters
• Internal coefficient register banks, 8 deep, for each multiplier in 18- or 27-bit mode
• Fully independent multiplier operation
• A second accumulator feedback register to accommodate complex multiply- accumulate functions
• Fully independent Efficient support for single-precision floating point arithmetic
• The inferability of all modes by the Intel Quartus Prime design software Cyclone V Device Overview 683694 | 2018.05.07 Send Feedback Cyclone V Device Overview

Table 16. Variable-Precision DSP Block Configurations for Cyclone V Devices Medium precision fixed point in FIR filters Two 18 x 18 1 FIR filters and general DSP usage Two 18 x 18 with accumulate 1 High precision fixed- or floating-point implementations One 27 x 27 with accumulate 1 You can configure each DSP block during compilation as independent three 9 x 9, two 18 x 18, or one 27 x 27 multipliers. With a dedicated 64 bit cascade bus, you can cascade multiple variable-precision DSP blocks to implement even higher precision DSP functions efficiently. Table 17. Number of Multipliers in Cyclone V Devices The table lists the variable-precision DSP resources by bit precision for each Cyclone V device.

• 10 Kb M10K blocks—blocks of dedicated memory resources. The M10K blocks are ideal for larger memory arrays while still providing a large number of independent ports.
• 640 bit memory logic array blocks (MLABs)—enhanced memory blocks that are configured from dual-purpose logic array blocks (LABs). The MLABs are ideal for wide and shallow memory arrays. The MLABs are optimized for implementation of shift registers for digital signal processing (DSP) applications, wide shallow FIFO buffers, and filter delay lines. Each MLAB is made up of ten adaptive logic modules (ALMs). In the Cyclone V devices, you can configure these ALMs as ten 32 x 2 blocks, giving you one 32 x 20 simple dual-port SRAM block per MLAB. Embedded Memory Capacity in Cyclone V Devices

Table 18. Embedded Memory Capacity and Distribution in Cyclone V Devices

Table 19. Supported Embedded Memory Block Configurations for Cyclone V Devices applicable only to the single-port RAM and ROM modes. 550 MHz Cyclone V devices have 16 global clock networks capable of up to operation. sections of the clock network and powers them down.

The PLLs in the Cyclone V devices support the following features:

• Frequency synthesis
• On-chip clock deskew
• Jitter attenuation
• Programmable output clock duty cycles
• PLL cascading
• Reference clock switchover
• Programmable bandwidth
• User-mode reconfiguration of PLLs
• Low power mode for each fractional PLL
• Dynamic phase shift
• Direct, source synchronous, zero delay buffer, external feedback, and LVDS compensation modes Fractional PLL In addition to integer PLLs, the Cyclone V devices use a fractional PLL architecture. The devices have up to eight PLLs, each with nine output counters. You can use the output counters to reduce PLL usage in two ways:
• Reduce the number of oscillators that are required on your board by using fractional PLLs
• Reduce the number of clock pins that are used in the device by synthesizing multiple clock frequencies from a single reference clock source If you use the fractional PLL mode, you can use the PLLs for precision fractional-N frequency synthesis—removing the need for off-chip reference clock sources in your design. The transceiver fractional PLLs that are not used by the transceiver I/Os can be used as general purpose fractional PLLs by the FPGA fabric. FPGA General Purpose I/O Cyclone V devices offer highly configurable GPIOs. The following list describes the features of the GPIOs:
• Programmable bus hold and weak pull-up
• LVDS output buffer with programmable differential output voltage (V OD ) and programmable pre-emphasis
• On-chip parallel termination (R T OCT) for all I/O banks with OCT calibration to limit the termination impedance variation
• On-chip dynamic termination that has the ability to swap between series and parallel termination, depending on whether there is read or write on a common bus for signal integrity
• Easy timing closure support using the hard read FIFO in the input register path, and delay-locked loop (DLL) delay chain with fine and coarse architecture Cyclone V Device Overview 683694 | 2018.05.07 Send Feedback Cyclone V Device Overview

lane configuration. The PCIe Gen2 x4 support is PCIe-compatible. Figure 9. PCIe Multifunction for Cyclone V Devices datapath protection using ECC. SDRAM devices for maximum flexibility.

Table 20. External Memory Interface Performance in Cyclone V Devices supported delay-locked loop (DLL) frequency listed in the device datasheet. Table 21. HPS External Memory Interface Performance The hard processor system (HPS) is available in Cyclone V SoC devices only. are designed to be compliant with a wide range of protocols and data rates.

Figure 10. Device Chip Overview for Cyclone V GX and GT Devices floorplans than the one shown here. Table 22. PMA Features of the Transceivers in Cyclone V Devices

• No decision feedback equalizer (DFE) Ring oscillator transmit PLLs 614 Mbps to 6.144 Gbps Input reference clock range 20 MHz to 400 MHz Transceiver dynamic reconfiguration Allows the reconfiguration of a single channel without affecting the operation of other channels Cyclone V Device Overview 683694 | 2018.05.07 Cyclone V Device Overview Send Feedback

RapidIO® (SRIO), and Common Public Radio Interface (CPRI). Table 23. Transceiver PCS Features for Cyclone V Devices

• Byte serializer
• 8B/10B encoder
• Transmitter bit-slip
• Word aligner
• Deskew FIFO
• Rate-match FIFO
• 8B/10B decoder
• Byte deserializer
• Byte ordering
• Receiver phase compensation FIFO PCIe Gen1 (x1, x2, x4) 2.5 and 5.0 • Dedicated PCIe PHY IP core
• PIPE 2.0 interface to the core logic
• Dedicated PCIe PHY IP core
• PIPE 2.0 interface to the core logic PCIe Gen2 ( x1, x2, x4)(12) GbE 1.25 • Custom PHY IP core with preset feature
• GbE transmitter synchronization state machine
• Custom PHY IP core with preset feature
• GbE receiver synchronization state machine XAUI (13) 3.125 • Dedicated XAUI PHY IP core
• XAUI synchronization state machine for bonding four channels
• Dedicated XAUI PHY IP core
• XAUI synchronization state machine for realigning four channels HiGig 3.75 SRIO 1.3 and 2.1 1.25 to 3.125 • Custom PHY IP core with preset feature
• SRIO version 2.1-compliant x2 and x4 channel bonding
• Custom PHY IP core with preset feature
• SRIO version 2.1-compliant x2 and x4 deskew state machine SDI, SD/HD, and 3G-SDI 0.27(14), 1.485, and 2.97 Custom PHY IP core with preset feature Custom PHY IP core with preset feature JESD204A 0.3125(15) to 3.125 continued... (12) PCIe Gen2 is supported for Cyclone V GT and ST devices. The PCIe Gen2 x4 support is PCIe-compatible. (13) XAUI is supported through the soft PCS. (14) The 0.27-Gbps data rate is supported using oversampling user logic that you must implement in the FPGA fabric. (15) The 0.3125-Gbps data rate is supported using oversampling user logic that you must implement in the FPGA fabric. Cyclone V Device Overview 683694 | 2018.05.07 Send Feedback Cyclone V Device Overview

(Gbps) Transmitter Data Path Feature Receiver Data Path Feature Serial ATA Gen1 and Gen2 1.5 and 3.0 • Custom PHY IP core with preset feature

• Electrical idle
• Custom PHY IP core with preset feature
• Signal detect
• Wider spread of asynchronous SSC CPRI 4.1(16) 0.6144 to 6.144 • Dedicated deterministic latency PHY IP core
• Transmitter (TX) manual bit-slip mode
• Dedicated deterministic latency PHY IP core
• Receiver (RX) deterministic latency state machine OBSAI RP3 0.768 to 3.072 V-by-One HS Up to 3.75 Custom PHY IP core • Custom PHY IP core
• Wider spread of asynchronous SSCDisplayPort 1.2(17) 1.62 and 2.7 SoC with HPS Each SoC combines an FPGA fabric and an HPS in a single device. This combination delivers the flexibility of programmable logic with the power and cost savings of hard IP in these ways:
• Reduces board space, system power, and bill of materials cost by eliminating a discrete embedded processor
• Allows you to differentiate the end product in both hardware and software, and to support virtually any interface standard
• Extends the product life and revenue through in-field hardware and software updates HPS Features The HPS consists of a dual-core Arm Cortex-A9 MPCore processor, a rich set of peripherals, and a shared multiport SDRAM memory controller, as shown in the following figure. (16) High-voltage output mode (1000-BASE-CX) is not supported. (17) Pending characterization. Cyclone V Device Overview 683694 | 2018.05.07 Cyclone V Device Overview Send Feedback

Figure 11. HPS with Dual-Core Arm Cortex-A9 MPCore Processor

32 KB Instruction Cache,

32 KB Data Cache, and

interface with other devices on your PCB. and supports Arm CoreSight debug and core traces to facilitate software development.

HPS–FPGA AXI Bridges The HPS–FPGA bridges, which support the Advanced Microcontroller Bus Architecture (AMBA®) Advanced eXtensible Interface (AXI™) specifications, consist of the following bridges:

• FPGA-to-HPS AXI bridge—a high-performance bus supporting 32, 64, and 128 bit data widths that allows the FPGA fabric to issue transactions to slaves in the HPS.
• HPS-to-FPGA AXI bridge—a high-performance bus supporting 32, 64, and 128 bit data widths that allows the HPS to issue transactions to slaves in the FPGA fabric.
• Lightweight HPS-to-FPGA AXI bridge—a lower latency 32 bit width bus that allows the HPS to issue transactions to slaves in the FPGA fabric. This bridge is primarily used for control and status register (CSR) accesses to peripherals in the FPGA fabric. The HPS–FPGA AXI bridges allow masters in the FPGA fabric to communicate with slaves in the HPS logic, and vice versa. For example, the HPS-to-FPGA AXI bridge allows you to share memories instantiated in the FPGA fabric with one or both microprocessors in the HPS, while the FPGA-to-HPS AXI bridge allows logic in the FPGA fabric to access the memory and peripherals in the HPS. Each HPS–FPGA bridge also provides asynchronous clock crossing for data transferred between the FPGA fabric and the HPS. HPS SDRAM Controller Subsystem The HPS SDRAM controller subsystem contains a multiport SDRAM controller and DDR PHY that are shared between the FPGA fabric (through the FPGA-to-HPS SDRAM interface), the level 2 (L2) cache, and the level 3 (L3) system interconnect. The FPGA-to-HPS SDRAM interface supports AMBA AXI and Avalon® Memory-Mapped (Avalon-MM) interface standards, and provides up to six individual ports for access by masters implemented in the FPGA fabric. To maximize memory performance, the SDRAM controller subsystem supports command and data reordering, deficit round-robin arbitration with aging, and high-priority bypass features. The SDRAM controller subsystem supports DDR2, DDR3, or LPDDR2 devices up to 4 Gb in density operating at up to 400 MHz (800 Mbps data rate). FPGA Configuration and Processor Booting The FPGA fabric and HPS in the SoC are powered independently. You can reduce the clock frequencies or gate the clocks to reduce dynamic power, or shut down the entire FPGA fabric to reduce total system power. You can configure the FPGA fabric and boot the HPS independently, in any order, providing you with more design flexibility:
• You can boot the HPS independently. After the HPS is running, the HPS can fully or partially reconfigure the FPGA fabric at any time under software control. The HPS can also configure other FPGAs on the board through the FPGA configuration controller.
• You can power up both the HPS and the FPGA fabric together, configure the FPGA fabric first, and then boot the HPS from memory accessible to the FPGA fabric. Cyclone V Device Overview 683694 | 2018.05.07 Cyclone V Device Overview Send Feedback

Note: Although the FPGA fabric and HPS are on separate power domains, the HPS must remain powered up during operation while the FPGA fabric can be powered up or down as required. Related Information Cyclone V Device Family Pin Connection Guidelines Provides detailed information about power supply pin connection guidelines and power regulator sharing. Hardware and Software Development For hardware development, you can configure the HPS and connect your soft logic in the FPGA fabric to the HPS interfaces using the Platform Designer (Standard) system integration tool in the Intel Quartus Prime software. For software development, the Arm-based SoC devices inherit the rich software development ecosystem available for the Arm Cortex-A9 MPCore processor. The software development process for Intel SoCs follows the same steps as those for other SoC devices from other manufacturers. Support for Linux, VxWorks®, and other operating systems is available for the SoCs. For more information on the operating systems support availability, contact the Intel sales team. You can begin device-specific firmware and software development on the Intel SoC Virtual Target. The Virtual Target is a fast PC-based functional simulation of a target development system—a model of a complete development board that runs on a PC. The Virtual Target enables the development of device-specific production software that can run unmodified on actual hardware. Related Information International Altera Sales Support Offices Dynamic and Partial Reconfiguration The Cyclone V devices support dynamic reconfiguration and partial reconfiguration. Dynamic Reconfiguration The dynamic reconfiguration feature allows you to dynamically change the transceiver data rates, PMA settings, or protocols of a channel, without affecting data transfer on adjacent channels. This feature is ideal for applications that require on-the-fly multiprotocol or multirate support. You can reconfigure the PMA and PCS blocks with dynamic reconfiguration. Partial Reconfiguration Note: The partial reconfiguration feature is available for Cyclone V E, GX, SE, and SX devices with the "SC" suffix in the part number. For device availability and ordering, contact your local Intel sales representatives. Partial reconfiguration allows you to reconfigure part of the device while other sections of the device remain operational. This capability is important in systems with critical uptime requirements because it allows you to make updates or adjust functionality without disrupting services. Cyclone V Device Overview 683694 | 2018.05.07 Send Feedback Cyclone V Device Overview

device—saving the board space and reducing the power consumption. the intricate device architecture details to perform a partial reconfiguration. enable simultaneous partial reconfiguration of both the device core and transceivers. several configuration schemes. Table 24. Configuration Schemes and Features Supported by Cyclone V Devices implementation conforms to the PCIe 100 ms power-up-to-active time requirement. Provides more information about CvP.

Leveraging the FPGA architectural features, process technology advancements, and transceivers that are designed for power efficiency, the Cyclone V devices consume less power than previous generation Cyclone FPGAs:

• Total device core power consumption—less by up to 40%.
• Transceiver channel power consumption—less by up to 50%. Additionally, Cyclone V devices contain several hard IP blocks that reduce logic resources and deliver substantial power savings of up to 25% less power than equivalent soft implementations. Document Revision History for Cyclone V Device Overview Document Version Changes 2018.05.07 • Added the low power option ("L" suffix) for Cyclone V SE and Cyclone V SX devices in the Sample Ordering Code and Available Options diagrams.
• Rebranded as Intel. Date Version Changes December 2017 2017.12.18 • Updated ALM resources for Cyclone V E, Cyclone V SE, Cyclone V SX, and Cyclone V ST devices. June 2016 2016.06.10 Updated Cyclone V GT speed grade to –7 in Sample Ordering Code and Available Options for Cyclone V GT Devices diagram. December 2015 2015.12.21 • Added descriptions to package plan tables for Cyclone V GT and ST devices.
• Changed instances of Quartus II to Quartus Prime. June 2015 2015.06.12 • Replaced a note to partial reconfiguration feature. Note: The partial reconfiguration feature is available for Cyclone V E, GX, SE, and SX devices with the "SC" suffix in the part number. For device availability and ordering, contact your local Altera sales representatives.
• Updated logic elements (LE) (K) for the following devices: — Cyclone V E A7: Updated from 149.5 to 150 — Cyclone V GX C3: Updated from 35.5 to 36 — Cyclone V GX C7: Updated from 149.7 to 150 — Cyclone V GT D7: Updated from 149.5 to 150
• Updated MLAB (Kb) in Maximum Resource Counts for Cyclone V GX Devices table as follows: — Cyclone V GX C3: Updated from 291 to 182 — Cyclone V GX C4: Updated from 678 to 424 — Cyclone V GX C5: Updated from 678 to 424 — Cyclone V GX C7: Updated from 1,338 to 836 — Cyclone V GX C9: Updated from 2,748 to 1,717 continued... Cyclone V Device Overview 683694 | 2018.05.07 Send Feedback Cyclone V Device Overview

• Updated MLAB RAM Bit (Kb) in Embedded Memory Capacity and Distribution in Cyclone V Devices table as follows: — Cyclone V GX C3: Updated from 181 to 182 — Cyclone V GX C4: Updated from 295 to 424
• Updated Total RAM Bit (Kb) in Embedded Memory Capacity and Distribution in Cyclone V Devices table as follows: — Cyclone V GX C3: Updated from 1,531 to 1,532 — Cyclone V GX C4: Updated from 2,795 to 2,924
• Updated MLAB Block count in Embedded Memory Capacity and Distribution in Cyclone V Devices table as follows: — Cyclone V GX C4: Updated from 472 to 678 — Cyclone V GX C5: Updated from 679 to 678 March 2015 2015.03.31 • Added internal scrubbing feature under configuration in Summary of Features for Cyclone V Devices table.
• Added optional suffix "SC: Internal scrubbing support" to the following diagrams: — Sample Ordering Code and Available Options for Cyclone V E Devices — Sample Ordering Code and Available Options for Cyclone V GX Devices — Sample Ordering Code and Available Options for Cyclone V SE Devices — Sample Ordering Code and Available Options for Cyclone V SX Devices January 2015 2015.01.23 • Updated Sample Ordering Code and Available Options for Cyclone V ST Devices figure because Cyclone V ST devices are only available in I temperature grade and –7 speed grade. — Operating Temperature: Removed C and A temperature grades — FPGA Fabric Speed Grade: Removed –6 and –8 speed grades
• Updated the transceiver specification for Cyclone V ST from 5 Gbps to

6.144 Gbps:

— Device Variants for the Cyclone V Device Family table — Sample Ordering Code and Available Options for Cyclone V ST Devices figure — Maximum Resource Counts for Cyclone V ST Devices

• Updated Maximum Resource Counts for Cyclone V GX Devices table for Cyclone V GX G3 devices. — Logic elements (LE) (K): Updated from 35.7 to 35.5 — Variable-precision DSP block: Updated from 51 to 57 — 18 x 18 multiplier: Updated from 102 to 114
• Updated Number of Multipliers in Cyclone V Devices table for Cyclone V GX G3 devices. — Variableprecision DSP Block: Updated from 51 to 57 — 9 x 9 Multiplier: Updated from 153 to 171 — 18 x 18 Multiplier: Updated from 102 to 114 — 27 x 27 Multiplier: Updated from 51 to 57 — 18 x 18 Multiplier Adder Mode: Updated from 51 to 57 — 18 x 18 Multiplier Adder Summed with 36 bit Input: Updated from 51 to 57
• Updated Embedded Memory Capacity and Distribution in Cyclone V Devices table for Cyclone V GX G3 devices. — M10K block: Updated from 119 to 135 — M10K RAM bit (Kb): Updated from 1,190 to 1,350 — MLAB block: Updated from 255 to 291 — MLAB RAM bit (Kb): Updated from 159 to 181 — Total RAM bit (Kb): Updated from 1,349 to 1,531 October 2014 2014.10.06 Added a footnote to the "Transceiver PCS Features for Cyclone V Devices" table to show that PCIe Gen2 is supported for Cyclone V GT and ST devices. continued... Cyclone V Device Overview 683694 | 2018.05.07 Cyclone V Device Overview Send Feedback

July 2014 2014.07.07 Updated the I/O vertical migration figure to clarify the migration capability of Cyclone V SE and SX devices. December 2013 2013.12.26 • Corrected single or dual-core ARM Cortex-A9 MPCore processor-up to 925 MHz from 800 MHz.

• Removed "Preliminary" texts from Ordering Code figures, Maximum Resources, Package Plan and I/O Vertical Migration tables.
• Removed the note "The number of GPIOs does not include transceiver I/Os. In the Quartus II software, the number of user I/Os includes transceiver I/Os." for GPIOs in the Maximum Resource Counts table for Cyclone V E and SE.
• Added link to Altera Product Selector for each device variant.
• Updated Embedded Hard IPs for Cyclone V GT devices to indicate Maximum 2 hard PCIe and 2 hard memory controllers.
• Added leaded package options.
• Removed the note "The number of PLLs includes general-purpose fractional PLLs and transceiver fractional PLLs." for all PLLs in the Maximum Resource Counts table.
• Corrected max LVDS counts for transmitter and receiver for Cyclone V E A5 device from 84 to 60.
• Corrected max LVDS counts for transmitter and receiver for Cyclone V E A9 device from 140 to 120.
• Corrected variable-precision DSP block, 27 x 27 multiplier, 18 x 18 multiplier adder mode and 18 x 18 multiplier adder summed with 36 bit input for Cyclone V SE devices from 58 to 84.
• Corrected 18 x 18 multiplier for Cyclone V SE devices from 116 to 168.
• Corrected 9 x 9 multiplier for Cyclone V SE devices from 174 to 252.
• Corrected LVDS transmitter for Cyclone V SE A2 and A4 as well as SX C2 and C4 devices from 31 to 32.
• Corrected LVDS receiver for Cyclone V SE A2 and A4 as well as SX C2 and C4 devices from 35 to 37.
• Corrected transceiver speed grade for Cyclone V ST devices ordering code from 4 to 5.
• Updated the DDR3 SDRAM for the maximum frequency's soft controller and the minimum frequency from 300 to 303 for voltage 1.35V.
• Added links to Altera's External Memory Spec Estimator tool to the topics listing the external memory interface performance.
• Corrected XAUI is supported through the soft PCS in the PCS features for Cyclone V.
• Added decompression support for the CvP configuration mode. May 2013 2013.05.06 • Added link to the known document issues in the Knowledge Base.
• Moved all links to the Related Information section of respective topics for easy reference.
• Corrected the title to the PCIe hard IP topic. Cyclone V devices support only PCIe Gen1 and Gen2.
• Updated Supporting Feature in Table 1 of Increased bandwidth capacity to '6.144 Gbps'.
• Updated Description in Table 2 of Low-power high-speed serial interface to '6.144 Gbps'.
• Updated Description in Table 3 of Cyclone V GT to '6.144 Gbps'.
• Updated the M386 package to M383 for Figure 1, Figure 2 and Figure 3.
• Updated Figure 2 and Figure 3 for Transceiver Count by adding 'F : 4'.
• Updated LVDS in the Maximum Resource Counts tables to include Transmitter and Receiver values.
• Updated the package plan with M383 for the Cyclone V E device.
• Removed the M301 and M383 packages from the Cyclone V GX C4 device.
• Updated the GPIO count to '129' for the M301 package of the Cyclone V GX C5 device.
• Updated 5 Gbps to '6.144 Gbps' forCyclone V GT device. continued... Cyclone V Device Overview 683694 | 2018.05.07 Send Feedback Cyclone V Device Overview

• Updated HPS I/O for U484 (19 mm) in Table 11 with '151' for A2, A4, A5 and A6.
• Updated Memory (Kb) for Maximum Resource Counts for Cyclone V SE A4 and A6, SX C4 and C6, ST D6 devices.
• Updated FPGA PLL for Maximum Resource Counts for Cyclone V SE A2, SX C2, devices.
• Removed '36 x 36' from the Variable-Precision DSP Block.
• Updated Variable-precision DSP Blocks and 18 x 18 Multiplier for Maximum Resource Counts for Cyclone V SX C4 device.
• Updated the HPS I/O counts for Cyclone V SE, SX, and ST devices.
• Updated Figure 7 which shows the I/O vertical migration table.
• Updated Table 17 for Cyclone V SX C4 device.
• Updated Embedded Memory Capacity and Distribution table for Cyclone V SE A4 and A6, SX C4 and C6, ST D6 devices.
• Removed 'Counter reconfiguration' from the PLL Features.
• Updated Low-Power Serial Transceivers by replacing 5 Gbps with 6.144 Gbps.
• Removed 'Distributed Memory' symbol.
• Updated the Capability in Table 22 of Backplane support to '6.144 Gbps'.
• Updated Capability in Table 22 of Ring oscillator transmit PLLs with 6.144 Gbps.
• Updated the PCS Support in Table 23 from 5 Gbps to '6 Gbps'.
• Updated the Data Rates (Gbps) in Table 23 of 3 Gbps and 6 Gbps Basic to '6.144 Gbps'.
• Updated the Data Rates (Gbps) in Table 23 of CPRI 4.1 to '6.144 Gbps'.
• Clarified that partial reconfiguration is an advanced feature. Contact Altera for support of the feature. December 2012 2012.12.28 • Updated the pin counts for the MBGA packages.
• Updated the GPIO and transceiver counts for the MBGA packages.
• Updated the GPIO counts for the U484 package of the Cyclone V E A9, GX C9, and GT D9 devices.
• Updated the vertical migration table for vertical migration of the U484 packages.
• Updated the MLAB supported programmable widths at 32 bits depth. November 2012 2012.11.19 • Added new MBGA packages and additional U484 packages for Cyclone V E, GX, and GT.
• Added ordering code for five-transceiver devices for Cyclone V GT and ST.
• Updated the vertical migration table to add MBGA packages.
• Added performance information for HPS memory controller.
• Removed DDR3U support.
• Updated Cyclone V ST speed grade information.
• Added information on maximum transceiver channel usage restrictions for PCI Gen2 and CPRI at 4.9152 Gbps transmit jitter compliance.
• Added note on the differences between GPIO reported in Overview with User I/O numbers shown in the Quartus II software.
• Updated template. July 2012 2.1 Added support for PCIe Gen2 x4 lane configuration (PCIe-compatible) June 2012 2.0 • Restructured the document.
• Added the “Embedded Memory Capacity” and “Embedded Memory Configurations” sections.
• Added Table 1, Table 3, Table 16, Table 19, and Table 20.
• Updated Table 2, Table 4, Table 5, Table 6, Table 7, Table 8, Table 9, Table 10, Table 11, Table 12, Table 13, Table 14, Table 17, and Table 18. continued... Cyclone V Device Overview 683694 | 2018.05.07 Cyclone V Device Overview Send Feedback

• Updated Figure 1, Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, and Figure 10.
• Updated the “FPGA Configuration and Processor Booting” and “Hardware and Software Development” sections.
• Text edits throughout the document. February 2012 1.2 • Updated Table 1–2, Table 1–3, and Table 1–6.
• Updated “Cyclone V Family Plan” on page 1–4 and “Clock Networks and PLL Clock Sources” on page 1–15.
• Updated Figure 1–1 and Figure 1–6. November 2011 1.1 • Updated Table 1–1, Table 1–2, Table 1–3, Table 1–4, Table 1–5, and Table 1–6.
• Updated Figure 1–4, Figure 1–5, Figure 1–6, Figure 1–7, and Figure 1–8.
• Updated “System Peripherals” on page 1–18, “HPS–FPGA AXI Bridges” on page 1–19, “HPS SDRAM Controller Subsystem” on page 1–19, “FPGA Configuration and Processor Booting” on page 1–19, and “Hardware and Software Development” on page 1–20.
• Minor text edits. October 2011 1.0 Initial release. Cyclone V Device Overview 683694 | 2018.05.07 Send Feedback Cyclone V Device Overview