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Cyclone V Device Datasheet

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Cyclone V Device Datasheet Subscribe Send Feedback CV-51002 | 2019.01.25 Latest document on the web: PDF | HTML

Cyclone V SoC devices are also offered in a low-power variant, as indicated by the L power option in the device part number. equivalent operating conditions and timing specifications as the standard –I7 speed grade devices. Table 1. Low Power Variants *Other names and brands may be claimed as the property of others.

Density Ordering Part Number (OPN) Static Power Reduction 110K LE 5CSEBA6U19I7LN 5CSEBA6U23I7LN 5CSXFC6C6U23I7LN To estimate total power consumption for a low-power device, listed in Table 1 on page 3: 1. Multiply the Total Static Power reported by the Early Power Estimator (EPE) by the appropriate scale factor:

For 25K LE and 40K LE devices, use 0.7
For 85K LE and 110K LE devices, use 0.8 2. Add the result from Step 1 on page 4 to the Total Dynamic Power reported by the EPE. Related Information Cyclone V Device Overview Provides more information about the densities and packages of devices in the Cyclone V family.

Electrical Characteristics

The following sections describe the operating conditions and power consumption of Cyclone V devices. Operating Conditions Cyclone V devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of the Cyclone V devices, you must consider the operating requirements described in this section. Absolute Maximum Ratings This section defines the maximum operating conditions for Cyclone V devices. The values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these conditions. Caution: Conditions outside the range listed in the following table may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device. Cyclone V Device Datasheet CV-51002 | 2019.01.25 Cyclone V Device Datasheet Send Feedback

Table 2. Absolute Maximum Ratings for Cyclone V Devices

currents less than 100 mA and periods shorter than 20 ns. is equivalent to 100% duty cycle. lifetime of 10 years, this amounts to 1.5 years. Table 3. Maximum Allowed Overshoot During Transitions for Cyclone V Devices This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For an overshoot of 3.8 V, the percentage of high time for the overshoot can be as high as 100% over a 10-year period. with 100% I/O toggle rate and 50% duty cycle signal. Figure 1. Cyclone V Devices Overshoot Duration This section lists the functional operation limits for the AC and DC parameters for Cyclone V devices.

Table 4. Recommended Operating Conditions for Cyclone V Devices This table lists the steady-state voltage values expected from Cyclone V devices. Power supply ramps must all be strictly monotonic, without plateaus. requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. device availability and ordering, contact your local Intel sales representatives.

Symbol Description Condition Minimum(2) Typical Maximum(2) Unit VCCPGM Configuration pins power supply 3.3 V 3.135 3.3 3.465 V 3.0 V 2.85 3.0 3.15 V 2.5 V 2.375 2.5 2.625 V 1.8 V 1.71 1.8 1.89 V VCCA_FPLL(5) PLL analog voltage regulator power supply — 2.375 2.5 2.625 V VCCBAT(6) Battery back-up power supply (For design security volatile key register) — 1.2 — 3.0 V VI DC input voltage — –0.5 — 3.6 V VO Output voltage — 0 — VCCIO V TJ Operating junction temperature Commercial 0 — 85 °C Industrial –40 — 100 °C Automotive –40 — 125 °C tRAMP(7) Power supply ramp time Standard POR 200µs — 100ms — Fast POR 200µs — 4ms — (2) The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. (5) PLL digital voltage is regulated from VCCA_FPLL. (6) If you do not use the design security feature in Cyclone V devices, connect VCCBAT to a 1.5-V, 2.5-V, or 3.0-V power supply. Cyclone V power-on reset (POR) circuitry monitors VCCBAT. Cyclone V devices do not exit POR if VCCBAT is not powered up. (7) This is also applicable to HPS power supply. For HPS power supply, refer to tRAMP specifications for standard POR when HPS_PORSEL = 0 and tRAMP specifications for fast POR when HPS_PORSEL = 1. Cyclone V Device Datasheet CV-51002 | 2019.01.25 Send Feedback Cyclone V Device Datasheet

Table 5. Transceiver Power Supply Operating Conditions for Cyclone V GX, GT, SX, and ST Devices

PCIe Supported Configurations and Placement Guidelines Provides more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices which require full compliance to the PCIe Gen2 transmit jitter specification.
6.144-Gbps Support Capability in Cyclone V GT Devices Provides more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices for CPRI 6.144 Gbps. (8) The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. (9) Intel recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for Cyclone V GT and ST FPGA systems which require full compliance to the PCIe Gen2 transmit jitter specification. For more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices under this condition, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter. (10) Intel recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for full compliance to CPRI transmit jitter specification at 4.9152 Gbps (Cyclone V GT and ST devices) and 6.144Gbps (Cyclone V GT and ST devices only). For more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices for CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter. Cyclone V Device Datasheet CV-51002 | 2019.01.25 Cyclone V Device Datasheet Send Feedback

Table 6. HPS Power Supply Operating Conditions for Cyclone V SX and ST Devices steady-state voltage values expected from the FPGA portion of the Cyclone V SoC devices. requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. 3.3 V when VCCIO_HPS is 3.3 V. (13) VCCIO_HPS 1.35 V is supported for HPS row I/O bank only.

Symbol Description Condition Minimum(11) Typical Maximum(11) Unit 1.8 V 1.71 1.8 1.89 V VCCPLL_HPS HPS PLL analog voltage regulator power supply — 2.375 2.5 2.625 V VCC_AUX_SHARED(14) HPS auxiliary power supply — 2.375 2.5 2.625 V Related Information Recommended Operating Conditions on page 8 Provides the steady-state voltage values for the FPGA portion of the device. DC Characteristics Supply Current and Power Consumption Intel offers two ways to estimate power for your design—the Excel-based Early Power Estimator (EPE) and the Intel® Quartus® Prime Power Analyzer feature. Use the Excel-based EPE before you start your design to estimate the supply current for your design. The EPE provides a magnitude estimate of the device power because these currents vary greatly with the resources you use. The Intel Quartus Prime Power Analyzer provides better quality estimates based on the specifics of the design after you complete place-and-route. The Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when combined with detailed circuit models, yields very accurate power estimates. Related Information

Early Power Estimator User Guide Provides more information about power estimation tools.
Power Analysis chapter, Intel Quartus Prime Handbook Provides more information about power estimation tools. (11) The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. (14) VCC_AUX_SHARED must be powered by the same source as VCC_AUX for Cyclone V SX C5, C6, D5, and D6 devices, and Cyclone V SE A5 and A6 devices. Cyclone V Device Datasheet CV-51002 | 2019.01.25 Cyclone V Device Datasheet Send Feedback

Table 7. I/O Pin Leakage Current for Cyclone V Devices Table 8. Bus Hold Parameters for Cyclone V Devices The bus-hold trip points are based on calculated input voltages from the JEDEC* standard.

Table 9. OCT Calibration Accuracy Specifications for Cyclone V Devices Calibration accuracy for the calibrated on-chip series termination (RS OCT) and on-chip parallel termination (RT OCT) are applicable at the moment of calibration. When process, voltage, and temperature (PVT) conditions change after calibration, the tolerance may change.

Table 10. OCT Without Calibration Resistance Tolerance Specifications for Cyclone V Devices This table lists the Cyclone V OCT without calibration resistance tolerance to PVT changes. Figure 2. Equation for OCT Variation Without Recalibration

The R OCT value calculated shows the range of OCT resistance with the variation of temperature and VCCIO.
R SCAL is the OCT resistance value at power-up.
ΔT is the variation of temperature with respect to the temperature at power up. Cyclone V Device Datasheet CV-51002 | 2019.01.25 Send Feedback Cyclone V Device Datasheet

ΔV is the variation of voltage with respect to the V CCIO at power up.
dR/dT is the percentage change of R SCAL with temperature.
dR/dV is the percentage change of R SCAL with voltage. OCT Variation after Power-Up Calibration

Table 11. OCT Variation after Power-Up Calibration for Cyclone V Devices

Table 12. Pin Capacitance for Cyclone V Devices Table 13. Hot Socketing Specifications for Cyclone V Devices All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up.

Table 14. Internal Weak Pull-Up Resistor Values for Cyclone V Devices Provides more information about the pins that support internal weak pull-up and internal weak pull-down features. and IOL) for various I/O standards supported by Cyclone V devices. You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards. (16) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO. (17) Valid with ±10% tolerances to cover changes over PVT.

Table 15. Single-Ended I/O Standards for Cyclone V Devices Table 16. Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Cyclone V Devices IOH specifications in the datasheet.

Table 17. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Cyclone V Devices IOH specifications in the datasheet.

I/O Standard VIL(DC) (V) VIH(DC) (V) VIL(AC) (V) VIH(AC) (V) VOL (V) VOH (V) IOL(19) (mA) IOH(19) (mA) Min Max Min Max Max Min Max Min SSTL-15 Class I SSTL-15 Class II HSTL-18 Class I HSTL-18 Class II HSTL-15 Class I HSTL-15 Class II HSTL-12 Class I HSTL-12 Class II (19) To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the SSTL15CI specification (8 mA), you should set the current strength settings to 8 mA. Setting at lower current strength may not meet the IOL and IOH specifications in the datasheet. Cyclone V Device Datasheet CV-51002 | 2019.01.25 Send Feedback Cyclone V Device Datasheet

Table 18. Differential SSTL I/O Standards for Cyclone V Devices Table 19. Differential HSTL and HSUL I/O Standards for Cyclone V Devices limits (VIH(DC) and VIL(DC)).

Table 20. Differential I/O Standard Specifications for Cyclone V Devices Differential inputs are powered by VCCPD which requires 2.5 V. I/O pin specifications, refer to Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices table.

1.05 DMAX > 700

(21) The minimum VID value is applicable over the entire common mode range, VCM. (23) This applies to default pre-emphasis setting only. Mbps and 0.00 V to 1.85 V for data rate below 700 Mbps. (25) There are no fixed VICM, VOD, and VOCM specifications for BLVDS. They depend on the system topology. (27) For optimized RSDS receiver performance, the receiver voltage input range must be within 0.25 V to 1.45 V. (28) For optimized mini-LVDS receiver performance, the receiver voltage input range must be within 0.300 V to 1.425 V.

I/O Standard VCCIO (V) VID (mV)(21) VICM(DC) (V) VOD (V)(22) VOCM (V)(22)(23) Min Typ Max Min Condition Max Min Condition Max Min Typ Max Min Typ Max LVPECL(29) — — — 300 — — 0.60 DMAX ≤ 700 Mbps

1.00 DMAX > 700

1.60 SLVS 2.375 2.5 2.625 100 VCM = 1.25 V Sub-LVDS 2.375 2.5 2.625 100 VCM = 1.25 V HiSpi 2.375 2.5 2.625 100 VCM = 1.25 V Related Information

AN522: Implementing Bus LVDS Interface in Supported Intel Device Families Provides more information about BLVDS interface support in Intel devices.
Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices on page 25 Provides the specifications for transmitter, receiver, and reference clock I/O pin. Switching Characteristics This section provides performance characteristics of Cyclone V core and periphery blocks. (21) The minimum VID value is applicable over the entire common mode range, VCM. (22) RL range: 90 ≤ RL ≤ 110 Ω. (23) This applies to default pre-emphasis setting only. (29) For optimized LVPECL receiver performance, the receiver voltage input range must be within 0.85 V to 1.75 V for data rate above 700 Mbps and 0.45 V to 1.95 V for data rate below 700 Mbps. Cyclone V Device Datasheet CV-51002 | 2019.01.25 Cyclone V Device Datasheet Send Feedback

Table 21. Reference Clock Specifications for Cyclone V GX, GT, SX, and ST Devices (30) Transceiver Speed Grade 5 covers specifications for Cyclone V GT and ST devices. more information about CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter. (33) REFCLK performance requires to meet transmitter REFCLK phase noise specification.

Symbol/Description Condition Transceiver Speed Grade 5(30) Transceiver Speed Grade 6 Transceiver Speed Grade 7 Unit Min Typ Max Min Typ Max Min Typ Max VICM (AC coupled) — VCCE_GXBL supply(34)(35) VCCE_GXBL supply VCCE_GXBL supply V VICM (DC coupled) HCSL I/O standard for the PCIe reference clock 250 — 550 250 — 550 250 — 550 mV Transmitter REFCLK phase noise(36) RREF — — 2000 ±1% — — 2000 ±1% — — 2000 ±1% — Ω (30) Transceiver Speed Grade 5 covers specifications for Cyclone V GT and ST devices. (34) Intel recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for Cyclone V GT and ST FPGA systems which require full compliance to the PCIe Gen2 transmit jitter specification. For more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices under this condition, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter. (35) Intel recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for full compliance to CPRI transmit jitter specification at 4.9152 Gbps (Cyclone V GT and ST devices) and 6.144 Gbps (Cyclone V GT and ST devices only). For more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices for CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter. (36) The transmitter REFCLK phase jitter is 30 ps p-p at bit error rate (BER) 10-12. Cyclone V Device Datasheet CV-51002 | 2019.01.25 Cyclone V Device Datasheet Send Feedback

Table 22. Transceiver Clocks Specifications for Cyclone V GX, GT, SX, and ST Devices Table 23. Receiver Specifications for Cyclone V GX, GT, SX, and ST Devices (38) To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only. (39) The device cannot tolerate prolonged operation at this absolute maximum.

Symbol/Description Condition Transceiver Speed Grade 5(30) Transceiver Speed Grade 6 Transceiver Speed Grade 7 Unit Min Typ Max Min Typ Max Min Typ Max Minimum differential eye opening at the receiver serial input pins(40) Differential on-chip termination resistors 85-Ω setting — 85 — — 85 — — 85 — Ω 100-Ω setting — 100 — — 100 — — 100 — Ω 120-Ω setting — 120 — — 120 — — 120 — Ω 150-Ω setting — 150 — — 150 — — 150 — Ω VICM (AC coupled) 2.5 V PCML, LVPECL, and LVDS VCCE_GXBL supply(34)(35) VCCE_GXBL supply VCCE_GXBL supply V tLTR_LTD_manual(45) — 15 — — 15 — — 15 — — µs continued... (40) The differential eye opening specification at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you enable the Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. (41) The AC coupled VICM = 650 mV for Cyclone V GX and SX in PCIe mode only. The AC coupled VICM = 750mV for Cyclone V GT and ST in PCIe mode only. (42) tLTR is the time required for the receive clock data recovery (CDR) to lock to the input reference clock frequency after coming out of reset. (43) tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high. (44) tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is functioning in the manual mode. Cyclone V Device Datasheet CV-51002 | 2019.01.25 Cyclone V Device Datasheet Send Feedback

DC Gain for Cyclone V GX, GT, SX, and ST Devices diagrams. Table 24. Transmitter Specifications for Cyclone V GX, GT, SX, and ST Devices high when the CDR is functioning in the manual mode. (46) The rate matcher supports only up to ±300 parts per million (ppm). (47) The Intel Quartus Prime software allows AC gain setting = 3 for design with data rate between 614 Mbps and 1.25 Gbps only.

Table 25. CMU PLL Specifications for Cyclone V GX, GT, SX, and ST Devices Table 26. Transceiver-FPGA Fabric Interface Specifications for Cyclone V GX, GT, SX, and ST Devices

CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain on page 32
CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain on page 33
PCIe Supported Configurations and Placement Guidelines Provides more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices which require full compliance to the PCIe Gen2 transmit jitter specification. Cyclone V Device Datasheet CV-51002 | 2019.01.25 Cyclone V Device Datasheet Send Feedback

6.144-Gbps Support Capability in Cyclone V GT Devices Provides more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices for CPRI 6.144 Gbps. Cyclone V Device Datasheet CV-51002 | 2019.01.25 Send Feedback Cyclone V Device Datasheet

Figure 3. Continuous Time-Linear Equalizer (CTLE) Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC

Figure 4. CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain for Cyclone V GX, GT, SX, and

Table 27. Typical TX VOD Setting for Cyclone V Transceiver Channels with termination of 100 Ω (48) Convert these values to their binary equivalent form if you are using the dynamic reconfiguration mode for PMA analog controls. (49) Only valid for data rates ≤ 5 Gbps.

Symbol VOD Setting(48) VOD Value (mV) VOD Setting(48) VOD Value (mV) 25 500 53 1060 26 520 54 1080 27 540 55 1100 28 560 56 1120 29 580 57 1140 30 600 58 1160 31 620 59 1180 32 640 60 1200 33 660 Transmitter Pre-Emphasis Levels The following table lists the simulation data on the transmitter pre-emphasis levels in dB for the first post tap under the following conditions:

Low-frequency data pattern—five 1s and five 0s
Data rate—2.5 Gbps The levels listed are a representation of possible pre-emphasis levels under the specified conditions only and the pre- emphasis levels may change with data pattern and data rate. Cyclone V devices only support 1st post tap pre-emphasis with the following conditions:
The 1st post tap pre-emphasis settings must satisfy |B| + |C| ≤ 60 where |B| = V OD setting with termination value, RTERM = 100 Ω and |C| = 1st post tap pre-emphasis setting.
|B| – |C| > 5 for data rates < 5 Gbps and |B| – |C| > 8.25 for data rates > 5 Gbps.
(V MAX/VMIN – 1)% < 600%, where VMAX = |B| + |C| and VMIN = |B| – |C|. (48) Convert these values to their binary equivalent form if you are using the dynamic reconfiguration mode for PMA analog controls. Cyclone V Device Datasheet CV-51002 | 2019.01.25 Send Feedback Cyclone V Device Datasheet

V OD setting = 50 and pre-emphasis setting = 22 are allowed for PCIe Gen2 design with transmit de-emphasis –6dB setting (pipe_txdeemp = 1’b0) using Intel PCIe Hard IP and PIPE IP cores.
V OD setting = 50 and pre-emphasis setting = 12 are allowed for PCIe Gen2 design with transmit de-emphasis –3.5dB setting (pipe_txdeemp = 1’b1) using Intel PCIe Hard IP and PIPE IP cores. For example, when VOD = 800 mV, the corresponding VOD value setting is 40. The following conditions show that the 1st post tap pre-emphasis setting = 2 is valid: To predict the pre-emphasis level for your specific data rate and pattern, run simulations using the Cyclone V HSSI HSPICE models.

Table 28. Transmitter Pre-Emphasis Levels for Cyclone V Devices

Intel Quartus Prime VOD Setting Unit 10 (200 mV) 20 (400 mV) 30 (600 mV) 35 (700 mV) 40 (800 mV) 45 (900 mV) 50 (1000 mV) 15 — — 8.87 7.21 6.06 5.14 — dB 16 — — 9.56 7.73 6.49 — — dB 17 — — 10.43 8.39 7.02 — — dB 18 — — 11.23 9.03 7.52 — — dB 19 — — 12.18 9.7 8.02 — — dB 20 — — 13.17 10.34 8.59 — — dB Related Information SPICE Models for Intel Devices Provides the Cyclone V HSSI HSPICE models. Cyclone V Device Datasheet CV-51002 | 2019.01.25 Send Feedback Cyclone V Device Datasheet

contact your Intel Sales Representative. Table 29. Transceiver Compliance Specification for All Supported Protocol for Cyclone V GX, GT, SX, and ST Devices Configurations in Cyclone V Devices chapter.

Protocol Sub-protocol Data Rate (Mbps) CPRI E12LV 1,228.8 CPRI E12HV 1,228.8 CPRI E12LVII 1,228.8 CPRI E24LV 2,457.6 CPRI E24LVII 2,457.6 CPRI E30LV 3,072 CPRI E30LVII 3,072 CPRI E48LVII(51) 4,915.2 CPRI E60LVII(51) 6,144 Gbps Ethernet (GbE) GbE 1250 1,250 OBSAI OBSAI 768 768 OBSAI 1536 1,536 OBSAI 3072 3,072 Serial digital interface (SDI) SDI 270 SD 270 SDI 1485 HD 1,485 SDI 2970 3G 2,970 VbyOne VbyOne 3750 3,750 HiGig+ HIGIG 3750 3,750 Related Information

PCIe Supported Configurations and Placement Guidelines Provides more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices which require full compliance to the PCIe Gen2 transmit jitter specification. (51) For CPRI E48LVII and E60LVII, Intel recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for full compliance to CPRI transmit jitter specification at 4.9152 Gbps (Cyclone V GT and ST devices) and 6.144 Gbps (Cyclone V GT and ST devices only). For more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices for CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter. Cyclone V Device Datasheet CV-51002 | 2019.01.25 Send Feedback Cyclone V Device Datasheet

6.144-Gbps Support Capability in Cyclone V GT Devices Provides more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices for CPRI 6.144 Gbps. Core Performance Specifications Clock Tree Specifications

Table 30. Clock Tree Specifications for Cyclone V Devices Table 31. PLL Specifications for Cyclone V Devices This table lists the Cyclone V PLL block specifications. Cyclone V PLL block does not include HPS PLL. different for each I/O standard.

Symbol Parameter Condition Min Typ Max Unit fVCO(53) PLL voltage-controlled oscillator (VCO) operating range –C6, –C7, –I7 speed grades 600 — 1600 MHz –C8, –A7 speed grades 600 — 1300 MHz tEINDUTY Input clock or external feedback clock input duty cycle — 40 — 60 % fOUT Output frequency for internal global or regional clock –C6, –C7, –I7 speed grades — — 550(54) MHz –C8, –A7 speed grades — — 460(54) MHz fOUT_EXT Output frequency for external clock output –C6, –C7, –I7 speed grades — — 667(54) MHz –C8, –A7 speed grades — — 533(54) MHz tOUTDUTY Duty cycle for external clock output (when set to 50%) — 45 50 55 % tFCOMP External feedback clock compensation time — — — 10 ns tDYCONFIGCLK Dynamic configuration clock for mgmt_clk and scanclk — — — 100 MHz tLOCK Time required to lock from end-of-device configuration or deassertion of areset — — — 1 ms tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post- scale counters/delays) — — — 1 ms fCLBW PLL closed-loop bandwidth Low — 0.3 — MHz Medium — 1.5 — MHz High(55) — 4 — MHz continued... (53) The VCO frequency reported by the Intel Quartus Prime software takes into consideration the VCO post divider value. Therefore, if the VCO post divider value is 2, the frequency reported can be lower than the fVCO specification. (54) This specification is limited by the lower of the two: I/O fMAX or FOUT of the PLL. (55) High bandwidth PLL settings are not supported in external feedback mode. Cyclone V Device Datasheet CV-51002 | 2019.01.25 Send Feedback Cyclone V Device Datasheet

Symbol Parameter Condition Min Typ Max Unit tPLL_PSERR Accuracy of PLL phase shift — — — ±50 ps tARESET Minimum pulse width on the areset signal — 10 — — ns tINCCJ(56)(57) Input clock cycle-to-cycle jitter FREF ≥ 100 MHz — — 0.15 UI (p-p) FREF < 100 MHz — — ±750 ps (p-p) tOUTPJ_DC(58) Period jitter for dedicated clock output in integer PLL FOUT ≥ 100 MHz — — 300 ps (p-p) FOUT < 100 MHz — — 30 mUI (p-p) tFOUTPJ_DC(58) Period jitter for dedicated clock output in fractional PLL FOUT ≥ 100 MHz — — 425(61), 300(59) ps (p-p) FOUT < 100 MHz — — 42.5(61), 30(59) mUI (p-p) tOUTCCJ_DC(58) Cycle-to-cycle jitter for dedicated clock output in integer PLL FOUT ≥ 100 MHz — — 300 ps (p-p) FOUT < 100 MHz — — 30 mUI (p-p) tFOUTCCJ_DC(58) Cycle-to-cycle jitter for dedicated clock output in fractional PLL FOUT ≥ 100 MHz — — 425(61), 300(59) ps (p-p) FOUT < 100 MHz — — 42.5(61), 30(59) mUI (p-p) tOUTPJ_IO(58)(60) Period jitter for clock output on a regular I/O in integer PLL FOUT ≥ 100 MHz — — 650 ps (p-p) FOUT < 100 MHz — — 65 mUI (p-p) continued... (56) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps. (57) FREF is fIN/N, specification applies when N = 1. (58) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a different measurement method and are available in Memory Output Clock Jitter Specification for Cyclone V Devices table. (59) This specification only covers fractional PLL for low bandwidth. The fVCO for fractional value range 0.20–0.80 must be ≥ 1200 MHz. (60) External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter Specification for Cyclone V Devices table. Cyclone V Device Datasheet CV-51002 | 2019.01.25 Cyclone V Device Datasheet Send Feedback

Symbol Parameter Condition Min Typ Max Unit tFOUTPJ_IO(58)(60)(61) Period jitter for clock output on a regular I/O in fractional PLL FOUT ≥ 100 MHz — — 650 ps (p-p) FOUT < 100 MHz — — 65 mUI (p-p) tOUTCCJ_IO(58)(60) Cycle-to-cycle jitter for clock output on regular I/O in integer PLL FOUT ≥ 100 MHz — — 650 ps (p-p) FOUT < 100 MHz — — 65 mUI (p-p) tFOUTCCJ_IO(58)(60)(61) Cycle-to-cycle jitter for clock output on regular I/O in fractional PLL FOUT ≥ 100 MHz — — 650 ps (p-p) FOUT < 100 MHz — — 65 mUI (p-p) tCASC_OUTPJ_DC(58)(62) Period jitter for dedicated clock output in cascaded PLLs FOUT ≥ 100 MHz — — 300 ps (p-p) FOUT < 100 MHz — — 30 mUI (p-p) tDRIFT Frequency drift after PFDENA is disabled for a duration of 100 µs — — — ±10 % dKBIT Bit number of Delta Sigma Modulator (DSM) — 8 24 32 Bits kVALUE Numerator of fraction — 128 8388608 2147483648 — fRES Resolution of VCO frequency fINPFD = 100 MHz 390625 5.96 0.023 Hz Related Information Memory Output Clock Jitter Specifications on page 49 Provides more information about the external memory interface clock output jitter specifications. (61) This specification only covers fractional PLL for low bandwidth. The fVCO for fractional value range 0.05–0.95 must be ≥ 1000 MHz. (62) The cascaded PLL specification is only applicable with the following conditions:

Upstream PLL: 0.59 MHz ≤ Upstream PLL BW < 1 MHz
Downstream PLL: Downstream PLL BW > 2 MHz Cyclone V Device Datasheet CV-51002 | 2019.01.25 Send Feedback Cyclone V Device Datasheet

Table 32. DSP Block Performance Specifications for Cyclone V Devices When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX. Table 33. Memory Block Performance Specifications for Cyclone V Devices

Memory Mode Resources Used Performance Unit ALUTs Memory –C6 –C7, –I7 –C8, –A7 ROM, all supported width 0 1 420 350 300 MHz M10K Block Single-port, all supported widths 0 1 315 275 240 MHz Simple dual-port, all supported widths 0 1 315 275 240 MHz Simple dual-port with the read-during-write option set to Old Data, all supported widths 0 1 275 240 180 MHz True dual port, all supported widths 0 1 315 275 240 MHz ROM, all supported widths 0 1 315 275 240 MHz Periphery Performance This section describes the periphery performance, high-speed I/O, and external memory interface. Actual achievable frequency depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system. Cyclone V Device Datasheet CV-51002 | 2019.01.25 Send Feedback Cyclone V Device Datasheet

Table 34. High-Speed I/O Specifications for Cyclone V Devices When J = 1 or 2, bypass the serializer/deserializer (SERDES) block. For LVDS applications, you must use the PLLs in integer PLL mode. This is achieved by using the LVDS clock network. The Cyclone V devices support the following output standards using true LVDS output buffer types on all I/O banks.

True RSDS output standard with data rates of up to 360 Mbps
True mini-LVDS output standard with data rates of up to 400 Mbps Symbol Condition –C6 –C7, –I7 –C8, –A7 Unit Min Typ Max Min Typ Max Min Typ Max fHSCLK_in (input clock frequency) True Differential I/O Standards Clock boost factor W = 1 to 40(63) 5 — 437.5 5 — 420 5 — 320 MHz fHSCLK_in (input clock frequency) Single-Ended I/O Standards Clock boost factor W = 1 to 40(63) 5 — 320 5 — 320 5 — 275 MHz fHSCLK_OUT (output clock frequency) — 5 — 420 5 — 370 5 — 320 MHz Transmitter True Differential I/O Standards - fHSDR (data rate) SERDES factor J =4 to 10(64) (65) — 840 (65) — 740 (65) — 640 Mbps continued... (63) Clock boost factor (W) is the ratio between the input data rate and the input clock rate. (64) The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain which is design dependent and requires timing analysis. (65) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate. Cyclone V Device Datasheet CV-51002 | 2019.01.25 Cyclone V Device Datasheet Send Feedback

Symbol Condition –C6 –C7, –I7 –C8, –A7 Unit Min Typ Max Min Typ Max Min Typ Max SERDES factor J = 1 to 2, uses DDR registers Emulated Differential I/O Standards with Three External Output Resistor Networks- fHSDR (data rate)(67) SERDES factor J = 4 to 10 (65) — 640 (65) — 640 (65) — 550 Mbps Emulated Differential I/O Standards with One External Output Resistor Network - fHSDR (data rate) SERDES factor J = 4 to 10 (65) — 170 (65) — 170 (65) — 170 Mbps tx Jitter -True Differential I/O Standards(67) Total Jitter for Data Rate, 600 Mbps – 840 Mbps Total Jitter for Data Rate < 600Mbps tx Jitter -Emulated Differential I/O Standards with Three External Output Resistor Networks Total Jitter for Data Rate < 640Mbps tx Jitter -Emulated Differential I/O Standards with One External Output Resistor Network Total Jitter for Data Rate < 640Mbps tDUTY TX output clock duty cycle for both True and 45 50 55 45 50 55 45 50 55 % continued... (66) The maximum ideal data rate is the SERDES factor (J) × PLL max output frequency (fout), provided you can close the design timing and the signal integrity simulation is clean. You can estimate the achievable maximum data rate by performing link timing closure analysis. You must consider the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported. (67) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin. Cyclone V Device Datasheet CV-51002 | 2019.01.25 Send Feedback Cyclone V Device Datasheet

Symbol Condition –C6 –C7, –I7 –C8, –A7 Unit Min Typ Max Min Typ Max Min Typ Max Emulated Differential I/O Standards tRISE and tFALL True Differential I/O Standards Emulated Differential I/O Standards with Three External Output Resistor Networks Emulated Differential I/O Standards with One External Output Resistor Network TCCS True Differential I/O Standards Emulated Differential I/O Standards with Three External Output Resistor Networks Emulated Differential I/O Standards with One External Output Resistor Network Receiver fHSDR (data rate) SERDES factor J =4 to 10(64) SERDES factor J = 1 to 2, uses DDR registers Sampling Window — — — 350 — — 350 — — 350 ps Cyclone V Device Datasheet CV-51002 | 2019.01.25 Cyclone V Device Datasheet Send Feedback

Table 35. DLL Frequency Range Specifications for Cyclone V Devices Table 36. DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) for Cyclone V Devices This error specification is the absolute maximum and minimum error. Table 37. Memory Output Clock Jitter Specifications for Cyclone V Devices The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard. The memory output clock jitter is applicable when an input jitter of 30 ps (p-p) is applied with bit error rate (BER) 10–12, equivalent to 14 sigma. Intel recommends using the UniPHY intellectual property (IP) with PHYCLK connections for better jitter performance.

Table 38. OCT Calibration Block Specifications for Cyclone V Devices Figure 5. Timing Diagram for oe and dyn_term_ctrl Signals

Table 39. Worst-Case DCD on Cyclone V I/O Pins The output DCD cycle only applies to the I/O buffer. It does not cover the system DCD. This section provides HPS specifications and timing for Cyclone V devices. Table 40. HPS Clock Performance for Cyclone V Devices

Table 41. HPS PLL VCO Frequency Range for Cyclone V Devices The HPS PLL input clock range is 10 – 50 MHz. This clock range applies to both HPS_CLK1 and HPS_CLK2 inputs. Provides more information about the clock range for different values of clock select (CSEL). divided by this value. The range of the denominator is 1 to 64. Table 42. Examples of Maximum Input Jitter

Table 43. Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Cyclone V Devices Figure 6. Quad SPI Flash Timing Diagram This timing diagram illustrates clock polarity mode 0 and clock phase mode 0. the Cyclone V Hard Processor System Technical Reference Manual.

Provides more information about Rdelay. Table 44. SPI Master Timing Requirements for Cyclone V Devices The setup and hold times can be used for Texas Instruments SSP mode and National Semiconductor Microwire mode. slower response times from the slave. Note that a delay of 0 is not allowed. The setup time can be used as a reference starting point. Controller chapter in the Hard Processor System Technical Reference Manual.

Figure 7. SPI Master Timing Diagram Table 45. SPI Slave Timing Requirements for Cyclone V Devices The setup and hold times can be used for Texas Instruments SSP mode and National Semiconductor Microwire mode.

Figure 8. SPI Slave Timing Diagram Provides more information about rx_sample_delay.

Table 46. Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Cyclone V Devices SDMMC_CLK is based on the external oscillator frequency and has a maximum value of 50 MHz. maximum of 200 MHz and 50 MHz respectively. (70) drvsel is the drive clock phase shift select value. (71) smplsel is the sample clock phase shift select value.

Figure 9. SD/MMC Timing Diagram Provides more information about CSEL pin settings in the SD/MMC Controller CSEL Pin Settings table. designers use the MicroChip USB3300 PHY device that has been proven to be successful on the development board. Table 47. USB Timing Requirements for Cyclone V Devices

Table 49. RGMII RX Timing Requirements for Cyclone V Devices Figure 12. RGMII RX Timing Diagram Table 50. Management Data Input/Output (MDIO) Timing Requirements for Cyclone V Devices

Figure 13. MDIO Timing Diagram Table 51. I2C Timing Requirements for Cyclone V Devices

Figure 14. I2C Timing Diagram Table 52. NAND ONFI 1.0 Timing Requirements for Cyclone V Devices (72) Timing of the NAND interface is controlled through the NAND configuration registers.

Figure 15. NAND Command Latch Timing Diagram

Figure 16. NAND Address Latch Timing Diagram

Figure 17. NAND Data Write Timing Diagram

Figure 18. NAND Data Read Timing Diagram Table 53. Arm Trace Timing Requirements for Cyclone V Devices Most debugging tools have a mechanism to adjust the capture point of trace data. The maximum UART baud rate is 6.25 megasymbols per second.

The maximum controller area network (CAN) data rate is 1 Mbps. Table 54. HPS JTAG Timing Parameters and Values for Cyclone V Devices This section provides configuration specifications and timing for Cyclone V devices.

Table 55. Fast and Standard POR Delay Specification for Cyclone V Devices Provides more information about POR delay based on MSEL pin settings for each configuration scheme. Table 56. FPGA JTAG Timing Parameters and Values for Cyclone V Devices (74) The maximum pulse width of the fast POR delay is 12 ms, providing enough time for the PCIe hard IP to initialize after the POR trip. (75) The minimum TCK clock period is 167 ns if VCCBAT is within the range 1.2 V – 1.5 V when you perform the volatile key programming.

last data is latched into the Cyclone V device. Table 57. DCLK-to-DATA[] Ratio for Cyclone V Devices 2.5 V, or 14 ns if it equals 1.8 V.

the respective DCLK-to-DATA[] ratio, refer to the DCLK-to-DATA[] Ratio for Cyclone V Devices table. Table 58. FPP Timing Parameters When DCLK-to-DATA[] Ratio is 1 for Cyclone V Devices (77) You can obtain this value if you do not delay configuration by extending the nCONFIG or the nSTATUS low pulse width. (78) You can obtain this value if you do not delay configuration by externally holding the nSTATUS low. (79) If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification.

FPP Configuration Timing Provides the FPP configuration timing waveforms.
DCLK-to-DATA[] Ratio (r) for FPP Configuration on page 69 FPP Configuration Timing when DCLK-to-DATA[] >1

Table 59. FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Cyclone V Devices Use these timing parameters when you use the decompression and design security features. (80) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device. (81) This value can be obtained if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.

Symbol Parameter Minimum Maximum Unit tCF2CK(83) nCONFIG high to first rising edge on DCLK 1506 — µs tST2CK(83) nSTATUS high to first rising edge of DCLK 2 — µs tDSU DATA[] setup time before rising edge on DCLK 5.5 — ns tDH DATA[] hold time after rising edge on DCLK N – 1/fDCLK(84) — s tCH DCLK high time 0.45 × 1/fMAX — s tCL DCLK low time 0.45 × 1/fMAX — s tCLK DCLK period 1/fMAX — s fMAX DCLK frequency (FPP ×8/ ×16) — 125 MHz tR Input rise time — 40 ns tF Input fall time — 40 ns tCD2UM CONF_DONE high to user mode(85) 175 437 µs tCD2CU CONF_DONE high to CLKUSR enabled 4 × maximum DCLK period — — tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (Tinit × CLKUSR period) — — Tinit Number of clock cycles required for device initialization 8,576 — Cycles Related Information FPP Configuration Timing Provides the FPP configuration timing waveforms. (82) This value can be obtained if you do not delay configuration by externally holding nSTATUS low. (83) If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification. (84) N is the DCLK-to-DATA[] ratio and fDCLK is the DCLK frequency of the system. (85) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device. Cyclone V Device Datasheet CV-51002 | 2019.01.25 Cyclone V Device Datasheet Send Feedback

Table 60. AS Timing Parameters for AS ×1 and ×4 Configurations in Cyclone V Devices The minimum and maximum numbers apply to both the internal oscillator and CLKUSR when either one is used as the clock source for device configuration. for Cyclone V Devices table. You can obtain the tCF2ST1 value if you do not delay configuration by externally holding nSTATUS low.

Passive Serial (PS) Configuration Timing on page 74 (86) Load capacitance for DCLK = 6 pF and AS_DATA/ASDO = 8 pF. Intel recommends obtaining the tCO for a given link (including receiver, transmission lines, connectors, termination resistors, and other components) through IBIS or HSPICE simulation. (87) To evaluate the data setup (tSU) and data hold time (tDH) slack on your board in order to ensure you are meeting the tSU and tDH requirement, Intel recommends following the guideline in the "Evaluating Data Setup and Hold Timing Slack" chapter in AN822: Intel FPGA Configuration Device Migration Guideline. (88) Specification for the commercial grade devices. (89) Specification for the industrial and automotive grade devices. Cyclone V Device Datasheet CV-51002 | 2019.01.25 Send Feedback Cyclone V Device Datasheet

AS Configuration Timing Provides the AS configuration timing waveform.
Evaluating Data Setup and Hold Timing Slack chapter, AN822: Intel FPGA Configuration Device Migration Guideline DCLK Frequency Specification in the AS Configuration Scheme

Table 61. DCLK Frequency Specification in the AS Configuration Scheme oscillator as the configuration clock source. The AS multi-device configuration scheme does not support DCLK frequency of 100 MHz. Table 62. PS Timing Parameters for Cyclone V Devices (90) You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. (91) You can obtain this value if you do not delay configuration by externally holding nSTATUS low.

Symbol Parameter Minimum Maximum Unit tST2CK(92) nSTATUS high to first rising edge of DCLK 2 — µs tDSU DATA[] setup time before rising edge on DCLK 5.5 — ns tDH DATA[] hold time after rising edge on DCLK 0 — ns tCH DCLK high time 0.45 × 1/fMAX — s tCL DCLK low time 0.45 × 1/fMAX — s tCLK DCLK period 1/fMAX — s fMAX DCLK frequency — 125 MHz tCD2UM CONF_DONE high to user mode(93) 175 437 µs tCD2CU CONF_DONE high to CLKUSR enabled 4 × maximum DCLK period — — tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (Tinit × CLKUSR period) — — Tinit Number of clock cycles required for device initialization 8,576 — Cycles Related Information PS Configuration Timing Provides the PS configuration timing waveform. (92) If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification. (93) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device. Cyclone V Device Datasheet CV-51002 | 2019.01.25 Send Feedback Cyclone V Device Datasheet

Table 63. Initialization Clock Source Option and the Maximum Frequency for Cyclone V Devices Table 64. Uncompressed .rbf Sizes for Cyclone V Devices format, have different file sizes. software, any design targeted for the same device has the same uncompressed configuration file size. The IOCSR raw binary file (.rbf) size is specifically for the Configuration via Protocol (CvP) feature. Quartus Prime software from the General panel of the Device and Pin Options dialog box. (95) The recommended EPCQ serial configuration devices are able to store more than one image. (96) No PCIe hard IP, configuration via protocol (CvP) is not supported in this family.

Variant Member Code Configuration .rbf Size (bits) IOCSR .rbf Size (bits) Recommended EPCQ Serial Configuration Device(95) A9 102,871,776 400,408 EPCQ256 Cyclone V GX C3 14,510,912 320,280 EPCQ32 C4 33,958,560 322,072 EPCQ128 C5 33,958,560 322,072 EPCQ128 C7 56,167,552 435,288 EPCQ128 C9 102,871,776 400,408 EPCQ256 Cyclone V GT D5 33,958,560 322,072 EPCQ128 D7 56,167,552 435,288 EPCQ128 D9 102,871,776 400,408 EPCQ256 Cyclone V SE (96) A2 33,958,560 322,072 EPCQ128 A4 33,958,560 322,072 EPCQ128 A5 56,057,632 324,888 EPCQ128 A6 56,057,632 324,888 EPCQ128 Cyclone V SX C2 33,958,560 322,072 EPCQ128 C4 33,958,560 322,072 EPCQ128 C5 56,057,632 324,888 EPCQ128 C6 56,057,632 324,888 EPCQ128 Cyclone V ST D5 56,057,632 324,888 EPCQ128 D6 56,057,632 324,888 EPCQ128 (95) The recommended EPCQ serial configuration devices are able to store more than one image. Cyclone V Device Datasheet CV-51002 | 2019.01.25 Send Feedback Cyclone V Device Datasheet

Table 65. Minimum Configuration Time Estimation for Cyclone V Devices The estimated values are based on the configuration .rbf sizes in Uncompressed .rbf Sizes for Cyclone V Devices table. (97) DCLK frequency of 100 MHz using external CLKUSR. (98) Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic.

Table 66. Remote System Upgrade Circuitry Timing Specifications for Cyclone V Devices (97) DCLK frequency of 100 MHz using external CLKUSR. (98) Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic. This is equivalent to strobing the reset timer input of the Remote Update Intel FPGA IP core high for the minimum timing specification.

Remote System Upgrade State Machine Provides more information about configuration reset (RU_CONFIG) signal.
User Watchdog Timer Provides more information about reset_timer (RU_nRSTIMER) signal. User Watchdog Internal Oscillator Frequency Specifications

Table 67. User Watchdog Internal Oscillator Frequency Specifications for Cyclone V Devices Intel offers two ways to determine I/O timing—the Excel-based I/O timing and the Intel Quartus Prime Timing Analyzer. prior to designing the FPGA to get an estimate of the timing budget as part of the link timing analysis. design after you complete place-and-route. Provides the Cyclone V Excel-based I/O timing spreadsheet.

Table 68. I/O element (IOE) Programmable Delay for Cyclone V Devices Table 69. Programmable Output Buffer Delay for Cyclone V Devices This table lists the delay chain settings that control the rising and falling edge delays of the output buffer. positive, negative, or both edges, with the specific values stated here (in ps) for the Output Buffer Delay assignment. Minimum offset does not include the intrinsic delay.

Table 70. Glossary

Positive Channel (p) = VOH Negative Channel (n) = VOL Ground VOD VOD VOD p - n = 0 V VCM fHSCLK Left/right PLL input clock frequency. fHSDR High-speed I/O block—Maximum/minimum LVDS data transfer rate (fHSDR =1/TUI). J High-speed I/O block—Deserialization factor (width of parallel data bus). JTAG timing specifications JTAG Timing Specifications continued... Cyclone V Device Datasheet CV-51002 | 2019.01.25 Send Feedback Cyclone V Device Datasheet

PLL specifications Diagram of PLL specifications continued... Cyclone V Device Datasheet CV-51002 | 2019.01.25 Cyclone V Device Datasheet Send Feedback

External FeedbackReconfigurable in User Mode Legend CLK N PFD Switchover Delta Sigma Modulator VCOCP LF CLKOUT Pins GCLK RCLK Counters C0..C17 Note: (1) Core Clock can only be fed by dedicated clock input pins or PLL outputs. fIN fINPFD fVCO fOUT_EXT fOUT RL Receiver differential input discrete resistor (external to the Cyclone V device). Sampling window (SW) Timing diagram—The period of time during which the data must be valid in order to capture it correctly. The setup and hold times determine the ideal strobe position in the sampling window, as shown: Bit Time 0.5 x TCCS RSKM Sampling Window (SW) RSKM 0.5 x TCCS continued... Cyclone V Device Datasheet CV-51002 | 2019.01.25 Send Feedback Cyclone V Device Datasheet

Single-ended voltage referenced I/O standard The JEDEC standard for the SSTL and HSTL I/O defines both the AC and DC input signal values. The AC values indicate the voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. After the receiver input has crossed the AC value, the receiver changes to the new logic state. The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform ringing. Single-Ended Voltage Referenced I/O Standard VIH (AC ) V IH(DC ) V REF V IL(D C) V IL(AC ) VOH VOL V CCIO V SS tC High-speed receiver/transmitter input and output clock period. TCCS (channel-to-channel-skew) The timing difference between the fastest and slowest output edges, including the tCO variation and clock skew, across channels driven by the same PLL. The clock is included in the TCCS measurement (refer to the Timing Diagram figure under SW in this table). tDUTY High-speed I/O block—Duty cycle on high-speed transmitter output clock. tFALL Signal high-to-low transition time (80–20%) tINCCJ Cycle-to-cycle jitter tolerance on the PLL clock input continued... Cyclone V Device Datasheet CV-51002 | 2019.01.25 Cyclone V Device Datasheet Send Feedback

tOUTPJ_IO Period jitter on the GPIO driven by a PLL tOUTPJ_DC Period jitter on the dedicated clock output driven by a PLL tRISE Signal low-to-high transition time (20–80%) Timing Unit Interval (TUI) The timing budget allowed for skew, propagation delays, and the data sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w) VCM(DC) DC common mode input voltage. VICM Input common mode voltage—The common mode of the differential signal at the receiver. VID Input differential voltage swing—The difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. VDIF(AC) AC differential input voltage—Minimum AC input differential voltage required for switching. VDIF(DC) DC differential input voltage— Minimum DC input differential voltage required for switching. VIH Voltage input high—The minimum positive voltage applied to the input which is accepted by the device as a logic high. VIH(AC) High-level AC input voltage VIH(DC) High-level DC input voltage VIL Voltage input low—The maximum positive voltage applied to the input which is accepted by the device as a logic low. VIL(AC) Low-level AC input voltage VIL(DC) Low-level DC input voltage VOCM Output common mode voltage—The common mode of the differential signal at the transmitter. VOD Output differential voltage swing—The difference in voltage between the positive and complementary conductors of a differential transmission line at the transmitter. VSWING Differential input voltage VX Input differential cross point voltage VOX Output differential cross point voltage W High-speed I/O block—Clock boost factor Cyclone V Device Datasheet CV-51002 | 2019.01.25 Send Feedback Cyclone V Device Datasheet

Document Revision History for Cyclone V Device Datasheet Document Version Changes 2019.01.25 • Changed "VCO post-scale counter K value" to "VCO post divider value" in the fVCO note in the PLL Specifications for Cyclone V Devices table.

Updated the AS Timing Parameters for AS ×1 and ×4 Configurations in Cyclone V Devices table. — Updated tDH specifications. These specifications are applicable to the commercial, industrial, and automotive grade devices. — Added note to tCO and tSU. 2018.05.07 • Added description about the low-power option ("L" suffix) for Cyclone V SE and SX devices.
Added the Cyclone V Devices Overshoot Duration diagram.
Removed the description on SD/MMC interface calibration support in the Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Cyclone V Devices table. This feature is currently supported in the preloader.
Removed the note to Cyclone V SE A2 and A4 devices, and Cyclone V SX C2 and C4 devices in the Uncompressed .rbf Sizes for Cyclone V Devices table. These devices are currently supported in the Intel Quartus Prime software.
Removed PowerPlay text from tool name.
Updated the IP name from ALTREMOTE_UPDATE to Remote Update Intel FPGA IP.
Rebranded as Intel.
Added the Low Power Variants table and the estimating power consumption steps to the "Cyclone V Device Datasheet" Overview section.
Updated the minimum value for t DH to 2.5 for -6 speed grade/2.9 for -7 and -8 speed grade. Date Version Changes December 2016 2016.12.09 • Updated V ICM (AC coupled) specifications for 1.5 V PCML in Receiver Specifications for Cyclone V GX, GT, SX, and ST Devices table.
Added maximum specification for T d in Management Data Input/Output (MDIO) Timing Requirements for Cyclone V Devices table.
Updated T init specifications in the following tables: — FPP Timing Parameters When DCLK-to-DATA[] Ratio is 1 for Cyclone V Devices — FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Cyclone V Devices — AS Timing Parameters for AS ×1 and ×4 Configurations in Cyclone V Devices — PS Timing Parameters for Cyclone V Devices June 2016 2016.06.10 • Changed pin capacitance to maximum values.
Updated SPI Master Timing Requirements for Cyclone V Devices table. — Added Tsu and Th specifications. — Removed Tdinmax specifications.
Updated SPI Master Timing Diagram.
Updated T clk spec from maximum to minimum in I2C Timing Requirements for Cyclone V Devices table. continued... Cyclone V Device Datasheet CV-51002 | 2019.01.25 Cyclone V Device Datasheet Send Feedback

December 2015 2015.12.04 • Updated Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Cyclone V Devices table. — Updated Fclk, Tdutycycle, and Tdssfrst specifications. — Added Tqspi_clk, Tdin_start, and Tdin_end specifications. — Removed Tdinmax specifications.

Updated the minimum specification for T clk to 16.67 ns and removed the maximum specification in SPI Master Timing Requirements for Cyclone V Devices table.
Updated Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Cyclone V Devices table. — Updated T clk to Tsdmmc_clk_out symbol. — Updated Tsdmmc_clk_out and Td specifications. — Added Tsdmmc_clk, Tsu, and Th specifications. — Removed Tdinmax specifications.
Updated the following diagrams: — Quad SPI Flash Timing Diagram — SD/MMC Timing Diagram
Updated configuration .rbf sizes for Cyclone V devices.
Changed instances of Quartus II to Quartus Prime. June 2015 2015.06.12 • Updated the supported data rates for the following output standards using true LVDS output buffer types in the High- Speed I/O Specifications for Cyclone V Devices table: — True RSDS output standard: data rates of up to 360 Mbps — True mini-LVDS output standard: data rates of up to 400 Mbps
Changed Queued Serial Peripheral Interface (QSPI) to Quad Serial Peripheral Interface (SPI) Flash.
Updated T h location in I2C Timing Diagram.
Updated T wp location in NAND Address Latch Timing Diagram.
Updated the maximum value for t CO from 4 ns to 2 ns in AS Timing Parameters for AS ×1 and ×4 Configurations in Cyclone V Devices table.
Moved the following timing diagrams to the Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices chapter. — FPP Configuration Timing Waveform When DCLK-to-DATA[] Ratio is 1 — FPP Configuration Timing Waveform When DCLK-to-DATA[] Ratio is >1 — AS Configuration Timing Waveform — PS Configuration Timing Waveform March 2015 2015.03.31 • Added V CC specifications for devices with internal scrubbing feature (with SC suffix) in Recommended Operating Conditions table.
Corrected the unit for t DH from ns to s in FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Cyclone V Devices table. continued... Cyclone V Device Datasheet CV-51002 | 2019.01.25 Send Feedback Cyclone V Device Datasheet

January 2015 2015.01.23 • Updated the transceiver specification for Cyclone V ST from 5 Gbps to 6.144 Gbps. Updated the note in the following tables: — Transceiver Power Supply Operating Conditions for Cyclone V GX, GT, SX, and ST Devices — Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices — Transceiver Compliance Specification for All Supported Protocol for Cyclone V Devices

Updated the description for V CC_AUX_SHARED to “HPS auxiliary power supply”. Added a note to state that VCC_AUX_SHARED must be powered by the same source as VCC_AUX for Cyclone V SX C5, C6, D5, and D6 devices, and Cyclone V SE A5 and A6 devices. Updated in the following tables: — Absolute Maximum Ratings for Cyclone V Devices — HPS Power Supply Operating Conditions for Cyclone V SE, SX, and ST Devices
Added statement in I/O Standard Specifications: You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.
Updated the conditions for transceiver reference clock rise time and fall time: Measure at ±60 mV of differential signal. Added a note to the conditions: REFCLK performance requires to meet transmitter REFCLK phase noise specification.
Updated f VCO maximum value from 1400 MHz to 1600 MHz for –C7 and –I7 speed grades in the PLL specifications table.
Updated the description in Periphery Performance Specifications to mention that proper timing closure is required in design.
Added the following notes in the High-Speed I/O Specifications for Cyclone V Devices table: — The Cyclone V devices support true RSDS output standard with data rates of up to 230 Mbps using true LVDS output buffer types on all I/O banks. — The Cyclone V devices support true mini-LVDS output standard with data rates of up to 340 Mbps using true LVDS output buffer types on all I/O banks.
Updated HPS Clock Performance main_base_clk specifications from 462 MHz to 400 MHz for –C6 speed grade.
Updated HPS PLL VCO maximum frequency to 1,600 MHz (for –C7, –I7, –A7, and –C8 speed grades) and 1,850 MHz (for – C6 speed grade).
Changed the symbol for HPS PLL input jitter divide value from NR to N.
Removed “Slave select pulse width (Texas Instruments SSP mode)” parameter from the following tables: — SPI Master Timing Requirements for Cyclone V Devices — SPI Slave Timing Requirements for Cyclone V Devices
Added descriptions to USB Timing Characteristics section in HPS Specifications: PHYs that support LPM mode may not function properly with the USB controller due to a timing issue. It is recommended that designers use the MicroChip USB3300 PHY device that has been proven to be successful on the development board.
Added HPS JTAG timing specifications.
Updated the configuration .rbf size (bits) for Cyclone V devices.
Added a note to Uncompressed .rbf Sizes for Cyclone V Devices table: The recommended EPCQ serial configuration devices are able to store more than one image. continued... Cyclone V Device Datasheet CV-51002 | 2019.01.25 Cyclone V Device Datasheet Send Feedback

July 2014 3.9 • Added a note in Table 3, Table 4, and Table 5: The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.

Added a note in Table 19: Differential inputs are powered by V CCPD which requires 2.5 V.
Updated "Minimum differential eye opening at the receiver serial input pins" specification in Table 20.
Updated h2f_user2_clk specification for –C6, –C7, and –I7 speed grades in Table 34.
Updated description in “HPS PLL Specifications” section.
Updated VCO range maximum specification in Table 35.
Updated T d and Th specifications in Table 41.
Added T h specification in Table 43 and Figure 10.
Updated a note in Figure 17, Figure 18, and Figure 20 as follows: Do not leave DCLK floating after configuration. DCLK is ignored after configuration is complete. It can toggle high or low if required.
Removed “Remote update only in AS mode” specification in Table 54.
Added DCLK device initialization clock source specification in Table 56.
Added description in “Configuration Files” section: The IOCSR .rbf size is specifically for the Configuration via Protocol (CvP) feature.
Added "Recommended EPCQ Serial Configuration Device" values in Table 57.
Removed f MAX_RU_CLK specification in Table 59. February 2014 3.8 • Updated V CCRSTCLK_HPS maximum specification in Table 1.
Added V CC_AUX_SHARED specification in Table 1. December 2013 3.7 • Updated Table 1, Table 3, Table 19, Table 20, Table 23, Table 25, Table 27, Table 34, Table 44, Table 51, Table 52, Table 55, and Table 61.
Removed Preliminary tags for Table 1, Table 2, Table 3, Table 4, Table 5, Table 6, Table 7, Table 9, Table 12, Table 13, Table 14, Table 15, Table 16, Table 17, Table 18, Table 19, Table 20, Table 24, Table 25, Table 26, Table 27, Table 28, Table 32, Table 33, Table 49, Table 50, Table 51, Table 52, Table 53, Table 54, Table 55, Table 57, Table 58, Table 59, Table 60, and Table 62. November 2013 3.6 Updated Table 23, Table 30, and Table 31. October 2013 3.5 • Added “HPS PLL Specifications”.
Added Table 23, Table 35, and Table 36.
Updated Table 1, Table 5, Table 11, Table 19, Table 20, Table 21, Table 22, Table 25, Table 28, Table 34, Table 37, Table 38, Table 39, Table 40, Table 41, Table 42, Table 43, Table 44, Table 45, Table 46, Table 47, and Table 53.
Updated Figure 1, Figure 2, Figure 4, Figure 10, Figure 12, Figure 13, and Figure 16.
Removed table: GPIO Pulse Width for Cyclone V Devices. continued... Cyclone V Device Datasheet CV-51002 | 2019.01.25 Send Feedback Cyclone V Device Datasheet

June 2013 3.4 • Updated Table 20, Table 27, and Table 34.

Updated “UART Interface” and “CAN Interface” sections.
Removed the following tables: — Table 45: UART Baud Rate for Cyclone V Devices — Table 47: CAN Pulse Width for Cyclone V Devices May 2013 3.3 • Added Table 33.
Updated Figure 5, Figure 6, Figure 17, Figure 19, and Figure 20.
Updated Table 1, Table 4, Table 5, Table 10, Table 13, Table 19, Table 20, Table 26, Table 32, Table 35, Table 36, Table 43, Table 53, Table 54, Table 57, and Table 61. March 2013 3.2 • Added HPS reset information in the “HPS Specifications” section.
Added Table 57.
Updated Table 1, Table 2, Table 17, Table 20, Table 52, and Table 56.
Updated Figure 18. January 2013 3.1 Updated Table 4, Table 20, and Table 56. November 2012 3.0 • Updated Table 1, Table 4, Table 5, Table 9, Table 14, Table 16, Table 17, Table 19, Table 20, Table 25, Table 28, Table 52, Table 55, Table 56, and Table 59.
Removed table: Transceiver Block Jitter Specifications for Cyclone V GX Devices.
Added HPS information: — Added “HPS Specifications” section. — Added Table 33, Table 34, Table 35, Table 36, Table 37, Table 38, Table 39, Table 40, Table 41, Table 42, Table 43, Table 44, Table 45, and Table 46. — Added Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10, Figure 11, Figure 12, Figure 13, Figure 14, Figure 15, and Figure 16. — Updated Table 3. June 2012 2.0 Updated for the Quartus Prime software v12.0 release:
Restructured document.
Removed “Power Consumption” section.
Updated Table 1,Table 3, Table 19, Table 20, Table 25, Table 27, Table 28, Table 30, Table 31, Table 34, Table 36, Table 37, Table 38, Table 39, Table 41, Table 43, and Table 46.
Added Table 22, Table 23, and Table 29.
Added Figure 1 and Figure 2.
Added “Initialization” and “Configuration Files” sections. continued... Cyclone V Device Datasheet CV-51002 | 2019.01.25 Cyclone V Device Datasheet Send Feedback

February 2012 1.2 • Added automotive speed grade information.

Added Figure 2–1.
Updated Table 2–3, Table 2–8, Table 2–9, Table 2–19, Table 2–20, Table 2–21, Table 2–22, Table 2–23, Table 2–24, Table 2–25, Table 2–26, Table 2–27, Table 2–28, Table 2–30, Table 2–35, and Table 2–43.
Minor text edits. November 2011 1.1 • Added Table 2–5.
Updated Table 2–3, Table 2–4, Table 2–11, Table 2–13, Table 2–20, and Table 2–21. October 2011 1.0 Initial release. Cyclone V Device Datasheet CV-51002 | 2019.01.25 Send Feedback Cyclone V Device Datasheet

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Intel Corporation 5CSEBA6U23A7N overview.

Overview

5CSEBA6U23A7N is listed in the IC category. Available datasheets include documents from Intel Corporation. DigiCamel provides a local PDF and searchable HTML technical text for online reference.

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Cyclone V Device Datasheet

Description

Cyclone V Device Datasheet

Source title 5CSEBA6U23A7N Datasheet(PDF) - Intel Corporation

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