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2013.12.26 CV-51001 Subscribe Send Feedback The Cyclone® V devices are designed to simultaneously accommodate the shrinking power consumption, cost, and time-to-market requirements; and the increasing bandwidth requirements for high-volume and cost-sensitive applications. Enhanced with integrated transceivers and hard memory controllers, the Cyclone V devices are suitable for applications in the industrial, wireless and wireline, military, and automotive markets. Related Information Cyclone V Device Handbook: Known Issues Lists the planned updates to the Cyclone V Device Handbook chapters. Key Advantages of Cyclone V Devices Table 1: Key Advantages of the Cyclone V Device Family Supporting FeatureAdvantage

• Built on TSMC's 28 nm low-power (28LP) process technology and includes an abundance of hard intellectual property (IP) blocks
• Up to 40% lower power consumption than the previous generation device Lower power consumption
• 8-input adaptive logic module (ALM)
• Up to 13.59 megabits (Mb) of embedded memory
• Variable-precision digital signal processing (DSP) blocks Improved logic integration and differentiation capabilities
• 3.125 gigabits per second (Gbps) and 6.144 Gbps transceivers
• Hard memory controllers Increased bandwidth capacity
• Tight integration of a dual-core ARM Cortex-A9 MPCore processor, hard IP, and an FPGA in a single Cyclone V system- on-a-chip (SoC)
• Supports over 128 Gbps peak bandwidth with integrated data coherency between the processor and the FPGA fabric Hard processor system (HPS) with integratedARM® Cortex™-A9 MPCore processor ISO 9001:2008 Registered © 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specificationsbefore relying on any published information and before placing orders for products or services. www.altera.com

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Supporting FeatureAdvantage

• Requires only two core voltages to operate
• Available in low-cost wirebond packaging
• Includes innovative features such as Configuration via Protocol (CvP) and partial reconfiguration Lowest system cost Summary of Cyclone V Features Table 2: Summary of Features for Cyclone V Devices DescriptionFeature
• TSMC's 28-nm low-power (28LP) process technology
• 1.1 V core voltage Technology
• Wirebond low-halogen packages
• Multiple device densities with compatible package footprints for seamless migration between different device densities
• RoHS-compliant and leaded(1)options Packaging Enhanced 8-input ALM with four registersHigh-performanceFPGAfabric
• M10K—10-kilobits (Kb) memory blocks with soft error correction code (ECC)
• Memory logic array block (MLAB)—640-bit distributed LUTRAM where you can use up to 25% of the ALMs as MLAB memory Internal memory blocks
• Native support for up to three signal processing precision levels (three 9 x 9, two 18 x 18, or one 27 x 27 multiplier) in the same variable-precision DSP block
• 64-bit accumulator and cascade
• Embedded internal coefficient memory
• Preadder/subtractor for improved efficiency Variable-precision DSP Embedded Hard IP blocks DDR3, DDR2, and LPDDR2 with 16 and 32 bit ECC support Memory controller PCI Express® (PCIe®) Gen2 and Gen1 (x1, x2, or x4) hard IP with multifunction support, endpoint, and root port Embedded transceiver I/O
• Up to 550 MHz global clock network
• Global, quadrant, and peripheral clock networks
• Clock networks that are not used can be powered down to reduce dynamic power Clock networks (1) Contact Altera for availability. Cyclone V Device OverviewAltera Corporation Send Feedback CV-51001 Summary of Cyclone V Features2 2013.12.26

• Precision clock synthesis,clock delay compensation,and zero delay buffering (ZDB)
• Integer mode and fractional mode Phase-locked loops (PLLs)
• 875 megabits per second (Mbps) LVDS receiver and 840 Mbps LVDS transmitter
• 400 MHz/800 Mbps external memory interface
• On-chip termination (OCT)
• 3.3 V support with up to 16 mA drive strength FPGA General-purpose I/Os (GPIOs)
• 614 Mbps to 6.144 Gbps integrated transceiver speed
• Transmit pre-emphasis and receiver equalization
• Dynamic partial reconfiguration of individual channels Low-power high-speed serial interface
• Single or dual-core ARM Cortex-A9 MPCore processor-up to 925 MHz maximum frequency with support for symmetric and asymmetric multiprocessing
• Interface peripherals—10/100/1000 Ethernet media access control (EMAC), USB 2.0 On-The-GO (OTG) controller, quad serial peripheral interface (QSPI) flash controller, NAND flash controller, Secure Digital/MultiMediaCard (SD/MMC) controller, UART, controller area network (CAN), serial peripheral interface (SPI), I2C interface, and up to 85 HPS GPIO interfaces
• Systemperipherals—general-purposetimers,watchdogtimers,directmemory access (DMA) controller, FPGA configuration manager, and clock and reset managers
• On-chip RAM and boot ROM
• HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight HPS-to-FPGA bridges that allow the FPGA fabric to issue transactions to slaves in the HPS, and vice versa
• FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface to the multiport front end (MPFE) of the HPS SDRAM controller
• ARM CoreSight™ JTAG debug access port, trace port, and on-chip trace storage HPS (Cyclone V SE, SX, and ST devices only)
• Tamper protection—comprehensive design protection to protect your valuable IP investments
• Enhanced advanced encryption standard (AES) design security features
• CvP
• Partial and dynamic reconfiguration of the FPGA
• Activeserial(AS) x1 and x4, passiveserial(PS), JTAG, and fast passiveparallel (FPP) x8 and x16 configuration options Configuration Altera CorporationCyclone V Device Overview Send Feedback 3Summary of Cyclone V Features CV-51001 2013.12.26

Cyclone V Device Variants and Packages Table 3: Device Variants for the Cyclone V Device Family DescriptionVariant Optimizedfor the lowestsystemcost and powerrequirementfor a wide spectrum of general logic and DSP applications Cyclone V E Optimizedfor the lowestcostand powerrequirementfor 614 Mbpsto 3.125Gbps transceiver applications Cyclone V GX The FPGA industry’s lowest cost and lowest power requirement for 6.144 Gbps transceiver applications Cyclone V GT SoC with integrated ARM-based HPSCyclone V SE SoC with integrated ARM-based HPS and 3.125 Gbps transceiversCyclone V SX SoC with integrated ARM-based HPS and 5 Gbps transceiversCyclone V ST Cyclone V E This section provides the available options, maximum resource counts, and package plan for the Cyclone V E devices. The information in this section is correct at the time of publication. For the latest information and to get more details, refer to the Altera Product Selector. Related Information Altera Product Selector Provides the latest information about Altera products. Cyclone V Device OverviewAltera Corporation Send Feedback CV-51001 Cyclone V Device Variants and Packages4 2013.12.26

Figure 1: Sample Ordering Code and Available Options for Cyclone V E Devices Family Signature Embedded Hard IPs Package Type Package Code Operating Temperature FPGA Fabric Speed Grade Optional Suffix Indicates specific device options or shipment method E : Enhancedlogic/memory B : NohardPCIeorhard memorycontroller F : NohardPCIeandmaximum 2hardmemorycontrollers 5C : CycloneV F : FineLineBGA(FBGA) U : UltraFineLineBGA(UBGA) M : MicroFineLineBGA(MBGA) 17 : 256pins 23 : 484pins 27 : 672pins 31 : 896pins 15 : 324pins 19 : 484pins 13 : 383pins 15 : 484pins C : Commercial(TJ =0°Cto85°C) I : Industrial(TJ =-40°Cto100°C) A : Automotive(TJ =-40°Cto125°C) 6(fastest) N : Lead-freepackaging Contact Altera for availability of leaded options ES: Engineeringsample 5C E F A9 F 31 C 7 N Member Code Family Variant A2 : 25Klogicelements A4 : 49Klogicelements A5 : 77Klogicelements A7 : 149.5Klogicelements A9 : 301Klogicelements Maximum Resources Table 4: Maximum Resource Counts for Cyclone V E Devices Member Code Resource A9A7A5A4A2 301149.5774925Logic Elements (LE) (K) 113,56056,48029,08018,4809,434ALM 454,240225,920116,32073,92037,736Register 12,2006,8604,4603,0801,760M10K Memory (Kb) 1,717836424303196MLAB 3421561506625Variable-precision DSP Block 6843123001325018 x 18 Multiplier 87644PLL 480480240224224GPIO 120120605656Transmitter LVDS 120120605656Receiver 22211Hard Memory Controller Altera CorporationCyclone V Device Overview Send Feedback 5Available Options CV-51001 2013.12.26

I/O Features in Cyclone V Devices Provides the number of LVDS channels in each device package. Package Plan Table 5: Package Plan for Cyclone V E Devices F896 (31 mm) F672 (27 mm) F484 (23 mm) U484 (19 mm) F256 (17 mm) U324 (15 mm) M484 (15 mm) M383 (13 mm)Member Code GPIOGPIOGPIOGPIOGPIOGPIOGPIOGPIO ——224224128176—223A2 ——224224128176—223A4 480336240240——240—A7 480336224240————A9 Cyclone V GX Thissectionprovidesthe availableoptions,maximumresourcecounts,and packageplanfor the CycloneV GX devices. The information in this section is correct at the time of publication. For the latest information and to get more details, refer to the Altera Product Selector. Related Information Altera Product Selector Provides the latest information about Altera products. Available Options The following figure shows sample ordering code and lists the options available for Cyclone V GX devices. Cyclone V Device OverviewAltera Corporation Send Feedback CV-51001 Package Plan6 2013.12.26

Figure 2: Sample Ordering Code and Available Options for Cyclone V GX Devices Family Signature Embedded Hard IPs Transceiver Count Transceiver Speed Grade Package Type Package Code Operating Temperature FPGA Fabric Speed Grade Optional Suffix Indicates specific device options or shipment methodGX: 3-Gbpstransceivers B : NohardPCIeorhard memorycontroller F : Maximum2hardPCIeand 2hardmemorycontrollers 5C : CycloneV C3 : 31.5Klogicelements C4 : 50Klogicelements C5 : 77Klogicelements C7 : 149.5Klogicelements C9 : 301Klogicelements B : 3 F : 4 A : 5 C : 6 D : 9 E : 12 6 : 3.125Gbps 7 : 2.5Gbps F : FineLineBGA(FBGA) U : UltraFineLineBGA(UBGA) M : MicroFineLineBGA(MBGA) 23 : 484pins 27 : 672pins 31 : 896pins 35 : 1,152pins 15 : 324pins 19 : 484pins 11 : 301pins 13 : 383pins 15 : 484pins C : Commercial(TJ =0°Cto85°C) I : Industrial(TJ =-40°Cto100°C) A : Automotive(TJ =-40°Cto125°C) 6(fastest) N : Lead-freepackaging Contact Altera for availability of leaded options ES: Engineeringsample 5C GX F C9 E 6 F 35 C 7 N Member Code Family Variant Maximum Resources Table 6: Maximum Resource Counts for Cyclone V GX Devices Member Code Resource C9C7C5C4C3 301149.5775031.5Logic Elements (LE) (K) 113,56056,48029,08018,86811,900ALM 454,240225,920116,32075,47247,600Register 12,2006,8604,4602,5001,190M10K Memory (Kb) 1,717836424295159MLAB 3421561507051Variable-precision DSP Block 68431230014010218 x 18 Multiplier 87664PLL

1296633 Gbps Transceiver

560480336336208GPIO(2) 140120848452Transmitter LVDS 140120848452Receiver (2) The number of GPIOs does not include transceiver I/Os. In the Quartus II software, the number of user I/Os includes transceiver I/Os. Altera CorporationCyclone V Device Overview Send Feedback 7Maximum Resources CV-51001 2013.12.26

22221Hard Memory Controller Related Information I/O Features in Cyclone V Devices Provides the number of LVDS channels in each device package. Package Plan Table 7: Package Plan for Cyclone V GX Devices F1152 (35 mm) F896 (31 mm) F672 (27 mm) F484 (23 mm) U484 (19 mm) U324 (15 mm) M484 (15 mm) M383 (13 mm) M301 (11 mm)Member Code XCVRGPIOXCVRGPIOXCVRGPIOXCVRGPIOXCVRGPIOXCVRGPIOXCVRGPIOXCVRGPIOXCVRGPIO Cyclone V GT Thissectionprovidesthe availableoptions,maximumresourcecounts,and packageplanfor the CycloneV GT devices. The information in this section is correct at the time of publication. For the latest information and to get more details, refer to the Altera Product Selector. Related Information Altera Product Selector Provides the latest information about Altera products. Available Options The following figure shows sample ordering code and lists the options available for Cyclone V GT devices. Cyclone V Device OverviewAltera Corporation Send Feedback CV-51001 Package Plan8 2013.12.26

Figure 3: Sample Ordering Code and Available Options for Cyclone V GT Devices Family Signature Embedded Hard IPs Transceiver Count Transceiver Speed Grade Package Type Package Code Operating Temperature FPGA Fabric Speed Grade GT: 6-Gbpstransceivers F : Maximum2hardPCIeand 2hardmemorycontrollers 5C : CycloneV D5 : 77Klogicelements D7 : 149.5Klogicelements D9 : 301Klogicelements B : 3 F : 4 A : 5 C : 6 D : 9 E : 12 5 : 6.144Gbps F : FineLineBGA(FBGA) U : UltraFineLineBGA(UBGA) M : MicroFineLineBGA(MBGA) 23 : 484pins 27 : 672pins 31 : 896pins 35 : 1,152pins 19 : 484pins 11 : 301pins 13 : 383pins 15 : 484pins C : Commercial(TJ =0°Cto85°C) I : Industrial(TJ =-40°Cto100°C) A : Automotive(TJ =-40°Cto125°C) 6(fastest) 5C GT F D9 E 5 F 35 C 7 N Member Code Family Variant Optional Suffix Indicates specific device options or shipment method N : Lead-freepackaging Contact Altera for availability of leaded options ES: Engineeringsample Maximum Resources Table 8: Maximum Resource Counts for Cyclone V GT Devices Member Code Resource D9D7D5 301149.577Logic Elements (LE) (K) 113,56056,48029,080ALM 454,240225,920116,320Register 12,2006,8604,460M10K Memory (Kb) 1,717836424MLAB 342156150Variable-precision DSP Block 68431230018 x 18 Multiplier 876PLL

12966 Gbps Transceiver

560480336GPIO(3) 14012084Transmitter LVDS 14012084Receiver 222PCIe Hard IP Block (3) The number of GPIOs does not include transceiver I/Os. In the Quartus II software, the number of user I/Os includes transceiver I/Os. Altera CorporationCyclone V Device Overview Send Feedback 9Maximum Resources CV-51001 2013.12.26

I/O Features in Cyclone V Devices Provides the number of LVDS channels in each device package. Package Plan Table 9: Package Plan for Cyclone V GT Devices F1152 (35 mm) F896 (31 mm) F672 (27 mm) F484 (23 mm) U484 (19 mm) M484 (15 mm) M383 (13 mm) M301 (11 mm)Member Code XCVRGPIOXCVRGPIOXCVRGPIOXCVRGPIOXCVRGPIOXCVRGPIOXCVRGPIOXCVRGPIO Cyclone V SE This sectionprovidesthe availableoptions,maximumresourcecounts,and packageplan for the CycloneV SE devices. The information in this section is correct at the time of publication. For the latest information and to get more details, refer to the Altera Product Selector. Related Information Altera Product Selector Provides the latest information about Altera products. Available Options The following figure shows sample ordering code and lists the options available for Cyclone V SE devices. (4) If you require CPRI (at 6.144 Gbps) and PCIe Gen2 transmit jitter compliance, Altera recommends that you use only up to three full-duplex transceiver channels for CPRI, and up to six full-duplex channels for PCIe Gen2. The CMU channels are not considered full-duplex channels. (5) If you require CPRI (at 6.144 Gbps) and PCIe Gen2 transmit jitter compliance, Altera recommends that you use only up to three full-duplex transceiver channels for CPRI, and up to eight full-duplex channels for PCIe Gen2. The CMU channels are not considered full-duplex channels. Cyclone V Device OverviewAltera Corporation Send Feedback CV-51001 Package Plan10 2013.12.26

Figure 4: Sample Ordering Code and Available Options for Cyclone V SE Devices Family Signature Embedded Hard IPs Package Type Package Code Operating Temperature FPGA Fabric Speed Grade Optional Suffix Indicates specific device options or shipment method SE: SoCwithenhancedlogic/memory 5C : CycloneV F : FineLineBGA(FBGA) U : UltraFineLineBGA(UBGA) 31 : 896pins 19 : 484pins 23 : 672pins C : Commercial(TJ =0°Cto85°C) I : Industrial(TJ =-40°Cto100°C) A : Automotive(TJ =-40°Cto125°C) 6(fastest) Processor Cores Omit for dual-core S : Single-core N : Lead-freepackaging Contact Altera for availability of leaded options ES: Engineeringsample 5C SE M A6 F 31 C 6 S N Member Code Family Variant A2 : 25Klogicelements A4 : 40Klogicelements A5 : 85Klogicelements A6 : 110Klogicelements B : NohardPCIeorhard memorycontroller M : NohardPCIeand 1hardmemorycontroller Maximum Resources Table 10: Maximum Resource Counts for Cyclone V SE Devices Member Code Resource A6A5A4A2 110854025Logic Elements (LE) (K) 41,50932,07515,0949,434ALM 166,036128,30060,37637,736Register 5,5703,9702,7001,400M10K Memory (Kb) 621480231138MLAB 112878436Variable-precision DSP Block 2241741687218 x 18 Multiplier 6655FPGA PLL 3333HPS PLL 288288145145FPGA GPIO 181181181181HPS I/O 72723232Transmitter LVDS 72723737Receiver 1111FPGA Hard Memory Controller 1111HPS Hard Memory Controller Single- or dual-coreSingle- or dual- core Single- or dual-core Single- or dual-core ARM Cortex-A9 MPCore Processor Altera CorporationCyclone V Device Overview Send Feedback 11Maximum Resources CV-51001 2013.12.26

I/O Features in Cyclone V Devices Provides the number of LVDS channels in each device package. Package Plan Table 11: Package Plan for Cyclone V SE Devices The HPS I/O counts are the number of I/Os in the HPS and does not correlate with the number of HPS-specific I/O pins in the FPGA. Each HPS-specific pin in the FPGA may be mapped to several HPS I/Os. F896 (31 mm) U672 (23 mm) U484 (19 mm)Member Code HPS I/OFPGA GPIOHPS I/OFPGA GPIOHPS I/OFPGA GPIO ——18114515166A2 ——18114515166A4 18128818114515166A5 18128818114515166A6 Cyclone V SX This sectionprovidesthe availableoptions,maximumresourcecounts,and packageplan for the CycloneV SX devices. The information in this section is correct at the time of publication. For the latest information and to get more details, refer to the Altera Product Selector. Related Information Altera Product Selector Provides the latest information about Altera products. Available Options The following figure shows sample ordering code and lists the options available for Cyclone V SX devices. Cyclone V Device OverviewAltera Corporation Send Feedback CV-51001 Package Plan12 2013.12.26

Figure 5: Sample Ordering Code and Available Options for Cyclone V SX Devices Family Signature Embedded Hard IPs Transceiver Count Transceiver Speed Grade Package Type Package Code Operating Temperature FPGA Fabric Speed Grade Optional Suffix Indicates specific device options or shipment method SX: SoCwith3-Gbpstransceivers F : Maximum2hardPCIe controllersand1hard memorycontroller 5C : CycloneV C2 : 25Klogicelements C4 : 40Klogicelements C5 : 85Klogicelements C6 : 110Klogicelements C : 6 D : 9 6 : 3.125Gbps F : FineLineBGA(FBGA) U : UltraFineLineBGA(UBGA) 31 : 896pins 23 : 672pins C : Commercial(TJ =0°Cto85°C) I : Industrial(TJ =-40°Cto100°C) A : Automotive(TJ =-40°Cto125°C) 6(fastest) N : Lead-freepackaging Contact Altera for availability of leaded options ES: Engineeringsample 5C SX F C6 D 6 F 31 C 6 N Member Code Family Variant Maximum Resources Table 12: Maximum Resource Counts for Cyclone V SX Devices Member Code Resource C6C5C4C2 110854025Logic Elements (LE) (K) 41,50932,07515,0949,434ALM 166,036128,30060,37637,736Register 5,5703,9702,7001,400M10K Memory (Kb) 621480231138MLAB 112878436Variable-precision DSP Block 2241741687218 x 18 Multiplier 6655FPGA PLL 3333HPS PLL

99663 Gbps Transceiver

288288145145FPGA GPIO(6) 181181181181HPS I/O 72723232Transmitter LVDS 72723737Receiver (6) The number of GPIOs does not include transceiver I/Os. In the Quartus II software, the number of user I/Os includes transceiver I/Os. Altera CorporationCyclone V Device Overview Send Feedback 13Maximum Resources CV-51001 2013.12.26

2 (7)2(7)22PCIe Hard IP Block 1111FPGA Hard Memory Controller 1111HPS Hard Memory Controller Dual-coreDual-coreDual-coreDual-coreARM Cortex-A9 MPCore Processor Related Information I/O Features in Cyclone V Devices Provides the number of LVDS channels in each device package. Package Plan Table 13: Package Plan for Cyclone V SX Devices The HPS I/O counts are the number of I/Os in the HPS and does not correlate with the number of HPS-specific I/O pins in the FPGA. Each HPS-specific pin in the FPGA may be mapped to several HPS I/Os. F896 (31 mm) U672 (23 mm)Member Code XCVRHPS I/OFPGA GPIOXCVRHPS I/OFPGA GPIO ———6181145C2 ———6181145C4 91812886181145C5 91812886181145C6 Cyclone V ST This sectionprovidesthe availableoptions,maximumresourcecounts,and packageplan for the CycloneV ST devices. The information in this section is correct at the time of publication. For the latest information and to get more details, refer to the Altera Product Selector. Related Information Altera Product Selector Provides the latest information about Altera products. Available Options The following figure shows sample ordering code and lists the options available for Cyclone V ST devices. (7) 1 PCIe Hard IP Block in U672 package. Cyclone V Device OverviewAltera Corporation Send Feedback CV-51001 Package Plan14 2013.12.26

Figure 6: Sample Ordering Code and Available Options for Cyclone V ST Devices Family Signature Embedded Hard IPs Transceiver Count Transceiver Speed Grade Package Type Package Code Operating Temperature FPGA Fabric Speed Grade Optional Suffix Indicates specific device options or shipment methodST : SoCwith5-Gbpstransceivers F : 2hardPCIecontrollers and1hardmemorycontroller 5C : CycloneV D5 : 85Klogicelements D6 : 110Klogicelements D : 9 5 : 5Gbps F : FineLineBGA(FBGA) 31 : 896pins C : Commercial(TJ =0°Cto85°C) I : Industrial(TJ =-40°Cto100°C) A : Automotive(TJ =-40°Cto125°C) 6(fastest) N : Lead-freepackaging Contact Altera for availability of leaded options ES: Engineeringsample 5C ST F D6 D 5 F 31 C 6 N Member Code Family Variant Maximum Resources Table 14: Maximum Resource Counts for Cyclone V ST Devices Member Code Resource D6D5 11085Logic Elements (LE) (K) 41,50932,075ALM 166,036128,300Register 5,5703,970M10K Memory (Kb) 621480MLAB 11287Variable-precision DSP Block 22417418 x 18 Multiplier 66FPGA PLL 33HPS PLL

995 Gbps Transceiver

288288FPGA GPIO(8) 181181HPS I/O 7272Transmitter LVDS 7272Receiver 22PCIe Hard IP Block 11FPGA Hard Memory Controller (8) The number of GPIOs does not include transceiver I/Os. In the Quartus II software, the number of user I/Os includes transceiver I/Os. Altera CorporationCyclone V Device Overview Send Feedback 15Maximum Resources CV-51001 2013.12.26

11HPS Hard Memory Controller Dual-coreDual-coreARM Cortex-A9 MPCore Processor Related Information I/O Features in Cyclone V Devices Provides the number of LVDS channels in each device package. Package Plan Table 15: Package Plan for Cyclone V ST Devices The HPS I/O counts are the number of I/Os in the HPS and does not correlate with the number of HPS-specific I/O pins in the FPGA. Each HPS-specific pin in the FPGA may be mapped to several HPS I/Os. F896 (31 mm)Member Code XCVRHPS I/OFPGA GPIO 9(9)181288D5 9(9)181288D6 (9) If you require CPRI (at 4.9152 Gbps) and PCIe Gen2 transmit jitter compliance, Altera recommends that you use only up to seven full-duplex transceiver channels for CPRI, and up to six full-duplex channels for PCIe Gen2. The CMU channels are not considered full-duplex channels. Cyclone V Device OverviewAltera Corporation Send Feedback CV-51001 Package Plan16 2013.12.26

I/O Vertical Migration for Cyclone V Devices Figure 7: Vertical Migration Capability Across Cyclone V Device Packages and Densities The arrows indicate the vertical migration paths. The devices included in each vertical migration path are shaded. You can also migrate your design across device densities in the same package option if the devices have the same dedicated pins, configuration pins, and power pins. Variant Member Code Package M301 M383 M484 F256 U324 U484 F484 U672 F672 F896 F1152 CycloneVE CycloneVGX CycloneVGT CycloneVSE CycloneVSX CycloneVST You can achieve the vertical migration shaded in red if you use only up to 175 GPIOs. This migration path is not shown in the Quartus II software Pin Migration View. To verify the pin migration compatibility, use the Pin Migration View window in the Quartus® II software Pin Planner. Note: Adaptive Logic Module Cyclone V devices use a 28 nm ALM as the basic building block of the logic fabric. The ALM, as shown in following figure, uses an 8-input fracturable look-up table (LUT) with four dedicated registers to help improve timing closure in register-rich designs and achieve an even higher design packing capability than previous generations. Altera CorporationCyclone V Device Overview Send Feedback 17I/O Vertical Migration for Cyclone V Devices CV-51001 2013.12.26

Figure 8: ALM for Cyclone V Devices FPGADevice Adaptive LUT Full Adder Reg Reg Full Adder Reg Reg You can configure up to 25% of the ALMs in the Cyclone V devices as distributed memory using MLABs. Related Information Embedded Memory Capacity in Cyclone V Devices on page 20 Lists the embedded memory capacity for each device. Variable-Precision DSP Block Cyclone V devices feature a variable-precision DSP block that supports these features:

• Configurable to support signal processing precisions ranging from 9 x 9, 18 x 18 and 27 x 27 bits natively
• A 64-bit accumulator
• A hard preadder that is available in both 18- and 27-bit modes
• Cascaded output adders for efficient systolic finite impulse response (FIR) filters
• Internal coefficient register banks, 8 deep, for each multiplier in 18- or 27-bit mode
• Fully independent multiplier operation
• A second accumulator feedback register to accommodate complex multiply-accumulate functions
• Efficient support for single-precision floating point arithmetic
• The inferability of all modes by the Quartus II design software Table 16: Variable-Precision DSP Block Configurations for Cyclone V Devices DSP Block ResourceMultiplier Size (Bit)Usage Example 1Three 9 x 9Low precision fixed point for video

applications

1Two 18 x 18Medium precision fixed point in FIR filters 1Two 18 x 18 with accumulate FIR filters and general DSP usage Cyclone V Device OverviewAltera Corporation Send Feedback CV-51001 Variable-Precision DSP Block18 2013.12.26

DSP Block ResourceMultiplier Size (Bit)Usage Example 1One 27 x 27 with accumulate High precision fixed- or floating-point implementations You can configure each DSP block during compilation as independent three 9 x 9, two 18 x 18, or one 27 x 27 multipliers. With a dedicated 64 bit cascade bus, you can cascade multiple variable-precision DSP blocks to implement even higher precision DSP functions efficiently. Table 17: Number of Multipliers in Cyclone V Devices The table lists the variable-precision DSP resources by bit precision for each Cyclone V device. 18 x 18 Multiplier Adder Summed with 36 bit Input 18 x 18 Multiplier Adder Mode Independent Input and Output Multiplications OperatorVariable- precision DSP Block Member CodeVariant 27 x 27 Multiplier 18 x 18 Multiplier 9 x 9 Multiplier 252525507525A2 Cyclone V E 66666613219866A4 150150150300450150A5 156156156312468156A7 3423423426841,026342A9 51515110215351C3 Cyclone V GX 70707014021070C4 150150150300450150C5 156156156312468156C7 3423423426841,026342C9 150150150300450150D5 Cyclone V GT 156156156312468156D7 3423423426841,026342D9 3636367210836A2 Cyclone V SE 84848416825284A4 87878717426187A5 112112112224336112A6 3636367210836C2 Cyclone V SX 84848416825284C4 87878717426187C5 112112112224336112C6 Altera CorporationCyclone V Device Overview Send Feedback 19Variable-Precision DSP Block CV-51001 2013.12.26

Independent Input and Output Multiplications OperatorVariable- precision DSP Block Member CodeVariant 27 x 27 Multiplier 18 x 18 Multiplier 9 x 9 Multiplier 87878717426187D5 Cyclone V ST 112112112224336112D6 Embedded Memory Blocks The embedded memory blocks in the devices are flexible and designed to provide an optimal amount of small- and large-sized memory arrays to fit your design requirements. Types of Embedded Memory The Cyclone V devices contain two types of memory blocks:

• 10 Kb M10K blocks—blocksof dedicatedmemoryresources.The M10K blocksare idealfor largermemory arrays while still providing a large number of independent ports.
• 640 bit memory logic array blocks (MLABs)—enhanced memory blocks that are configured from dual- purposelogic array blocks (LABs).The MLABs are ideal for wide and shallowmemory arrays.The MLABs are optimized for implementation of shift registers for digital signal processing (DSP) applications, wide shallow FIFO buffers, and filter delay lines. Each MLAB is made up of ten adaptive logic modules (ALMs). In the Cyclone V devices, you can configure these ALMs as ten 32 x 2 blocks, giving you one 32 x 20 simple dual-port SRAM block per MLAB. Embedded Memory Capacity in Cyclone V Devices Table 18: Embedded Memory Capacity and Distribution in Cyclone V Devices Total RAM Bit (Kb) MLABM10KMember CodeVariant RAM Bit (Kb)BlockRAM Bit (Kb)Block 1,9561963141,760176A2 Cyclone V E 3,3833034853,080308A4 4,8844246794,460446A5 7,69683613386,860686A7 13,9171,717274812,2001,220A9 1,3491592551,190119C3 Cyclone V GX 2,7952954722,500250C4 4,8844246794,460446C5 7,69683613386,860686C7 13,9171,717274812,2001,220C9 Cyclone V Device OverviewAltera Corporation Send Feedback CV-51001 Embedded Memory Blocks20 2013.12.26

Total RAM Bit (Kb) MLABM10KMember CodeVariant RAM Bit (Kb)BlockRAM Bit (Kb)Block 4,8844246794,460446D5 Cyclone V GT 7,69683613386,860686D7 13,9171,717274812,2001,220D9 1,5381382211,400140A2 Cyclone V SE 2,4602313702,700270A4 4,4504807683,970397A5 5,7616219945,570557A6 1,5381382211,400140C2 Cyclone V SX 2,4602313702,700270C4 4,4504807683,970397C5 5,7616219945,570557C6 4,4504807683,970397D5 Cyclone V ST 5,7616219945,570557D6 Embedded Memory Configurations Table 19: Supported Embedded Memory Block Configurations for Cyclone V Devices This table lists the maximum configurations supported for the embedded memory blocks. The information is applicable only to the single-port RAM and ROM modes. Programmable WidthDepth (bits)Memory Block x16, x18, or x2032MLAB x40 or x32256 M10K x20 or x16512 x10 or x81K x5 or x42K x24K x18K Clock Networks and PLL Clock Sources Cyclone V devices have 16 global clock networks capable of up to 550 MHz operation. The clock network architecture is based on Altera's global, quadrant, and peripheral clock structure. This clock structure is supported by dedicated clock input pins and fractional PLLs. To reduce power consumption, the Quartus II software identifies all unused sections of the clock network and powers them down. Note: Altera CorporationCyclone V Device Overview Send Feedback 21Embedded Memory Configurations CV-51001 2013.12.26

The PLLs in the Cyclone V devices support the following features:

• Frequency synthesis
• On-chip clock deskew
• Jitter attenuation
• Programmable output clock duty cycles
• PLL cascading
• Reference clock switchover
• Programmable bandwidth
• User-mode reconfiguration of PLLs
• Low power mode for each fractional PLL
• Dynamic phase shift
• Direct, source synchronous, zero delay buffer, external feedback, and LVDS compensation modes Fractional PLL In addition to integer PLLs, the Cyclone V devices use a fractional PLL architecture. The devices have up to eight PLLs, each with nine output counters. You can use the output counters to reduce PLL usage in two ways:
• Reduce the number of oscillators that are required on your board by using fractional PLLs
• Reduce the number of clock pins that are used in the device by synthesizing multiple clock frequencies from a single reference clock source If you use the fractional PLL mode, you can use the PLLs for precision fractional-N frequency synthesis—removing the need for off-chip reference clock sources in your design. The transceiver fractional PLLs that are not used by the transceiver I/Os can be used as general purpose fractional PLLs by the FPGA fabric. FPGA General Purpose I/O Cyclone V devices offer highly configurable GPIOs. The following list describes the features of the GPIOs:
• Programmable bus hold and weak pull-up
• LVDS output buffer with programmable differential output voltage (VOD ) and programmable pre- emphasis
• On-chip parallel termination (RT OCT) for all I/O banks with OCT calibration to limit the termination impedance variation
• On-chip dynamic termination that has the ability to swap between series and parallel termination, depending on whether there is read or write on a common bus for signal integrity
• Easy timing closure support using the hard read FIFO in the input register path, and delay-locked loop (DLL) delay chain with fine and coarse architecture PCIe Gen1 and Gen2 Hard IP CycloneV GX, GT, SX, and ST devicescontainPCIe hard IP that is designedfor performanceand ease-of-use. The PCIe hard IP consists of the MAC, data link, and transaction layers. Cyclone V Device OverviewAltera Corporation Send Feedback CV-51001 FPGA General Purpose I/O22 2013.12.26

The PCIe hard IP supports PCIe Gen2 and Gen1 end point and root port for up to x4 lane configuration. The PCIe Gen2 x4 support is PCIe-compatible. The PCIe endpoint support includes multifunction support for up to eight functions, as shown in the following figure. The integrated multifunction support reduces the FPGA logic requirements by up to 20,000 LEs for PCIe designs that require multiple peripherals. Figure 9: PCIe Multifunction for Cyclone V Devices PCIeLink External System FPGA Device HostCPU Memory Controller Root Complex Local Peripheral1 Local Peripheral2 PCIeRP PCIeEP CAN GbE ATA Bridge toPCIe SPI GPIO I2C USB The Cyclone V PCIe hard IP operates independently from the core logic. This independent operation allows the PCIe link to wake up and complete link training in less than 100 ms while the Cyclone V device completes loading the programming file for the rest of the device. In addition, the PCIe hard IP in the Cyclone V device provides improved end-to-end datapath protection using ECC. External Memory Interface This section provides an overview of the external memory interface in Cyclone V devices. Hard and Soft Memory Controllers Cyclone V devices support up to two hard memory controllers for DDR3, DDR2, and LPDDR2 SDRAM devices. Each controller supports 8 to 32 bit components of up to 4 gigabits (Gb) in density with two chip selects and optional ECC. For the Cyclone V SoC devices, an additional hard memory controller in the HPS supports DDR3, DDR2, and LPDDR2 SDRAM devices. All Cyclone V devices support soft memory controllers for DDR3, DDR2, and LPDDR2 SDRAM devices for maximum flexibility. External Memory Performance Table 20: External Memory Interface Performance in Cyclone V Devices The maximum and minimum operating frequencies depend on the memory interface standards and the supported delay-locked loop (DLL) frequency listed in the device datasheet. Minimum Frequency (MHz) Maximum Frequency (MHz)Voltage (V)Interface Soft ControllerHard Controller 3033034001.5DDR3 SDRAM 3033034001.35 Altera CorporationCyclone V Device Overview Send Feedback 23External Memory Interface CV-51001 2013.12.26

Minimum Frequency (MHz) Maximum Frequency (MHz)Voltage (V)Interface Soft ControllerHard Controller 1673004001.8DDR2 SDRAM 1673003331.2LPDDR2 SDRAM Related Information External Memory Interface Spec Estimator For the latest informationand to estimatethe externalmemory system performancespecification,use Altera's External Memory Interface Spec Estimator tool. HPS External Memory Performance Table 21: HPS External Memory Interface Performance The hard processor system (HPS) is available in Cyclone V SoC devices only. HPS Hard Controller (MHz)Voltage (V)Interface 4001.5 DDR3 SDRAM 4001.35 4001.8DDR2 SDRAM 3331.2LPDDR2 SDRAM Related Information External Memory Interface Spec Estimator For the latest informationand to estimatethe externalmemory system performancespecification,use Altera's External Memory Interface Spec Estimator tool. Low-Power Serial Transceivers Cyclone V devices deliver the industry’s lowest power 6.144 Gbps transceivers at an estimated 88 mW maximum power consumption per channel. Cyclone V transceivers are designed to be compliant with a wide range of protocols and data rates. Transceiver Channels The transceivers are positioned on the left outer edge of the device. The transceiver channels consist of the physical medium attachment (PMA), physical coding sublayer (PCS), and clock networks. Cyclone V Device OverviewAltera Corporation Send Feedback CV-51001 HPS External Memory Performance24 2013.12.26

Figure 10: Device Chip Overview for Cyclone V GX and GT Devices The figure shows a Cyclone V FPGA with transceivers. Different Cyclone V devices may have a different floorplans than the one shown here. I/O,LVDS,andMemoryInterface I/O,LVDS,andMemoryInterface I/O,LVDS,andMemoryInterface TransceiverPMABlocks FractionalPLLs HardPCSBlocks FractionalPLL FractionalPLLs PCIeHardIPBlocks HardMemoryController HardMemoryController CoreLogicFabricandMLABs Variable-PrecisionDSPBlocks M10KInternalMemoryBlocks Transceiver PMA Transceiver PMA Transceiver PMA Hard PCS Hard PCS Hard PCS ClockNetworks Transceiver IndividualChannels PMA Features To prevent core and I/O noise from coupling into the transceivers, the PMA block is isolated from the rest of the chip—ensuringoptimal signal integrity.For the transceivers,you can use the channel PLL of an unused receiver PMA as an additional transmit PLL. Table 22: PMA Features of the Transceivers in Cyclone V Devices CapabilityFeatures Driving capability up to 6.144 GbpsBackplane support Superior jitter tolerancePLL-based clock recovery Flexible deserialization width and configurable word alignment patternProgrammabledeserializationand word alignment

• Up to 14.37 dB of pre-emphasis and up to 4.7 dB of equalization
• No decision feedback equalizer (DFE) Equalization and pre-emphasis 614 Mbps to 6.144 GbpsRing oscillator transmit PLLs

20 MHz to 400 MHzInput reference clock range

Altera CorporationCyclone V Device Overview Send Feedback 25PMA Features CV-51001 2013.12.26

Allows the reconfiguration of a single channel without affecting the operation of other channels Transceiverdynamicreconfigura- tion PCS Features The Cyclone V core logic connects to the PCS through an 8, 10, 16, 20, 32, or 40 bit interface, depending on the transceiver data rate and protocol. Cyclone V devices contain PCS hard IP to support PCIe Gen1 and Gen2, Gbps Ethernet (GbE), Serial RapidIO® (SRIO), and Common Public Radio Interface (CPRI). Most of the standard and proprietary protocols from 614 Mbps to 6.144 Gbps are supported. Table 23: Transceiver PCS Features for Cyclone V Devices Receiver Data Path FeatureTransmitter Data Path FeatureData Rates(Gbps)PCS Support

• Word aligner
• Deskew FIFO
• Rate-match FIFO
• 8B/10B decoder
• Byte deserializer
• Byte ordering
• Receiver phase compensa- tion FIFO
• Phase compensation FIFO
• Byte serializer
• 8B/10B encoder
• Transmitter bit-slip 0.614 to 6.1443-Gbps and 6-Gbps Basic
• Dedicated PCIe PHY IP core
• PIPE 2.0 interface to the core logic
• Dedicated PCIe PHY IP core
• PIPE 2.0 interface to the core logic 2.5 and 5.0 PCIe Gen1 (x1, x2, x4) PCIe Gen2 ( x1, x2, x4)(10)
• Custom PHY IP core with preset feature
• GbE receiver synchroniza- tion state machine
• Custom PHY IP core with preset feature
• GbE transmitter synchroniza- tion state machine 1.25GbE
• Dedicated XAUI PHY IP core
• XAUIsynchronizationstate machine for realigning four channels
• Dedicated XAUI PHY IP core
• XAUI synchronization state machine for bonding four channels 3.125XAUI (11) 3.75HiGig (10) PCIe Gen2 is supported only for Cyclone V GT devices. The PCIe Gen2 x4 support is PCIe-compatible. (11) XAUI is supported through the soft PCS. Cyclone V Device OverviewAltera Corporation Send Feedback CV-51001 PCS Features26 2013.12.26

Receiver Data Path FeatureTransmitter Data Path FeatureData Rates(Gbps)PCS Support

• Custom PHY IP core with preset feature
• SRIO version2.1-compliant x2 and x4 deskew state machine
• Custom PHY IP core with preset feature
• SRIO version 2.1-compliant x2 and x4 channel bonding 1.25 to 3.125SRIO 1.3 and 2.1 Custom PHY IP core with preset feature Custom PHY IP core with preset feature 0.27(12), 1.485, and 2.97 SDI, SD/HD, and 3G- SDI 0.3125(13) to 3.125 JESD204A
• Custom PHY IP core with preset feature
• Signal detect
• Wider spread of asynchronous SSC
• Custom PHY IP core with preset feature
• Electrical idle 1.5 and 3.0Serial ATA Gen1 and Gen2
• Dedicated deterministic latency PHY IP core
• Receiver(RX) deterministic latency state machine
• Dedicateddeterministiclatency PHY IP core
• Transmitter (TX) manual bit-slip mode 0.6144 to 6.144CPRI 4.1(14) 0.768 to 3.072 OBSAI RP3
• Custom PHY IP core
• Wider spread of asynchronous SSC Custom PHY IP core Up to 3.75V-by-One HS 1.62 and 2.7DisplayPort 1.2(15) SoC with HPS Each SoC combines an FPGA fabric and an HPS in a single device. This combination delivers the flexibility of programmable logic with the power and cost savings of hard IP in these ways:
• Reducesboardspace,systempower,and bill of materialscost by eliminatinga discreteembeddedprocessor
• Allows you to differentiate the end product in both hardware and software, and to support virtually any interface standard
• Extends the product life and revenue through in-field hardware and software updates (12) The 0.27-Gbps data rate is supported using oversampling user logic that you must implement in the FPGA fabric. (13) The 0.3125-Gbps data rate is supported using oversampling user logic that you must implement in the FPGA fabric. (14) High-voltage output mode (1000-BASE-CX) is not supported. (15) Pending characterization. Altera CorporationCyclone V Device Overview Send Feedback 27SoC with HPS CV-51001 2013.12.26

The HPS consists of a dual-core ARM Cortex-A9 MPCore processor, a rich set of peripherals, and a shared multiport SDRAM memory controller, as shown in the following figure. Figure 11: HPS with Dual-Core ARM Cortex-A9 MPCore Processor FPGA Fabric HPS HPS-to-FPGA Lightweight HPS-to-FPGAFPGA-to-HPS FPGA-to-HPSSDRAM Configuration Controller FPGA Manager 64KB On-ChipRAM 64KB BootROM Level3 Interconnect Ethernet MAC(2x) USB OTG(2x) NANDFlash Controller SD/MMC Controller DMA Controller STM ETR (Trace) Debug AccessPort ARMCortex-A9MPCore MPU Subsystem CPU0 ARMCortex-A9 withNEON/FPU, 32KBInstructionCache, 32KBDataCache,and MemoryManagementUnit CPU1 ARMCortex-A9 withNEON/FPU, 32KBInstructionCache, 32KBDataCache,and MemoryManagementUnit SCUACP Level2Cache(512KB) Multiport DDRSDRAM Controller with OptionalECC Peripherals (UART,Timer,I2C,WatchdogTimer,GPIO,SPI,ClockManager,ResetManager,ScanManager,SystemManager,and QuadSPIFlashController) System Peripherals and Debug Access Port Each Ethernet MAC, USB OTG, NAND flash controller, and SD/MMC controller module has an integrated DMA controller. For modules without an integrated DMA controller, an additional DMA controller module provides up to eight channels of high-bandwidth data transfers. Peripherals that communicate off-chip are multiplexed with other peripherals at the HPS pin level. This allows you to choose which peripherals to interface with other devices on your PCB. The debug access port provides interfaces to industry standard JTAG debug probes and supports ARM CoreSight debug and core traces to facilitate software development. Cyclone V Device OverviewAltera Corporation Send Feedback CV-51001 HPS Features28 2013.12.26

HPS–FPGA AXI Bridges The HPS–FPGAbridges,whichsupportthe AdvancedMicrocontrollerBus Architecture(AMBA®) Advanced eXtensible Interface (AXI™) specifications, consist of the following bridges:

• FPGA-to-HPS AXI bridge—a high-performance bus supporting 32, 64, and 128 bit data widths that allows the FPGA fabric to issue transactions to slaves in the HPS.
• HPS-to-FPGA AXI bridge—a high-performance bus supporting 32, 64, and 128 bit data widths that allows the HPS to issue transactions to slaves in the FPGA fabric.
• Lightweight HPS-to-FPGA AXI bridge—a lower latency 32 bit width bus that allows the HPS to issue transactions to slaves in the FPGA fabric. This bridge is primarily used for control and status register (CSR) accesses to peripherals in the FPGA fabric. The HPS–FPGA AXI bridges allow masters in the FPGA fabric to communicate with slaves in the HPS logic, and vice versa. For example, the HPS-to-FPGA AXI bridge allows you to share memories instantiated in the FPGA fabric with one or both microprocessors in the HPS, while the FPGA-to-HPS AXI bridge allows logic in the FPGA fabric to access the memory and peripherals in the HPS. Each HPS–FPGA bridge also provides asynchronous clock crossing for data transferred between the FPGA fabric and the HPS. HPS SDRAM Controller Subsystem The HPS SDRAM controller subsystem contains a multiport SDRAM controller and DDR PHY that are shared between the FPGA fabric (through the FPGA-to-HPS SDRAM interface), the level 2 (L2) cache, and the level 3 (L3) system interconnect.The FPGA-to-HPSSDRAM interfacesupports AMBA AXI and Avalon® Memory-Mapped (Avalon-MM) interface standards, and provides up to six individual ports for access by masters implemented in the FPGA fabric. To maximize memory performance, the SDRAM controller subsystem supports command and data reordering, deficit round-robin arbitration with aging, and high-priority bypass features. The SDRAM controller subsystem supports DDR2, DDR3, or LPDDR2 devices up to 4 Gb in density operating at up to 400 MHz (800 Mbps data rate). FPGA Configuration and Processor Booting The FPGA fabric and HPS in the SoC are powered independently. You can reduce the clock frequencies or gate the clocks to reduce dynamic power, or shut down the entire FPGA fabric to reduce total system power. You can configure the FPGA fabric and boot the HPS independently, in any order, providing you with more design flexibility:
• You can boot the HPS independently. After the HPS is running, the HPS can fully or partially reconfigure the FPGA fabric at any time under software control. The HPS can also configure other FPGAs on the board through the FPGA configuration controller.
• You can power up both the HPS and the FPGA fabric together, configure the FPGA fabric first, and then boot the HPS from memory accessible to the FPGA fabric. Although the FPGA fabric and HPS are on separate power domains, the HPS must remain powered up during operation while the FPGA fabric can be powered up or down as required. Note: Altera CorporationCyclone V Device Overview Send Feedback 29HPS–FPGA AXI Bridges CV-51001 2013.12.26

Cyclone V Device Family Pin Connection Guidelines Provides detailed information about power supply pin connection guidelines and power regulator sharing. Hardware and Software Development For hardware development, you can configure the HPS and connect your soft logic in the FPGA fabric to the HPS interfaces using the Qsys system integration tool in the Quartus II software. For software development, the ARM-based SoC devices inherit the rich software development ecosystem available for the ARM Cortex-A9 MPCore processor. The software development process for Altera SoCs followsthe samestepsas thosefor otherSoC devicesfromothermanufacturers.Supportfor Linux,VxWorks®, and other operatingsystems is availablefor the SoCs. For more informationon the operatingsystems support availability, contact the Altera sales team. You can begin device-specific firmware and software development on the Altera SoC Virtual Target. The VirtualTargetis a fast PC-basedfunctionalsimulationof a targetdevelopmentsystem—amodel of a complete development board that runs on a PC. The Virtual Target enables the development of device-specific production software that can run unmodified on actual hardware. Related Information Altera Worldwide Sales Support Dynamic and Partial Reconfiguration The Cyclone V devices support dynamic reconfiguration and partial reconfiguration(16). Dynamic Reconfiguration The dynamic reconfiguration feature allows you to dynamically change the transceiver data rates, PMA settings, or protocols of a channel, without affecting data transfer on adjacent channels. This feature is ideal for applications that require on-the-fly multiprotocol or multirate support. You can reconfigure the PMA and PCS blocks with dynamic reconfiguration. Partial Reconfiguration Partial reconfiguration is an advanced feature of the device family. If you are interested in using partial reconfiguration, contact Altera for support. Note: Partial reconfiguration allows you to reconfigure part of the device while other sections of the device remain operational. This capability is important in systems with critical uptime requirements because it allows you to make updates or adjust functionality without disrupting services. Apart from loweringcost and power consumption,partialreconfigurationincreasesthe effectivelogic density of the device because placing device functions that do not operate simultaneously is not necessary. Instead, you can store these functions in external memory and load them whenever the functions are required. This (16) Partial reconfiguration is an advanced feature of the device family. If you are interested in using partial reconfiguration, contact Altera for support. Cyclone V Device OverviewAltera Corporation Send Feedback CV-51001 Hardware and Software Development30 2013.12.26

capability reduces the size of the device because it allows multiple applications on a single device—saving the board space and reducing the power consumption. Altera simplifies the time-intensive task of partial reconfiguration by building this capability on top of the proven incremental compile and design flow in the Quartus II design software. With the Altera® solution, you do not need to know all the intricate device architecture details to perform a partial reconfiguration. Partial reconfiguration is supported through the FPP x16 configuration interface. You can seamlessly use partialreconfigurationin tandemwithdynamicreconfigurationto enablesimultaneouspartialreconfiguration of both the device core and transceivers. Enhanced Configuration and Configuration via Protocol Cyclone V devices support 1.8 V, 2.5 V, 3.0 V, and 3.3 V programming voltages and several configuration modes. Table 24: Configuration Modes and Features Supported by Cyclone V Devices Remote System Update Partial Reconfigura- tion(17) Design Security Decompres- sion Max Data Rate (Mbps) Max Clock Rate (MHz) Data Width Mode Yes—YesYes—1001 bit, 4 bits AS through the EPCS and EPCQ serial configura- tion device ——YesYes1251251 bitPSthroughCPLD or external microcontroller Parallel flash loader —YesYes—1258 bits FPP YesYesYes—12516 bits —YesYesYes——x1, x2, and x4 lanes CvP (PCIe) ————33331 bitJTAG Instead of using an external flash or ROM, you can configure the Cyclone V devices through PCIe using CvP. The CvP mode offers the fastest configuration rate and flexibility with the easy-to-use PCIe hard IP block interface. The Cyclone V CvP implementation conforms to the PCIe 100 ms power-up-to-active time requirement. Related Information Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide Provides more information about CvP. (17) Partial reconfiguration is an advanced feature of the device family. If you are interested in using partial reconfiguration, contact Altera for support. Altera CorporationCyclone V Device Overview Send Feedback 31Enhanced Configuration and Configuration via Protocol CV-51001 2013.12.26

Leveraging the FPGA architectural features, process technology advancements, and transceivers that are designed for power efficiency, the Cyclone V devices consume less power than previous generation Cyclone FPGAs:

• Total device core power consumption—less by up to 40%.
• Transceiver channel power consumption—less by up to 50%. Additionally, Cyclone V devices contain several hard IP blocks that reduce logic resources and deliver substantial power savings of up to 25% less power than equivalent soft implementations. Document Revision History ChangesVersionDate
• Corrected single or dual-core ARM Cortex-A9 MPCore processor-up to 925 MHz from 800 MHz.
• Removed "Preliminary" texts from Ordering Code figures, Maximum Resources, Package Plan and I/O Vertical Migration tables.
• Removed the note "The number of GPIOs does not include transceiver I/Os. In the Quartus II software, the number of user I/Os includes transceiver I/Os." for GPIOs in the Maximum Resource Counts table for Cyclone V E and SE.
• Added link to Altera Product Selector for each device variant. 2014.12.26December 2013
• Updated Embedded Hard IPs for Cyclone V GT devices to indicate Maximum 2 hard PCIe and 2 hard memory controllers.
• Added leaded package options.
• Removed the note "The number of PLLs includes general-purpose fractional PLLs and transceiver fractional PLLs." for all PLLs in the Maximum Resource Counts table.
• Corrected max LVDS counts for transmitter and receiver for Cyclone V E A5 device from 84 to 60.
• Corrected max LVDS counts for transmitter and receiver for Cyclone V E A9 device from 140 to 120.
• Corrected variable-precision DSP block, 27 x 27 multiplier, 18 x 18 multiplier adder mode and 18 x 18 multiplier adder summed with 36 bit input for Cyclone V SE devices from 58 to 84.
• Corrected 18 x 18 multiplier for Cyclone V SE devices from 116 to 168.
• Corrected 9 x 9 multiplier for Cyclone V SE devices from 174 to 252.
• Corrected LVDS transmitter for Cyclone V SE A2 and A4 as well as SX C2 and C4 devices from 31 to 32.
• Corrected LVDS receiver for Cyclone V SE A2 and A4 as well as SX C2 and C4 devices from 35 to 37.
• Corrected transceiver speed grade for Cyclone V ST devices ordering code from 4 to 5. Cyclone V Device OverviewAltera Corporation Send Feedback CV-51001 Power Management32 2013.12.26

• UpdatedtheDDR3SDRAMforthemaximumfrequency'ssoftcontroller and the minimum frequency from 300 to 303 for voltage 1.35V.
• Added links to Altera's External Memory Spec Estimator tool to the topics listing the external memory interface performance.
• Corrected XAUI is supported through the soft PCS in the PCS features for Cyclone V.
• Added decompression support for the CvP configuration mode.
• Added link to the known document issues in the Knowledge Base.
• Moved all links to the Related Information section of respective topics for easy reference.
• Corrected the title to the PCIe hard IP topic. Cyclone V devices support only PCIe Gen1 and Gen2.
• Updated SupportingFeature in Table 1 of Increasedbandwidthcapacity to '6.144 Gbps'. 2013.05.06May 2013
• UpdatedDescriptionin Table2 of Low-powerhigh-speedserialinterface to '6.144 Gbps'.
• Updated Description in Table 3 of Cyclone V GT to '6.144 Gbps'.
• Updated the M386 package to M383 for Figure 1, Figure 2 and Figure
• Updated Figure 2 and Figure 3 for Transceiver Count by adding 'F : 4'.
• Updated LVDS in the Maximum Resource Counts tables to include Transmitter and Receiver values.
• Updated the package plan with M383 for the Cyclone V E device.
• Removed the M301 and M383 packages from the Cyclone V GX C4 device.
• Updated the GPIO count to '129' for the M301 package of the Cyclone V GX C5 device.
• Updated 5 Gbps to '6.144 Gbps' forCyclone V GT device.
• Updated HPS I/O for U484 (19 mm) in Table 11 with '151' for A2, A4, A5 and A6.
• Updated Memory (Kb) for Maximum Resource Counts for Cyclone V SE A4 and A6, SX C4 and C6, ST D6 devices.
• Updated FPGA PLL for Maximum Resource Counts for Cyclone V SE A2, SX C2, devices.
• Removed '36 x 36' from the Variable-Precision DSP Block.
• Updated Variable-precision DSP Blocks and 18 x 18 Multiplier for Maximum Resource Counts for Cyclone V SX C4 device.
• Updated the HPS I/O counts for Cyclone V SE, SX, and ST devices.
• Updated Figure 7 which shows the I/O vertical migration table.
• Updated Table 17 for Cyclone V SX C4 device.
• Updated Embedded Memory Capacity and Distribution table for Cyclone V SE A4 and A6, SX C4 and C6, ST D6 devices.
• Removed 'Counter reconfiguration' from the PLL Features. Altera CorporationCyclone V Device Overview Send Feedback 33Document Revision History CV-51001 2013.12.26

• Updated Low-Power Serial Transceivers by replacing 5 Gbps with 6.144 Gbps.
• Removed 'Distributed Memory' symbol.
• Updatedthe Capabilityin Table 22 of Backplanesupportto '6.144 Gbps'.
• Updated Capability in Table 22 of Ring oscillator transmit PLLs with 6.144 Gbps.
• Updated the PCS Support in Table 23 from 5 Gbps to '6 Gbps'.
• Updated the Data Rates (Gbps) in Table 23 of 3 Gbps and 6 Gbps Basic to '6.144 Gbps'.
• Updated the Data Rates (Gbps) in Table 23 of CPRI 4.1 to '6.144 Gbps'.
• Clarified that partial reconfiguration is an advanced feature. Contact Altera for support of the feature.
• Updated the pin counts for the MBGA packages.
• Updated the GPIO and transceiver counts for the MBGA packages.
• Updated the GPIO counts for the U484 package of the Cyclone V E A9, GX C9, and GT D9 devices.
• Updated the vertical migration table for vertical migration of the U484 packages.
• Updated the MLAB supported programmable widths at 32 bits depth. 2012.12.28December 2012
• Added new MBGA packages and additional U484 packages for Cyclone V E, GX, and GT.
• Added ordering code for five-transceiver devices for Cyclone V GT and ST.
• Updated the vertical migration table to add MBGA packages.
• Added performance information for HPS memory controller.
• Removed DDR3U support.
• Updated Cyclone V ST speed grade information.
• Added informationon maximum transceiverchannel usage restrictions for PCI Gen2 and CPRI at 4.9152 Gbps transmit jitter compliance.
• Added note on the differences between GPIO reported in Overview with User I/O numbers shown in the Quartus II software.
• Updated template. 2012.11.19November2012 Added support for PCIe Gen2 x4 lane configuration (PCIe-compatible)2.1July 2012 Cyclone V Device OverviewAltera Corporation Send Feedback CV-51001 Document Revision History34 2013.12.26

• Restructured the document.
• Added the “Embedded Memory Capacity” and “Embedded Memory Configurations” sections.
• Added Table 1, Table 3, Table 16, Table 19, and Table 20.
• Updated Table 2, Table 4, Table 5, Table 6, Table 7, Table 8, Table 9, Table 10, Table 11, Table 12, Table 13, Table 14, Table 17, and Table 18.
• Updated Figure 1, Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, and Figure 10.
• Updated the “FPGA Configuration and Processor Booting” and “Hardware and Software Development” sections.
• Text edits throughout the document. 2.0June 2012
• Updated Table 1–2, Table 1–3, and Table 1–6.
• Updated “Cyclone V Family Plan” on page 1–4 and “Clock Networks and PLL Clock Sources” on page 1–15.
• Updated Figure 1–1 and Figure 1–6. 1.2February 2012
• Updated Table 1–1, Table 1–2, Table 1–3, Table 1–4, Table 1–5, and Table 1–6.
• Updated Figure 1–4, Figure 1–5, Figure 1–6, Figure 1–7, and Figure 1–8.
• Updated“SystemPeripherals”on page 1–18, “HPS–FPGAAXI Bridges” on page 1–19, “HPS SDRAM Controller Subsystem” on page 1–19, “FPGA Configuration and Processor Booting” on page 1–19, and “Hardware and Software Development” on page 1–20.
• Minor text edits. 1.1November2011 Initial release.1.0October 2011 Altera CorporationCyclone V Device Overview Send Feedback 35Document Revision History CV-51001 2013.12.26