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June 2013 Altera Corporation CV-51002-3.4 Datasheet © 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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San Jose, CA 95134 www.altera.com Feedback Subscribe ISO 9001:2008 Registered Cyclone V Device Datasheet This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and I/O timing for Cyclone ® V devices. Cyclone V devices are offered in commercial and industrial grades. Commercial devices are offered in –C6 (fastest), –C7, and –C8 speed grades. Industrial devices are offered in the –I7 speed grade. Automotive devices are offered in the –A7 speed grade. f For more information about the densities and packages of devices in the Cyclone V family, refer to the Cyclone V Device Overview .
Electrical Characteristics
The following sections describe the electrical characteristics of Cyclone V devices. Operating Conditions Cyclone V devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of the Cyclone V devices, you must consider the operating requirements described in this datasheet. June 2013 CV-51002-3.4
theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these conditions. periods of time may have adverse effects on the device. Table 1 lists the Cyclone V absolute maximum ratings. Table 1. Absolute Maximum Ratings for Cyclone V Devices— Preliminary
over the lifetime of the device. A DC signal is equivalent to 100% duty cycle. lifetime of the device; for a device lifetime of 10 years, this amounts to 1.5 years. overshoot voltage as a percentage of device lifetime. Table 2. Maximum Allowed Overshoot During Transitions for Cyclone V Devices— Preliminary
and DC parameters for Cyclone V devices. supply ramps must all be strictly monotonic, without plateaus. Table 3. Recommended Operating Conditions for Cyclone V Devices— Preliminary (Part 1 of 2)
Cyclone V GX and GT devices. supply ramps must all be strictly monotonic, without plateaus. (2) PLL digital voltage is regulated from V CCA_FPLL. (POR) circuitry monitors V CCBAT. Cyclone V devices do not exit POR if V CCBAT stays low. tRAMP specifications for fast POR when HPS_PORSEL = 1. Table 3. Recommended Operating Conditions for Cyclone V Devices— Preliminary (Part 2 of 2) Table 4. Transceiver Power Supply Operating Conditions for Cyclone V GX and GT Devices— Preliminary Cyclone V GT and ST devices under this condition, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter. in Cyclone V Devices chapter. Table 5. HPS Power Supply Operating Conditions for Cyclone V SE, SX, and ST Devices (1)— Preliminary (Part 1 of 2)
Power Estimator (EPE) and the Quartus ® II PowerPlay Power Analyzer feature. of the device power because these currents vary greatly with the resources you use. (1) Refer to Table 3 for the steady-state voltage values expected from the FPGA portion of the Cyclone V system-on-a-chip (SoC) FPGAs. Table 5. HPS Power Supply Operating Conditions for Cyclone V SE, SX, and ST Devices (1)— Preliminary (Part 2 of 2)
Table 6 lists the Cyclone V I/O pin leakage current specifications. based on calculated input voltages from the JEDEC standard. Table 6. I/O Pin Leakage Current for Cyclone V Devices— Preliminary Table 7. Bus Hold Parameters for Cyclone V Devices— Preliminary
performed at power up for I/Os connected to the calibration block. OCT calibration accuracy is valid at the time of calibration only.
1 Calibration accuracy for the calibrated on-chip series termination (R S OCT) and
on-chip parallel termination (R T OCT) are applicable at the moment of calibration. Table 8. OCT Calibration Accuracy Specifications for Cyclone V Devices
Equation 1 to determine the OCT variation without recalibration. Table 9. OCT Without Calibration Resistance Tolerance Specifications for Cyclone V Devices— Preliminary (2) R SCAL is the OCT resistance value at power-up. (3) ΔT is the variation of temperature with respect to the temperature at power up. (4) ΔV is the variation of voltage with respect to V CCIO at power up. (5) dR/dT is the percentage change of R SCAL with temperature. (6) dR/dV is the percentage change of R SCAL with voltage.
Table 11 lists the Cyclone V device family pin capacitance. Table 12 lists the hot socketing specifications for Cyclone V devices. Table 10. OCT Variation after Power-Up Calibration for Cyclone V Devices Table 11. Pin Capacitance for Cyclone V Devices Table 12. Hot Socketing Specifications for Cyclone V Devices— Preliminary capacitance and dv/dt is the slew rate.
Table 13 lists the weak pull-up resistor values for Cyclone V devices. supported by Cyclone V devices. Table 13. Internal Weak Pull-Up Resistor Values for Cyclone V Devices— Preliminary programmable pull-up resistor option. (1) Pin pull-up resistance values may be lower if an external source drives the pin higher than V CCIO. (2) These specifications are valid with ±10% tolerances to cover changes over PVT. Table 14. Single-Ended I/O Standards for Cyclone V Devices— Preliminary (Part 1 of 2)
Table 14. Single-Ended I/O Standards for Cyclone V Devices— Preliminary (Part 2 of 2) Table 15. Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Cyclone V Devices— Preliminary Table 16. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Cyclone V Devices—
should set the current strength settings to 8 mA. Setting at lower current strength may not meet the I OL and I OH specifications in the handbook. Table 17. Differential SSTL I/O Standards for Cyclone V Devices— Preliminary
0.15 VCCIO/2 VCCIO/2 +
Table 18. Differential HSTL and HSUL I/O Standards for Cyclone V Devices— Preliminary
0.3 VCCIO
Table 19. Differential I/O Standard Specifications for Cyclone V Devices— Preliminary transmitter, receiver, and reference clock I/O pin specifications, refer to Table 20.
1.25 V —
0.05 DMAX
1.05 DMAX
0.60 DMAX
1.00 DMAX
(1) The minimum V ID value is applicable over the entire common mode range, V CM. for data rate below 700 Mbps. (4) For optimized RSDS receiver performance, the receiver voltage input range must be within 0.25 V to 1.45 V. (5) For optimized mini-LVDS receiver performance, the receiver voltage input range must be within 0.300 V to 1.425 V. 1.95 V for data rate below 700 Mbps.
blocks for commercial grade devices. This section describes transceiver performance specifications. Table 20 lists the Cyclone V GX, GT, SX, and ST transceiver specifications. Table 20. Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices— Preliminary (Part 1 of 4)
2.5 V PCML ,
Table 20. Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices— Preliminary (Part 2 of 4)
Table 20. Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices— Preliminary (Part 3 of 4)
(1) Transceiver Speed Grade 5 covers specifications for Cyclone V GT and ST devices. (2) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table. CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter. (4) The transmitter REFCLK phase jitter is 30 ps p-p at bit error rate (BER) 10 -12. devices under this condition, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter. recommended in Cyclone V GT devices for CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter. (7) The maximum supported clock frequency is 100 MHz if the PCIe hard IP block is enabled or 125 MHz if the PCIe hard IP block is not enabled. Transceiver Architecture in Cyclone V Devices chapter. (9) The device cannot tolerate prolonged operation at this absolute maximum. Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. LTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset. (12) t LTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high. functioning in the manual mode. is functioning in the manual mode. (15) The rate matcher supports only up to ±300 parts per million (ppm). (16) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode. Table 20. Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices— Preliminary (Part 4 of 4)
Table 21 lists the TX V OD settings for Cyclone V transceiver channels. Table 21. Typical TX V OD Setting for Cyclone V Transceiver Channels = 100 Ω— Preliminary
1 To predict the pre-emphasis level for your specific data rate and pattern, run
simulations using the Cyclone V HSSI HSPICE models. Table 22. Transmitter Pre-Emphasis Levels for Cyclone V Devices (1), (2), (3), (4)— Preliminary (Part 1 of 2)
(4) For example, when V OD = 800 mV, the corresponding V OD value setting is 40. Therefore, the 1st post tap pre-emphasis settin g=2i sa valid condition. Table 22. Transmitter Pre-Emphasis Levels for Cyclone V Devices (1), (2), (3), (4)— Preliminary (Part 2 of 2)
processing (DSP), and memory block specifications. Table 23 lists the clock tree specifications for Cyclone V devices. Table 23. Clock Tree Performance for Cyclone V Devices— Preliminary Table 24. PLL Specifications for Cyclone V Devices (1)— Preliminary (Part 1 of 3)
Table 24. PLL Specifications for Cyclone V Devices (1)— Preliminary (Part 2 of 3)
Table 25 lists the Cyclone V DSP block performance specifications. (1) Pending silicon characterization. (2) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard . a value of 2, the frequency reported can be lower than the f VCO specification. (4) This specification is limited by the lower of the two: I/O f MAX or F OUT of the PLL. (5) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 12 0 ps. (6) F REF is f IN/N, specification applies when N =1 . measurement method and are available in Table 30 on page 1–30 . (9) High bandwidth PLL settings are not supported in external feedback mode. (10) External memory interface clock output jitter specifications use a different measurement method, which is available in Table 30 on page 1–30 . Table 24. PLL Specifications for Cyclone V Devices (1)— Preliminary (Part 3 of 3) Table 25. DSP Block Performance Specifications for Cyclone V Devices— Preliminary
Table 26 lists the Cyclone V memory block specifications. setup to determine the maximum achievable frequency in your system. Table 26. Memory Block Performance Specifications for Cyclone V Devices— Preliminary
Table 27 lists high-speed I/O timing for Cyclone V devices. Table 27. High-Speed I/O Specifications for Cyclone V Devices (1), (2), (3) — Preliminary (Part 1 of 2)
600 Mbps - 840 Mbps — — 350
( 1 ) W h e nJ=1o r2 , bypass the serializer/deserializer (SERDES) block. (2) For LVDS applications, you must use the PLLs in integer PLL mode. (3) This is achieved by using the LVDS clock network. (4) Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate. design dependent and requires timing analysis. or local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate. margin, transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin. (8) The specifications are retrieved without partial reconfiguration support. the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported. Table 27. High-Speed I/O Specifications for Cyclone V Devices (1), (2), (3) — Preliminary (Part 2 of 2)
Table 28 lists the DLL operating frequency range specifications for Cyclone V devices. is the absolute maximum and minimum error. Table 30 lists the memory output clock jitter specifications for Cyclone V devices. specified in the JEDEC DDR2/DDR3 SDRAM standard. applied with bit error rate (BER) 10 –12, equivalent to 14 sigma. connections for better jitter performance. Table 28. DLL Operating Frequency Range Specifications for Cyclone V Devices Table 29. DQS Phase Shift Error Specification for DLL-Delayed Clock (t DQS_PSERR) for Cyclone V (1) The numbers are preliminary pending silicon characterization. Table 30. Memory Output Clock Jitter Specification for Cyclone V Devices— Preliminary
This section provides configuration specifications and timing for Cyclone V devices. Table 46 lists the specifications for fast and standard POR delay for Cyclone V devices. Table 47 lists the JTAG timing parameters and values for Cyclone V devices. Table 46. Fast and Standard POR Delay Specification for Cyclone V Devices (1) Devices” table in the Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices chapter. Table 47. JTAG Timing Parameters and Values for Cyclone V Devices— Preliminary I/O bank = 2.5 V, or 13 ns if it equals 1.8 V.
encryption or the compression feature. Table 48 lists the DCLK-to-DATA[] ratio for each combination.
1 If the DCLK-to-DATA[] ratio is greater than 1, at the end of configuration, you can only
Table 48. DCLK-to-DATA[] Ratio for Cyclone V Devices— Preliminary
1 When you enable decompression or the design security feature, the DCLK-to-DATA[]
Figure 17. DCLK-to-DATA[] FPP Configuration Timing Waveform for Cyclone V Devices When the Ratio is 1 (1) nCONFIG is pulled low, a reconfiguration cycle begins. (2) After power up, the Cyclone V device holds nSTATUS low for the time of the POR delay. (3) After power up, before and during configuration, CONF_DONE is low. (4) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient. pin depends on the dual-purpose pin settings. (7) After the option bit to enable the INIT_DONE pin is configured into the device, INIT_DONE goes low.
when the DCLK-to-DATA[] ratio is 1. Table 49. DCLK-to-DATA[] FPP Timing Parameters for Cyclone V Devices When the Ratio is 1— Preliminary (1) You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. (2) You can obtain this value if you do not delay configuration by externally holding nSTATUS low. (3) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
DCLK-to-DATA[]ratio is more than 1. Table 50. DCLK-to-DATA[] FPP Timing Parameters for Cyclone V Devices when the Ratio is > 1 (1)— Preliminary (1) Use these timing parameters when you use decompression and the design security features. (2) This value can be obtained if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. (3) This value can be obtained if you do not delay configuration by externally holding nSTATUS low. (4) N is the DCLK-to-DATA[] ratio and f DCLK is the DCLK frequency of the system. (5) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
Table 53 lists the PS timing parameter for Cyclone V devices. Table 53. PS Timing Parameters for Cyclone V Devices— Preliminary (1) You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. (2) You can obtain this value if you do not delay configuration by externally holding nSTATUS low. (3) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
schemes, and the maximum frequency for Cyclone V devices. format, have different file sizes. targeted for the same device has the same uncompressed configuration file size. Table 55 lists the uncompressed raw binary file ( .rbf) sizes for Cyclone V devices. Table 54. Initialization Clock Source Option and the Maximum Frequency for Cyclone V Devices option in the Quartus II software from the General panel of the Device and Pin Options dialog box. Table 55. Uncompressed .rbf Sizes for Cyclone V Devices —Preliminary (Part 1 of 2)
estimated values are based on the configuration .rbf sizes in Table 55. (1) No PCIe hard IP , configuration via protocol (CvP) is not supported in this family. (2) This device will be supported in a future release of the Quartus II software. Table 55. Uncompressed .rbf Sizes for Cyclone V Devices —Preliminary (Part 2 of 2) Table 56. Minimum Configuration Time Estimation for Cyclone V Devices —Preliminary (Part 1 of 2)
Table 58 lists the frequency specifications for the user watchdog internal oscillator. (1) DCLK frequency of 100 MHz using external CLKUSR. (2) Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic. Table 56. Minimum Configuration Time Estimation for Cyclone V Devices —Preliminary (Part 2 of 2) Table 57. Remote System Upgrade Circuitry Timing Specification for Cyclone V Devices— megafunction, the clock user-supplied to the ALTREMOTE_UPDATE megafunction must meet this specification. section in the Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices chapter. Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices chapter. Table 58. User Watchdog Internal Oscillator Frequency Specifications for Cyclone V Devices—
of the timing budget as part of the link timing analysis. data based on the specifics of the design after you complete place-and-route. Devices Documentation webpage. Table 59 lists the Cyclone V IOE programmable delay settings. the output buffer. The default delay is 0 ps. Table 59. IOE Programmable Delay for Cyclone V Devices Table 60. Programmable Output Buffer Delay for Cyclone V Devices (1)— Preliminary (1) Pending data extraction from the Quartus II software.
Table 61 lists the glossary for this datasheet. Table 61. Glossary Table (Part 1 of 4) HSCLK Left/right PLL input clock frequency.
J High-speed I/O block—Deserialization factor (width of parallel data bus). (1) Core Clock can only be fed by dedicated clock input pins or PLL outputs. using simulation results, process data, and other known parameters. temperature conditions. There are no preliminary designations on finalized tables. L Receiver differential input discrete resistor (external to the Cyclone V device). Table 61. Glossary Table (Part 2 of 4)
receiver changes to the new logic state. The new logic state is then maintained as long as the input stays beyond the DC threshold. C High-speed receiver/transmitter input and output clock period. the TCCS measurement (refer to the Timing Diagram figure under SW in this table). High-speed I/O block—Duty cycle on high-speed transmitter output clock. The timing budget allowed for skew, propagation delays, and the data sampling window. Table 61. Glossary Table (Part 3 of 4)
Table 62 lists the revision history for this document. VCM(DC) DC common mode input voltage. VICM Input common mode voltage—The common mode of the differential signal at the receiver. complementary conductors of a differential transmission at the receiver. VDIF(AC) AC differential input voltage—Minimum AC input differential voltage required for switching. VDIF(DC) DC differential input voltage— Minimum DC input differential voltage required for switching. complementary conductors of a differential transmission at the transmitter. Table 61. Glossary Table (Part 4 of 4) Table 62. Document Revision History (Part 1 of 2) ■ Updated Table 20, Table 27, and Table 34. ■ Updated “UART Interface” and “CAN Interface” sections. ■ Updated Figure 5, Figure 6, Figure 17, Figure 19, and Figure 20. Table 32, Table 35, Table 36, Table 43, Table 53, Table 54, Table 57, and Table 61.
■ Added HPS reset information in the “HPS Specifications” section. ■ Updated Table 1, Table 2, Table 17, Table 20, Table 52, and Table 56. January 2013 3.1 Updated Table 4, Table 20, and Table 56. Table 20, Table 25, Table 28, Table 52, Table 55, Table 56, and Table 59. ■ Removed table: Transceiver Block Jitter Specifications for Cyclone V GX Devices. ■ Added “HPS Specifications” section. Table 41, Table 42, Table 43, Table 44, Table 45, and Table 46. Figure 12, Figure 13, Figure 14, Figure 15, and Figure 16. ■ Removed “Power Consumption” section. ■ Added Table 22, Table 23, and Table 29. ■ Added Figure 1 and Figure 2. ■ Added “Initialization” and “Configuration Files” sections. ■ Added automotive speed grade information. Table 2–30, Table 2–35, and Table 2–43. ■ Updated Table 2–3, Table 2–4, Table 2–11, Table 2–13, Table 2–20, and Table 2–21. October 2011 1.0 Initial release. Table 62. Document Revision History (Part 2 of 2)