HS-3282 RENESAS

Document overview

  • Manufacturer or author: Provided By digicamel.com
  • PDF pages: 19

Technical content

Features

  • ARlNC Specification 429 Compatible
  • Data Rates of 100 Kilobits or 12.5 Kilobits
  • Separate Receiver and Transmitter Section
  • Dual and Independent Receivers, Connecting Directly to ARINC Bus
  • Serial to Parallel Receiver Data Conversion
  • Parallel to Serial Transmitter Data Conversion
  • Word Lengths of 25 or 32 Bits
  • Parity Status of Received Data
  • Generate Parity of Transmitter Data
  • Automatic Word Gap Timer
  • Single 5V Supply
  • Low Power Dissipation
  • Full Military Temperature Range
  • REFERENCE AN400

FN2964 Rev.2.02 Page 2 of 18 Feb 11, 2022

Ordering Information

NUMBER (Note 1) PART NUMBER PACKAGE DESCRIPTION PKG. DWG. # TEMP . RANGE N/A HS4-3282-8 44 Ld CLCC, Solder Seal J44.A -55 to +125°C 5962-8688001QA 5962-8688001QA 40 Ld CERDIP , Solder Seal F40.6 N/A HS1-3282-8 40 Ld CERDIP , Solder Seal F40.6 NOTES: 1. Specifications for Rad Hard QML device s are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed must be used when ordering. Pinouts HS-3282 (CERDIP) TOP VIEW HS-3282 (CLCC) TOP VIEW VDD 429DI1(A) 429DI1(B) 429DI2(A) 429DI2(B) D/R1 D/R2 SEL EN1 EN2 BD15 BD14 BD13 BD12 BD11 BD10 BD09 BD08 BD07 BD06 NC MR TX CLK CLK NC NC CWSTR ENTX 429D0 429D0 TX/R PL2 PL1 BD00 BD01 BD02 BD03 BD04 BD05 GND 46 3 BD15 BD12 NC D/R1 BD14 EN2 BD11 NC NC CWSTR ENTX 429D0 429D0 TX/R PL2 PL1 BD01 BD00 NC 429DI2(B) TXCLK CLK 429DI2(A) NC NC BD10 BD09 BD08 BD07 BD06 BD04 BD03 GND BD02 BD05 429DI1(A) SEL EN1 4041424344 2827262524232221201918 VDD BD13 D/R2 429DI1(B) MR NC

FN2964 Rev.2.02 Page 3 of 18 Feb 11, 2022 Pin Description PIN SYMBOL SECTION DESCRIPTION 1V CC Recs/Trans Supply pin 5 volts 5%. 2 429 DI1 (A) Receiver ARlNC 429 data input to Receiver 1. 3 429 DI1 (B) Receiver ARlNC 429 data input to Receiver 1. 4 429 Dl2 (A) Receiver ARINC 429 data input to Receiver 2. 5 429 DI2 (B) Receiver ARINC 429 data input to Receiver 2. 6D / R 1 Receiver Device ready flag output from Receiver 1 i ndicating a valid data word is ready to be fetched. 7D / R 2 Receiver Device ready flag output from Receiver 2 i ndicating a valid data word is ready to be fetched. 8 SEL Receiver Bus Data Selector - Input signal to select one of two 16-bit words from either Receiver 1 or 2. 9E N 1 Receiver Input signal to enable data from Receiver 1 onto the data bus. 10 EN2 Receiver Input signal to enable data from Receiver 2 onto the data bus. 11 BD15 Recs/Trans Bi-directional data bus fo r fetching data from either of the Rece ivers, or for loading data into the Transmitter memory or control word register. See Control Word Table for description of Control Word bits. 12 BD14 Recs/Trans See Pin 11. 13 BD13 Recs/Trans See Pin 11. 14 BD12 Recs/Trans See Pin 11. 15 BD11 Recs/Trans See Pin 11. 16 BD10 Recs/Trans See Pin 11. 17 BD09 Recs/Trans See Pin 11. 18 BD08 Recs/Trans See Pin 11. 19 BD07 Recs/Trans See Pin 11. 20 BD06 Recs/Trans See Pin 11. 21 GND Recs/Trans Circuit Ground. 22 BD05 Recs/Trans See Pin 11. 23 BD04 Recs/Trans See Pin 11. Cont rol Word function not applicable. 24 BD03 Recs/Trans See Pin 11. Cont rol Word function not applicable. 25 BD02 Recs/Trans See Pin 11. Cont rol Word function not applicable. 26 BD01 Recs/Trans See Pin 11. Cont rol Word function not applicable. 27 BD00 Recs/Trans See Pin 11. Cont rol Word function not applicable.

28 PL1

Transmitter Parallel load input si gnal loading the first 16-bit word into the Transmitter memory. 29 PL2 Transmitter Parallel load input signal loading the first 16-bit word into the Transmitter memory and initiates data transfer into the memory stack. 30 TX/R Transmitter Transmitter flag output to indicate the memory is empty.

FN2964 Rev.2.02 Page 4 of 18 Feb 11, 2022 Pinout 31 429D0 Transmitter Data output from Transmitter 32 429D0 Transmitter Data output from Transmitter. 33 ENTX Transmitter Transmitter Enable input signal to initiate data transmission from FIFO memory. 34 CWSTR Recs/Trans Control word input strobe signal to latch t he control word from the databus into the control word register. 35 - - No connection. Must be left open. 36 - - No connection. Must be left open or tied low but never tied high. 37 CLK Recs/Trans External clock input. May be either ten (10) or eighty (80) times the data rate. If using both ARINC data rates it must be ten (10) times the highest data rate, (typically 1MHz). 38 TXCLK Transmitter Transmitter Clock output. Delivers a clock frequency equal to the transmitter data rate. 39 MR Recs/Trans Master Reset. Active low pulse used to rese t FIFO, bit counters, gap timer, word count signal, TX/R and various other flags and controls. Master reset does not reset the control word register. Usually only used on Power-Up or System Reset. 40 - - No Connection. Pin Description (Continued) PIN SYMBOL SECTION DESCRIPTION 28 40 393837363534333231302927262524232221 13 1 2345678910111214151617181920 NCNC NC

Word Strobe (CWSTR) signal going to a logic “1”. BD05 SLFTST Connects the self test signal from the transmitter dire ctly to the receiver shift registers, bypassing the input receivers. Receiver 1 receives Data True and Receiver 2 receives Data Not. Note that the transmitter output remains active. (Logic “0” on SLFTST Enables Self Test). BD06 SDENB1 Signal to Activate the Source/Destination (S/D) Decoder for Receiver 1. (Logic “1” activates S/D Decoder). cepted by the Receiver 1. If SDENB1 = “0” this bit becomes a don’t care. accepted by the Receiver 1. If SDENB1 = “0” this bit becomes a don’t care. BD09 SDENB2 Signal to activate the Source/Destination (S/D) Decoder for Receiver 2. (Logic “1” activates S/D Decoder). cepted by the Receiver 2. If SDENB2 = “0” this bit becomes a don’t care. accepted by the Receiver 2. If SDENB2 = “0” this bit becomes a don’t care. by ten (10). If TXSEL = “1” then transmitter data rate is equal to the clock rate divided by eighty (80). TABLE 1. ARINC 429 32-BIT DATA FORMAT

11 LSB

28 MSB

29 Sign

32 Parity Status

13 LSB 11

8 Parity Status 32

partially received data word. No Source/Destination (S/D) in 25-Bit format.

  • T h e Line Receiver functions as a voltage level translator. It transforms the 10 volt differ ential line voltage, ARINC 429 format, into 5 volt internal logic level.
  • The output of the Line Receiver is one of two inputs to the Self-Test Data Selector (SEL). The other input to the Data Selector is the Self-Test Signal from the Transmitter section.
  • The incoming data, either Self-Test or ARlNC 429, is double sampled by the Word Gap Timer to generate a Data Clock. The Receiver sample frequency (RCVCLK), 1MHz, or 125kHz, is generated by the Receiver/Transmitter Timing Circuit. This sampling frequency is ten times the Data Rate to ensure no data ambiguity.
  • The derived data clock then shifts the data down a 32-Bit long Data Shift Register (Data S/RI). The Data Word Length is selectable for either 25 Bits or 32 Bits long by the Control Signal (WLSEL). As soon as the data word is completely received, an internal signal (WDCNT1) is gener- ated by the Word Gap Timer Circuit.
  • The Source/Destination (S/D) Decoder compares the user set code (X and Y) with Bits 9 and 10 of the Data Word. If the two codes are matched, a positive signal is generated to enable the WDCNT1 signal to latch in the received data. Otherwise, the data word is ignored and no latching action takes place. The S/D Decoder can be Enabled and Disabled by the control signal S/D ENB. If the data word is latched, an indicator flag (D/R1 ) is set. This indicates a valid data word is ready to be fetched by the user.
  • After the receiver data has been shifted down the shift register, it is placed in a holding register. The device ready flag will then be set indicating that data is ready to be fetched. If the data is ignored and left in the holding register, it will be written over when the next data word is received.
  • The received data in the 32-bit holding register is placed on the bus in the form of two (2)16-bit words regardless of whether the format is for 32 or 25-bit data words. Either word can be accessed first or repeatedly until the next received data word falls into the holding register.
  • The parity of the incoming word is checked and the status (i.e., logic “0” for odd parity and logic “1” for even parity) stored in the receiver latch and output on BD08 during the Word No. 1.
  • Assuming the user desires to access the data, he first sets the Data Select Line (SEL) to a Logic “0” level and pulses the Enable (EN1 ) line. This action causes the Data Selector (SELl) to select the first-data word, which contains the label field and Enable it onto the Data Bus. To obtain the second data word, the user sets the SEL line to a Logic “1” level and pulse the Enable (EN1 ) line again. The Enable pulse dura- tion is matched to the user circuit requirement needed to read the Data Word from the Data Bus. The second Enable pulse is also used to reset the Device Ready (D/R1) flip-flop. This completes a receiving cycle. TABLE 2B. WORD 2 FORMAT BI-DIRECTIONAL BlT# FUNCTION ARINC BIT#

15 Sign 29

14 MSB 28

TABLE 3. ARINC 25-BIT DATA FORMAT

24 MSB

25 Parity Status

8 Parity Status 25

15 MSB 24

FN2964 Rev.2.02 Page 7 of 18 Feb 11, 2022 Transmitter Operation The Transmitter section consists of an 8-word deep by 31- Bit long FIFO Memory, Parity Generator, Transmitter Word Gap Timing Circuit and Driver Circuit.

  • The FlFO Memory is organized in such a way that data loaded in the input register is automatically transferred to the output register for Serial Data Transmission. This eliminates a large amount of data managing time since the data need not be clocked from the input register to the output register. The FIFO input register is made up of two sets of 16 D-type flip-flops, which are clocked by the two parallel load signals (PL1 and PL2 ). PL1 must always precede PL2. Multiple PL1’s may occur and data will be written over. As soon as PL2 is received, data is transferred to the FIFO. The data from the Data Bus is clocked into the D-type flip-flop on the positive going edge of the PL signals. If the FIFO memory is initially empty, or the stack is not full, the data will be automatically transferred down the Memory Stack and into the output register or to the last empty FIFO storage register. If the Transmitter Enable signal (ENTX) is not active, a Logic “0”, the data remains at the output regis- ter. The FIFO Memory has storage locations to hold eight 31-bit words. If the memory is full and the new data is again strobed with PL , the old data at the input register is written over by the new data. Data will remain in the Memory until ENTX goes to a Logic “1”. This activates the FIFO Clock and data is shifted out serially to the Transmitter Driver. Data may be loaded into the FIFO only while ENTX is inac- tive (low). It is not possible to write data into the FIFO while transmitting. WARNING: If PL1 or PL2 is applied while ENTX is high, i.e., while transmitting, the FlFO may be dis- rupted such that it would require a MR (Master Reset) sig- nal to recover.
  • The Output Register of the FIFO is designed such that it can shift out a word of 24 Bits long or 31 Bits long. This word length is again controlled by the WLSEL bit. The TX word Gap Timer Circuit also automatically inserts a gap equivalent to 4-Bit Times between each word. This gives a minimum requirement of 29-Bit time or 36-Bit time for each word transmission. Assuming the signal, ENTX, remains at a Logic “1”, a transfer to stack signal is generated to transfer the data down the Memory Stack one position. This action is continued until the last word is shifted out of the FIFO memory. At this time a Transmitter Ready (TX/R) flag is generated to signal the user that the Transmitter is ready to receive eight more data words. During transmis- sion, if ENTX is taken low then high again, transmission will cease leaving a portion of the word untransmitted, and the data integrity of the FIFO will be destroyed.
  • A Bit Counter is used to detect the last Bit shifted out of the FIFO memory and appends the Parity Bit generated by the Parity Generator. The Parity Generator has a control signal, Parity Check (PARCK), which establishes whether odd or even parity is used in the output data word. PARCK set to a logic “0” will result in odd parity and when set to a logic “1” will result in even parity. Sample Interface Technique From Figure 1, one can see that the Data Bus is time shared between the Receiver and Transmitter. Therefore, bus controlling must be synchronously shared between the Receiver and the Transmitter. Figure 2 shows the typical interface timing control of the ARlNC Chip for Receiving function and for Transmitting function. Timing sequence for loading the Transmitter FIFO Memory is shown in Timing Interval A. A transmitter Ready (TX/R) Flag signals the user that the Transmitter Memory is empty. The user then Enables the Transmitter Data, a 16-Bit word, on the Data Bus and strobes the Transmitter with a Parallel Load (PL1 ) Signal. The second part of the 32-Bit word is similarly loaded into the Transmitter with PL2, which also initiates data transfer to stack. This is continuous until the Memory is full, which is eight 31-Bit words. The user must keep track of the number of words loaded into the Memory to ensure no data is written over by other data. During the time the user is loading the Transmitter, he does not have to service the Receiver, even if the Receiver flags the user with the signal D/R1 that a valid received word is ready to be fetched. This is shown by the Timing interval B. If the user decides to obtain the received data before the Transmitter is completely loaded, he sets the two parallel load signals (PL1 and PL2) at a Logic “1” state, and strobes EN1 while the signal SEL is at a Logic “0” state. After the negative edge of EN1, the first 16-Bit segment of the received word becomes valid on the Data Bus. At the positive edge of EN1 , the user should toggle the signal SEL to ready the Receiver for the second 16-Bit word. Strobing the Receiver with EN1, the second time, enables the second 16-Bit word and resets the Receiver Ready Flag D/R1. The user should now reset the signal SEL to a Logic “0” state to ready the Receiver for another Read Cycle. During the time period that the user is fetching the received words, he can load the transmitter. This is done by interlacing the PL signals with the EN signals as shown in the Timing Interval B. Servicing the Receiver 2 is similar and is illustrated by Timing interval C. Timing interval D shows the rest of the Transmitter loading sequence and the beginning of the transmission by switching the signal TX Enable to a Logic “1” state. Timing interval E is the time it takes to transmit all data from the FlFO Memory, either 288 Bit times or 232 Bit times. Repeater Operation This mode of operation allows a data word that has been received to be placed directly in the FIFO for transmission. A timing diagram is shown in Figure 7. A 32-bit word is used in this example. The data word is shifted into the shift register and the D/R flag goes low. A logic “0” is placed on the SEL line and EN1 is strobed. This is the same as the normal receiver operation and places half the data word (16 bits) on the data bus. By strobing PL1 at the same time as EN1, these 16 bits will be taken off the bus and placed in the FIFO. SEL is brought back high and EN1 is strobed again for the second 16 bits of the data word. Again by strobing PL2 at the same time the second 16 bits will be placed in the FIFO. The parity bit will have been stripped away leaving the 31-bit

FIGURE 1. SINGLE CHIP ARINC 429 INTERFACE FUNCTIONAL BLOCK DIAGRAM

16 SEL 1

FN2964 Rev.2.02 Page 9 of 18 Feb 11, 2022 Absolute Maximum Ratings Thermal Information Input, Output or I/O Voltage Applied Operating Conditions Operating Temperature Range Thermal Resistance JA (oC/W) JC (oC/W) Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TA = -55oC to +125oC (HS-3282-8) PARAMETER SYMBOL CONDITIONS LIMITS UNITSMIN MAX ARlNC INPUTS Pins 2-3,4-5 Logic “1” Input Voltage V lH VDD = 5.25V 6.7 13.0 V Logic “0” Input Voltage V IL VDD = 5.25V -13.0 -6.7 V Null Input Voltage V NUL VDD = 4.75V, 5.25V -2.5 +2.5 V Common Mode Voltage V CH VDD = 4.75V, 5.25V -5.0 +5.0 V Input Leakage I lH VDD = 5.25V, VIN = 6.5V - 200 A Input Leakage I lL VDD = 5.25V, VIN = 0.0V -450 - A Differential Input Impedance RI V DD = 5.25V, VIN = +5V, -5V 12 - k  Input lmpedance to VDD RH V DD = 5.25V, VlN = 0V 12 - k  Input lmpedance to GND RG V DD = Open, VlN = 5.0V 12 - k  BIDIRECTIONAL INPUTS Pins 11-20, 22-27 Logic “1” Input Voltage V IH VDD = 5.25V 2.1 - V Logic “0” Input Voltage V IL VDD = 4.75V - 0.7 V Input Leakage l IH VDD = 5.25V,VIN = 5.25V - 1.5 A Input Leakage I lL VDD = 5.25V, VIN = 0.0V -1.5 - A ALL OTHER INPUTS Pins 8-10, 28, 29, 33, 34, 37, 39 Logic “1” Input Voltage V IH VDD = 5.25V 3.5 - V Logic “0” Input Voltage V IL VDD = 4.75V - 0.7 V Input Leakage I lH VDD = 5.25V, VIN = 5.25V - 10 A Input Leakage I lL VDD = 5.25V, VIN = 0.0V -75 - A OUTPUTS Pins 6, 7, 11-20, 22-27, 30-32, 38, Supply Pin 1 Logic “1” Output Voltage V OH VDD = 4.75V, IOH = -1.5mA 2.7 - V Logic “0” Output Voltage V OL VDD = 4.75V lOL= 1.8mA - 0.4 V Standby Supply Current l CC1 VDD = 5.25V, VIN = 0V Except 9,10, 29 = 5.25V -2 0 m A Operating Supply Current l CC2 VDD = 5.25V, VIN = 5.25V Except 8, 33 = 0.0V, CLK = 1MHz -2 0 m A

FN2964 Rev.2.02 Page 10 of 18 Feb 11, 2022 TA = -55oC to +125oC (HS-3282-8) PARAMETER SYMBOL CONDITIONS LIMITS UNITSMIN MAX Clock Frequency FC V DD = 4.75V, 5.25V - 1 MHz Data Rate 1/ FD V DD = 4.75V, 5.25V - 100 kHz Data Rate 2/ FD V DD = 4.75V, 5.25V - 12.5 kHz Master Reset Pulse Width TMR V DD = 4.75V, 5.25V 200 - ns RECEIVER TIMING Receiver Ready Time From 32nd Bit 1/ TD/R2 V DD = 4.75V, 5.25V - 16 s Receiver Ready Time From 32nd Bit 2/ TD/R2 V DD = 4.75V, 5.25V - 128 s Device Ready to Enable Time TD/REN V DD = 4.75V, 5.25V 0 - ns Data Enable Pulse Width TEN V DD = 4.75V, 5.25V 200 - ns Data Enable to Data Enable Time TENEN V DD = 4.75V, 5.25V 50 - ns Data Enable to Device Ready Reset Time TEND/R V DD = 4.75V, 5.25V - 200 ns Output Data Valid to Enable Time TENDATA V DD = 4.75V, 5.25V - 200 ns Data Enable to Data Select Time TENSEL V DD = 4.75V, 5.25V 20 - ns Data Select to Data Enable Time TSELEN V DD = 4.75V, 5.25V 20 - ns Output Data Disable Time TDATAEN V DD = 4.75V, 5.25V - 80 ns CONTROL WORD TIMING Control Word Strobe Pulse Width TCWSTR V DD = 4.75V, 5.25V 130 - ns Control Word Setup Time TCWSET V DD = 4.75V, 5.25V 130 - ns Control Word Hold Time TCWHLD V DD = 4.75V, 5.25V 0 - ns TRANSMITTER FIFO Write Timing Parallel Load Pulse Width TPL V DD = 4.75V, 5.25V 200 - ns Parallel Load to Parallel Load 2 Delay TPL12 V DD = 4.75V, 5.25V 0 - ns Transmitter Ready Delay Time TTX/R V DD = 4.75V, 5.25V - 840 ns Data Word Setup Time TDWSET V DD = 4.75V, 5.25V 110 - ns Data Word Hold Time TDWHLD V DD = 4.75V, 5.25V 0 - ns TRANSMITTER Output Timing Enable Transmit to Output Data Valid Time 1/ TENDAT V DD = 4.75V, 5.25V - 25 s Enable Transmit to Output Data Valid Time 2/ TENDAT V DD = 4.75V, 5.25V - 200 s Output Data Bit Time 1/ TBlT V DD = 4.75V, 5.25V 4.95 5.05 s Output Data Bit Time 2/ TBlT V DD = 4.75V, 5.25V 39.6 40.4 s Output Data Null Time 1/ TNULL V DD = 4.75V, 5.25V 4.95 5.05 s Output Data Null Time 2/ TNULL V DD = 4.75V, 5.25V 39.6 40.4 s

FN2964 Rev.2.02 Page 11 of 18 Feb 11, 2022 Data Word Gap Time 1/ TGAP V DD = 4.75V, 5.25V 39.6 40.4 s Data Word Gap Time 2/ TGAP V DD = 4.75V, 5.25V 316.8 323.2 s Data Transmission Word to TX/R Set Time TDTX/R V DD = 4.75V, 5.25V - 400 ns Enable Transmit Turnoff Time TENTX/R V DD = 4.75V, 5.25V 0 - ns REPEATER OPERATION TIMING Data Enable to Parallel Load Delay Time TENPL V DD = 4.75V, 5.25V 0 - ns Data Enable Hold for Parallel Load Time TPLEN V DD = 4.75V, 5.25V 0 - ns Enable Transmit Delay Time TTX/REN V DD = 4.75V, 5.25V 0 - ns NOTES: 1. 100kHz Data Rate. 2. 12.5kHz Data Rate. Electrical Performance Specifications VDD = 5V 5%, TA = 0oC to +70oC (HS-3282-5), TA = -55oC to +125oC (HS-3282-8) PARAMETER SYMBOL (NOTE 1) CONDITIONS LIMITS UNITSMIN MAX Differential Input Capacitance CD V DD = Open, f = 1MHz, Note 2, 3 - 20 pF Input Capacitance to VDD CH V DD = GND, f = 1MHz, Note 2, 3 - 20 pF lnput Capacitance to GND CG V DD = Open, f = 1MHz, Note 2, 3 - 20 pF Input Capacitance Cl V DD = Open, f = 1MHz, Note 2, 4 - 15 pF Output Capacitance CO V DD = Open, f = 1MHz, Note 2, 5 - 15 pF Clock Rise Time TLHC CLK = 1MHz, From 0.7V to 3.5V - 10 ns Clock Fall Time THLC CLK = 1MHz, From 3.5V to 0.7V - 10 ns Input Rise Time TLHI From 0.7V to 3.5V, Note 6 - 15 ns Input Fall Time THLI From 3.5V to 0.7V, Note 6 - 15 ns NOTES: 1. The parameters listed in this table ar e controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after major process and/or design changes affecting these parameters. 2. All measurements are referenced to device GND. 3. Pins 2-3, 4-5. 4. Pins 8-10, 28, 29, 33, 34, 37, 39. 6. Pins 8-20, 22-29, 33, 34. TA = -55oC to +125oC (HS-3282-8) (Continued) PARAMETER SYMBOL CONDITIONS LIMITS UNITSMIN MAX

FIGURE 7. REPEATER OPERATION TIMING

FN2964 Rev.2.02 Page 15 of 18 Feb 11, 2022 Burn-In Circuits HS-3282 CERDIP VDD DI1(A) DI1(B) DI2(A) DI2(B) D/R1 D/R2 SEL EN1 EN2 BD15 BD14 BD13 BD12 BD11 BD10 BD09 BD08 BD07 BD06 NC MR TX CLK CLK NC NC CWSTR ENTX 429D0 429D0 TX/R PL2 PL1 BD00 BD01 BD02 BD03 BD04 BD05 GND F10 F11 F12 F13 F14 F15 VDD NC NC GND GND GND NC NC NC NC GND VDD NC NC NC F15 VDDC

FN2964 Rev.2.02 Page 16 of 18 Feb 11, 2022 HS-3282 CLCC NOTES: 1. Resistors = 47k , 5%, 1/4W (Min) 2. GND = Ground 4. C = 0.01mF/Socket (Min) 5. F0 = 100kHz, F1 = F0/2, . . . F15 = F14/2 Burn-In Circuits 46 3 BD15 BD12 NC D/R1 BD14 EN2 BD11 NC NC CWSTR ENTX TX/R PL2 PL1 BD01 BD00 NC DI2(B) TXCLK CLK DI2(A) NC NC BD10 BD09 BD08 BD07 BD06 BD04 BD03 GND BD02 BD05 DI1(A) SEL EN1 4041424344 2827262524232221201918 VCC BD13 D/R2 DI1(B) MR NC NC NC NC VDD F15 F14 F13 F12 F11 NC NC V DD GND NC NC NC VDD GND NC F15 NC NC GND GND NCNC F10 F09 F08 F07 F06 GND F05 F04 F03 F02 C

FN2964 Rev.2.02 Page 17 of 18 Feb 11, 2022 Die Characteristics DIE DIMENSIONS: 224 mils x 246 mils x 14 mils) (5700µm x 6250µm x 355.6µm) METALLIZATION: Type: Si-Al Thickness: 11kÅ 2kÅ GLASSIVATION: Type: SiO2 Thickness: 8kA 1kÅ WORST CASE CURRENT DENSITY: 2 x 105 A/cm2 Metallization Mask Layout HS-3282 (2) 429DI1(A) (36) N/C (26) BD01 (4) 429DI2(A) (5) 429DI2(B) BD09 (17) BD15 (11) SEL (8) D/R2 (7) (3) 429DI1(B) (1) VDD (39) MR (37) CLK (38) TX CLK EN1 (9) EN1 (10) BD14 (12) BD13 (13) BD12 (14) BD11 (15) D/R1 (6) BD08 (18) BD07 (19) BD06 (20) GND (21) BD05 (22) BD04 (23) BD03 (24) BD02 (25) BD10 (16) (34) CWSTR (33) ENTX (32) 429D0 (31) 429D0 (35) N/C (30) TX/R (29) PL2 (28) PL1 (27) BD00

FN2964 Rev.2.02 Page 18 of 18 Feb 11, 2022

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit our website to make sure you have the latest revision. DATE REVISION CHANGE Feb 11, 2022 2.02 Removed Related Literature section. Updated Ordering Information table by adding note and formatting. Updated Metallization Mask Layout Diagram Feb 28, 2020 2.01 Updated Ordering Information table. Added Revision History Updated disclaimer.

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