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SMJ320C6203 TI

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/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 /C0068High-Performance Fixed-Point Digital Signal Processor (DSP) – SMJ320C62x – 5-ns Instruction Cycle Time – 200-MHz Clock Rate – Eight 32-Bit Instructions/Cycle – 1600 Million Instructions Per Second (MIPS) /C0068429-Pin Ball Grid Array (BGA) Package (GLP Suffix) /C0068VelociTI Advanced Very-Long-Instruction- Word (VLIW) C62x DSP Core – Eight Highly Independent Functional Units: – Six Arithmetic Logic Units (ALUs) (32-/40-Bit) – Two 16-Bit Multipliers (32-Bit Result) – Load-Store Architecture With 32 32-Bit General-Purpose Registers – Instruction Packing Reduces Code Size – All Instructions Conditional /C0068Instruction Set Features – Byte-Addressable (8-, 16-, 32-Bit Data) – 8-Bit Overflow Protection – Saturation – Bit-Field Extract, Set, Clear – Bit-Counting – Normalization /C00687M-Bit On-Chip SRAM – 3M-Bit Internal Program/Cache (96K 32-Bit Instructions) – 4M-Bit Dual-Access Internal Data (512K Bytes) – Organized as Two 256K-Byte Blocks for Improved Concurrency /C0068Flexible Phase-Locked-Loop (PLL) Clock Generator /C006832-Bit External Memory Interface (EMIF) – Glueless Interface to Synchronous Memories: SDRAM or SBSRAM – Glueless Interface to Asynchronous Memories: SRAM and EPROM – 52M-Byte Addressable External Memory Space /C0068Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel /C006832-Bit Expansion Bus – Glueless/Low-Glue Interface to Popular PCI Bridge Chips – Glueless/Low-Glue Interface to Popular Synchronous or Asynchronous Microprocessor Buses – Master/Slave Functionality – Glueless Interface to Synchronous FIFOs and Asynchronous Peripherals /C0068Three Multichannel Buffered Serial Ports (McBSPs) – Direct Interface to T1/E1, MVIP, SCSA Framers – ST-Bus-Switching Compatible – Up to 256 Channels Each – AC97-Compatible – Serial-Peripheral Interface (SPI) Compatible (Motorola ) /C0068Two 32-Bit General-Purpose Timers /C0068IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible /C00680.15-µm/5-Level Metal Process – CMOS Technology /C00683.3-V I/Os, 1.5-V Internal /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SMJ320C62x, VelociTI, and C62x are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc. All trademarks are the property of their respective owners. † IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. Copyright  2002, Texas Instruments Incorporated /C0079/C0110 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0109/C0112/C0108/C0105/C0097/C0110/C0116 /C0116/C0111 /C0077/C0073/C0076/C0262/C0080/C0082/C0070/C0262/C0051/C0056/C0053/C0051/C0053/C0044 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115 /C0097/C0114/C0101 /C0116/C0101/C0115/C0116/C0101/C0100 /C0117/C0110/C0108/C0101/C0115/C0115 /C0111/C0116/C0104/C0101/C0114/C0119/C0105/C0115/C0101 /C0110/C0111/C0116/C0101/C0100/C0046 /C0079/C0110 /C0097/C0108/C0108 /C0111/C0116/C0104/C0101/C0114 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115/C0044 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002

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signal descriptions 19/C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 absolute maximum ratings over operating case electrical characteristics over recommended ranges of supply voltage and operating case temperature 37. . GLP BGA package (bottom view) GLP 429-PIN BALL GRID ARRAY (BGA) PACKAGE (BOTTOM VIEW) 2119 1816 15 171311 10 12 14 W Y AA V T U P M N R L J K G E F H D B C A 1 9

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

description

The SMJ320C6203 device is part of the SMJ320C62x fixed-point DSP generation in the SMJ320C6000 DSP platform. The C62x DSP devices are based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. The SMJ320C62x  DSP offers cost-effective solutions to high-performance DSP-programming challenges. The SMJ320C6203 has a performance capability of up to 1600 MIPS at a clock rate of 200 MHz. The C6203 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6203 can produce two multiply-accumulates (MACs) per cycle for a total of 400 million MACs per second (MMACS). The C6203 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The C6203 device program memory consists of two blocks, with a 256K-byte block configured as memory-mapped program space, and the other 128K-byte block user-configurable as cache or memory-mapped program space. Data memory for the C6203 consists of two 256K-byte blocks of RAM. The C6203 device has a powerful and diverse set of peripherals. The peripheral set includes three multichannel buffered serial ports (McBSPs), two general-purpose timers, a 32-bit expansion bus that offers ease of interface to synchronous or asynchronous industry-standard host bus protocols, and a glueless 32-bit external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals. The C62x devices have a complete set of development tools that includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution. device characteristics Table 1 provides an overview of the SMJ320C6203 DSP. The table shows significant features of the device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count. This data sheet focuses on the functionality of the SMJ320C6203 device. For more details on the C6000 DSP part numbering, see Figure 4. SMJ320C6000 and C6000 are trademarks of Texas Instruments. Windows is a registered trademark of the Microsoft Corporation.

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Table 1. Characteristics of the C6203 DSP

2 Blocks:

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 functional and CPU (DSP core) block diagram Multichannel Buffered Serial Port 1 Direct Memory Access Controller (DMA) (See Table 1) Test C62x CPU (DSP Core) Data Path B B Register File Program Access/Cache Controller Instruction Fetch Instruction Dispatch Instruction Decode Data Path A A Register File PLL (x1, x4, x6, x7, x8, Data Access Controller Power- Down Logic SDRAM or SBSRAM ROM/FLASH SRAM I/O Devices Synchronous FIFOs I/O Devices Timer 0 Timer 1 External Memory Interface (EMIF) Multichannel Buffered Serial Port 0 Multichannel Buffered Serial Port 2 Expansion Bus 32-Bit Internal Program Memory

2 Blocks Program/Cache

(384K Bytes) Control Registers Control Logic Internal Data Memory (512K Bytes) In-Circuit Emulation Interrupt Control Framing Chips: H.100, MVIP, SCSA, T1, E1 AC97 Devices, SPI Devices, Codecs HOST CONNECTION Master /Slave TI PCI2040 Power PC 683xx 960 C6203 Digital Signal Processors Peripheral Control Bus DMA Bus Boot Configuration Interrupt Selector † For additional details on the PLL clock module and specific options for the C6203 device, see Table 1 and the Clock PLL section of this data sheet.

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002

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CPU (DSP core) description The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C62x CPU from other VLIW architectures. The CPU features two sets of functional units. Each set contains four units and a register file. One set contains each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU [see the functional and CPU (DSP core) block diagram and Figure 1]. The four functional units on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle, register access using the register file across the CPU supports one read and one write per cycle. Another key feature of the C62x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The C62x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the 256-bit-wide fetch-packet boundary, the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-, half-word, or word-addressable.

Figure 1. SMJ320C62x CPU (DSP Core) Data Paths

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of the TMS320C6000 Peripherals Reference Guide (literature number SPRU190). Table 2. 320C6203 Memory Map Summary

Table 3. EMIF Registers

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Table 4. DMA Registers

Table 5. Expansion Bus Registers Table 6. Interrupt Selector Registers Table 7. Peripheral Power-Down Control Register

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Table 8. McBSP 0 Registers Table 9. McBSP 1 Registers

Table 10. McBSP 2 Registers Table 11. Timer 0 Registers input clock cycles to count. Table 12. Timer 1 Registers input clock cycles to count.

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Peripherals Reference Guide (literature number SPRU190). Table 13. 320C6203 DMA Synchronization Events

00000 Reserved Reserved

00001 TINT0 Timer 0 interrupt

00010 TINT1 Timer 1 interrupt

00011 SD_INT EMIF SDRAM timer interrupt

00100 EXT_INT4 External interrupt pin 4

00101 EXT_INT5 External interrupt pin 5

00110 EXT_INT6 External interrupt pin 6

00111 EXT_INT7 External interrupt pin 7

01000 DMA_INT0 DMA channel 0 interrupt

01001 DMA_INT1 DMA channel 1 interrupt

01010 DMA_INT2 DMA channel 2 interrupt

01011 DMA_INT3 DMA channel 3 interrupt

01100 XEVT0 McBSP0 transmit event

01101 REVT0 McBSP0 receive event

01110 XEVT1 McBSP1 transmit event

01111 REVT1 McBSP1 receive event

10000 DSP_INT Host processor-to-DSP interrupt

10001 XEVT2 McBSP2 transmit event

10010 REVT2 McBSP2 receive event

10011 – 11111 Reserved Reserved. Not used.

registers: MUXH (address 0x019C0000) and MUXL (address 0x019C0004). Table 14. C6203 DSP Interrupts INT_02† – – Reserved Reserved. Do not use. INT_03† – – Reserved Reserved. Do not use. – – 10000 Reserved Reserved. Not used. – – 10011 – 11111 Reserved Reserved. Do not use. † Interrupts INT_00 through INT_03 are non-maskable and fixed. TMS320C6000 Peripherals Reference Guide (literature number SPRU190).

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Figure 2. CPU (DSP Core) Signals

Figure 3. Peripheral Signals

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Figure 3. Peripheral Signals (Continued)

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002 19POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 Signal Descriptions SIGNAL NAME PIN NO. TYPE † DESCRIPTIONNAME GLP TYPE † DESCRIPTION CLOCK/PLL CLKIN D10 I Clock input CLKOUT1 Y17 O Clock output at full device speed CLKOUT2 Y16 O Clock output at half (1/2) of device speed

Used for synchronous memory interface CLKMODE0 C12 I Clock mode selects
Selects what multiply factors of the input clock frequency the CPU frequency CLKMODE1 G10 I
Selects what multiply factors of the input clock frequency the CPU frequency equals. For more details on the CLKMODE pins and the PLL m ltipl factors for the C6203 de ice see the CLKMODE2 G12 I For more details on the CLKMODE pins and the PLL multiply factors for the C6203 device, see the Clock PLL section of this data sheet. PLLV ‡ B11 A§ PLL analog VCC connection for the low-pass filter PLLG ‡ A11 A§ PLL analog GND connection for the low-pass filter PLLF ‡ G11 A§ PLL low-pass filter connection to external components and a bypass capacitor JTAG EMULATION TMS W5 I JTAG test-port mode select (features an internal pullup) TDO R8 O/Z JTAG test-port data out TDI W4 I JTAG test-port data in (features an internal pullup) TCK V5 I JTAG test-port clock TRST R7 I JTAG test-port reset (features an internal pulldown) EMU1 T7 I/O/Z Emulation pin 1, pullup with a dedicated 20-kΩ resistor¶ EMU0 Y5 I/O/Z Emulation pin 0, pullup with a dedicated 20-kΩ resistor¶ RESET AND INTERRUPTS RESET J4 I Device reset NMI K2 I Nonmaskable interrupt
Edge-driven (rising edge) EXT_INT7 R4 External interrupts EXT_INT6 P6 I External interrupts
Edge-driven EXT_INT5 T2 I • Edge-driven
Polarity independently selected via the External Interrupt Polarity Register bits (EXTPOL [3 0])EXT_INT4 T3 yy y g (EXTPOL.[3:0]) IACK R2 O Interrupt acknowledge for all active interrupts serviced by the CPU INUM3 P4 INUM2 P1 O Active interrupt identification number
Valid during IACK for all active interrupts (not just external)INUM1 P2 O • Valid during IACK for all active interrupts (not just external)
Encoding order follows the interrupt-service fetch-packet ordering INUM0 N6
Encoding order follows the interru t-service fetch- acket ordering † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground ‡ PLLV, PLLG, and PLLF are not part of external voltage supply or ground. See the clock PLL section for information on how to connect these pins. § A = Analog Signal (PLL Filter) ¶ For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kΩ resistor. For boundary scan, pull down EMU1 and EMU0 with a dedicated 20-kΩ resistor.

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002

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Signal Descriptions (Continued) SIGNAL NAME PIN NO. TYPE † DESCRIPTIONNAME GNP TYPE † DESCRIPTION POWER-DOWN STATUS PD V3 O Power-down modes 2 or 3 (active if high) EXPANSION BUS XCLKIN C9 I Expansion bus synchronous host interface clock input XFCLK B9 O Expansion bus FIFO interface clock output XD31 D11 XD30 B13 XD29 F12 XD28 C13 XD27 D12 XD26 A14 XD25 B14 XD24 F13 XD23 B15 Expansion bus data XD22 C15 Ex ansion bus data

Used for transfer of data, address, and control Al t l i iti li ti f DSP d d i b t tXD21 D13 • Also controls initialization of DSP modes and expansion bus at reset [Note: For more information onpin control and boot configuration fields see the Boot Modes XD20 B16 [Note: For more information on pin control and boot configuration fields, see the Boot M odes and Configuration chapter of the TMS320C6000 Peripherals Reference Guide (literature XD19 B17 and Configuration cha ter of the TMS320C6000 Peri herals Reference Guide (literature number SPRU190)] XD18 D14 XD[30:16]– XCE[3:0]memory type XD17 F15 XD[30:16]– XCE[3:0] memory type XD13 – XBLAST polarity XD16 C17 I/O/Z XD13 XBLAST olarity XD12 – XW/R polarity XD11 Asynchronous or synchronous host operationXD15 G14 I/O/Z XD11 – Asynchronous or synchronous host operation XD10 – Arbitration mode (internal or external) XD14 D17 XD10 – Arbitration mode (internal or external) XD9 – FIFO mode XD13 C18 XD9 FIFO mode XD8 – Little endian/big endian XD7 SCRT select XD12 E18 XD7 – SCRT select XD [4:0] – Boot mode XD11 D18 XD[4:0] – Boot mode XD10 G15 All other expansion bus data pins not listed should be pulled down. XD9 D19 For proper operation, XD7 must be pulled down with a 10-kΩ resistor. The board design should be wired XD8 F16 For ro er o eration, XD7 must be ulled down with a 10-kΩ resistor. The board design should be wired such that a pullup or pulldown resistor can be used on XD7 for future applications. XD7 F19 XD6 E20 XD5 G16 XD4 H19 XD3 G20 XD2 J18 XD1 H20 XD0 H21 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002 21POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 Signal Descriptions (Continued) SIGNAL NAME PIN NO. TYPE † DESCRIPTIONNAME GLP TYPE † DESCRIPTION EXPANSION BUS (CONTINUED) XCE3 D3 XCE2 G6 O/Z Expansion bus I/O port memory space enables

Enabled by bits 28 29 and 30 of the word addressXCE1 D4 O/Z • Enabled by bits 28, 29, and 30 of the word address
Only one asserted during any I/Oport data access XCE0 E4
Only one asserted during any I/O ort data access XBE3 /XA5 F6 XBE2 /XA4 F7 I/O/Z Expansion bus multiplexed byte-enable control/address signals
Act as byte enable for hostport operation XBE1 /XA3 B5 I/O/Z • Act as byte-enable for host-port operation
Act as address for I/Oport operation XBE0 /XA2 C7
Act as address for I/O ort o eration XOE B7 O/Z Expansion bus I/O port output-enable XRE B8 O/Z Expansion bus I/O port read-enable XWE /XWAIT D7 O/Z Expansion bus I/O port write-enable and host-port wait signals XCS D8 I Expansion bus host-port chip-select input XAS G9 I/O/Z Expansion bus host-port address strobe XCNTL A9 I Expansion bus host control. XCNTL selects between expansion bus address or data register. XW/R F9 I/O/Z Expansion bus host-port write/read-enable. XW/R polarity is selected at reset. XRDY F4 I/O/Z Expansion bus host-port ready (active low) and I/O port ready (active high) XBLAST C5 I/O/Z Expansion bus host-port burst last-polarity selected at reset XBOFF C10 I Expansion bus back off XHOLD C4 I/O/Z Expansion bus hold request XHOLDA D6 I/O/Z Expansion bus hold acknowledge EMIF – CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY CE3 V18 CE2 W18 O/Z Memory space enables
Enabled by bits 24 and 25 of the word addressCE1 T15 O/Z • Enabled by bits 24 and 25 of the word address
Only one asserted during any external data access CE0 U18
Only one asserted during any external data access BE3 R15 Byte-enable control BE2 V19 O/Z Byte-enable control
Decoded from the two lowest bits of the internal address BE1 U20 O/Z • Decoded from the two lowest bits of the internal address
Byte-write enables for most types of memory C b di tl t d t SDRAM d d it k i l (SDQM)BE0 V16 yy y
Can be directly connected to SDRAM read and write mask signal (SDQM) † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002

22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

Signal Descriptions (Continued) SIGNAL NAME PIN NO. TYPE † DESCRIPTIONNAME GLP TYPE † DESCRIPTION EMIF – ADDRESS EA21 K18 EA20 K16 EA19 J20 EA18 K19 EA17 J21 EA16 K20 EA15 M19 EA14 L16 EA13 K21 EA12 M18 O/Z E ternal address ( ord address)EA11 L21 O/Z External address (word address) EA10 N18 EA9 M20 EA8 M16 EA7 R18 EA6 M21 EA5 N21 EA4 N16 EA3 P20 EA2 T18 EMIF – DATA ED31 V6 ED30 Y6 ED29 T8 ED28 Y7 ED27 Y8 ED26 V7 ED25 T9 ED24 AA8 ED23 V8 I/O/Z E ternal dataED22 Y9 I/O/Z External data ED21 AA9 ED20 V9 ED19 T10 ED18 Y10 ED17 W9 ED16 V10 ED15 T11 ED14 AA10 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002 23POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 Signal Descriptions (Continued) SIGNAL NAME PIN NO. TYPE † DESCRIPTIONNAME GLP TYPE † DESCRIPTION EMIF – DATA (CONTINUED) ED13 W10 ED12 W12 ED11 Y11 ED10 Y12 ED9 T12 ED8 AA13 ED7 R12 I/O/Z E ternal dataED6 V13 I/O/Z External data ED5 Y13 ED4 Y14 ED3 T13 ED2 Y15 ED1 R13 ED0 V14 EMIF – ASYNCHRONOUS MEMORY CONTROL ARE T20 O/Z Asynchronous memory read-enable AOE P16 O/Z Asynchronous memory output-enable AWE R20 O/Z Asynchronous memory write-enable ARDY R16 I Asynchronous memory ready input EMIF – SYNCHRONOUS DRAM (SDRAM)/SYNCHRONOUS BURST SRAM (SBSRAM) CONTROL SDA10 T14 O/Z SDRAM address 10 (separate for deactivate command) SDCAS /SSADS V17 O/Z SDRAM column-address strobe/SBSRAM address strobe SDRAS /SSOE W17 O/Z SDRAM row-address strobe/SBSRAM output-enable SDWE /SSWE W15 O/Z SDRAM write-enable/SBSRAM write-enable EMIF – BUS ARBITRATION HOLD T19 I Hold request from the host HOLDA T16 O Hold-request-acknowledge to the host TIMER 0 TOUT0 F2 O Timer 0 or general-purpose output TINP0 E2 I Timer 0 or general-purpose input TIMER 1 TOUT1 G4 O Timer 1 or general-purpose output TINP1 H6 I Timer 1 or general-purpose input DMA ACTION COMPLETE STATUS DMAC3 R6 DMAC2 U2 O DMA action completeDMAC1 T6 O DMA action complete DMAC0 V4 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002

24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

Signal Descriptions (Continued) SIGNAL NAME PIN NO. TYPE † DESCRIPTIONNAME GLP TYPE † DESCRIPTION MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0) CLKS0 K6 I External clock source (as opposed to internal) CLKR0 L1 I/O/Z Receive clock CLKX0 K3 I/O/Z Transmit clock DR0 M1 I Receive data DX0 L6 O/Z Transmit data FSR0 L2 I/O/Z Receive frame sync FSX0 L3 I/O/Z Transmit frame sync MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) CLKS1 G2 I External clock source (as opposed to internal) CLKR1 H2 I/O/Z Receive clock CLKX1 H4 I/O/Z Transmit clock DR1 J2 I Receive data DX1 H3 O/Z Transmit data FSR1 J6 I/O/Z Receive frame sync FSX1 J1 I/O/Z Transmit frame sync MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP2) CLKS2 L4 I External clock source (as opposed to internal) CLKR2 M2 I/O/Z Receive clock CLKX2 N4 I/O/Z Transmit clock DR2 P3 I Receive data DX2 N2 O/Z Transmit data FSR2 M6 I/O/Z Receive frame sync FSX2 N1 I/O/Z Transmit frame sync RESERVED FOR TEST RSV0 K1 I Reserved for testing, pullup with a dedicated 20-kΩ resistor RSV1 F3 I Reserved for testing, pullup with a dedicated 20-kΩ resistor RSV2 A10 I Reserved for testing, pullup with a dedicated 20-kΩ resistor RSV3 F11 O Reserved (leave unconnected, do not connect to power or ground) RSV4 D9 O Reserved (leave unconnected, do not connect to power or ground) R11 - N/C R9 - No connectN/C W7 - No connect † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002 25POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 Signal Descriptions (Continued) SIGNAL NAME PIN NO. TYPE † DESCRIPTIONNAME GLP TYPE † DESCRIPTION SUPPLY VOLTAGE PINS C14 E19 H11 H13 J10 J12 J14 J19 K11 K13 K15 D V 33V L10 S 3 3 V s ppl oltage (I/O)DV DD - 3.3 V L12 S 3.3-V supply voltage (I/O) L14 M11 M13 M15 N10 N12 N14 N19 P11 P13 U19 W14 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002

26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

Signal Descriptions (Continued) SIGNAL NAME PIN NO. TYPE † DESCRIPTIONNAME GLP TYPE † DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) A12 A13 A16 A18 B10 B12 B19 C20 D15 D16 D21 CV DD - 1.5 V E1 S 1.5-V supply voltage (core)CV DD 1.5 V S 1.5 V su ly voltage (core) E10 E12 E14 E16 F10 F14 F17 F20 F21 G13 G18 H16 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002 27POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 Signal Descriptions (Continued) SIGNAL NAME PIN NO. TYPE † DESCRIPTIONNAME GLP TYPE † DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) H17 H18 K17 L18 L19 L20 M17 N20 P17 P18 P19 R10 R14 R21 CV DD - 1.5 V T1 S 1.5-V supply voltage (core)CV DD 1.5 V S 1.5 V su ly voltage (core) T17 U10 U12 U14 U16 U21 V11 V12 V15 V20 W13 W19 W21 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002

28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

Signal Descriptions (Continued) SIGNAL NAME PIN NO. TYPE † DESCRIPTIONNAME GLP TYPE † DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) Y18 Y20 AA4 AA6 CV DD - 1.5 V AA11 S 1.5-V supply voltage (core)CV DD 1.5 V AA12 S 1.5 V su ly voltage (core) AA15 AA17 AA19 GROUND PINS A15 A17 A19 B18 B20 C11 C16 C19 C21 VSS D1 GND Ground pinsVSS GND Ground ins D20 E11 E13 E15 E17 E21 F18 G17 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002 29POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 Signal Descriptions (Continued) SIGNAL NAME PIN NO. TYPE † DESCRIPTIONNAME GLP TYPE † DESCRIPTION GROUND PINS (CONTINUED) G19 G21 H10 H12 H14 H15 J11 J13 J15 J16 J17 K10 K12 VSS K14 GND Ground pinsVSS GND Ground ins L11 L13 L15 L17 M10 M12 M14 N11 N13 N15 N17 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002

30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

Signal Descriptions (Continued) SIGNAL NAME PIN NO. TYPE † DESCRIPTIONNAME GLP TYPE † DESCRIPTION GROUND PINS (CONTINUED) P10 P12 P14 P15 P21 R17 R19 T21 U11 U13 VSS U15 GND Ground pinsVSS U17 GND Ground ins V21 W11 W16 W20 Y19 AA3 AA5 AA7 AA14 AA16 AA18 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002 31POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 development support TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of C6000 DSP-based applications: Software Development Tools: Code Composer Studio Integrated Development Environment (IDE) including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP/BIOS ), which provides the basic run-time target software needed to support any DSP application. Hardware Development Tools: Extended Development System (XDS ) Emulator (supports C6000 DSP multiprocessor system debug) EVM (Evaluation Module) The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about development-support products for all TMS320 DSP family member devices, including documentation. See this document for further information on TMS320 DSP documentation or any TMS320 DSP support products from Texas Instruments. An additional document, the TMS320 Third-Party Support Reference Guide (SPRU052), contains information about TMS320 DSP-related products from other companies in the industry. To receive TMS320 DSP literature, contact the Literature Response Center at 800/477-8924. For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL) and select “Find Development Tools”. For device-specific tools, under “Semiconductor Products” select “Digital Signal Processors”, choose a product family, and select the particular DSP device. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. TMS320C6000, C6000, Code Composer Studio, DSP/BIOS, XDS, and TMS320 are trademarks of Texas Instruments.

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002

32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

development support (Continued) device and development-support tool nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all SMJ320  DSP devices and support tools. Each SMJ320 DSP commercial family member has one of three prefixes: SMX, SM, or SMJ. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (SMX/TMDX) through fully qualified production devices/tools (SMJ/TMDS). Device development evolutionary flow: SMX Experimental device that is not necessarily representative of the final device’s electrical specifications SM Final silicon die that conforms to the device’s electrical specifications but has not completed quality and reliability verification SMJ Fully qualified production device processed to MIL-PRF-38535 Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product SMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: “Developmental product is intended for internal evaluation purposes.” SMJ devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI’s standard warranty applies. Predictions show that prototype devices (SMX or SM) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, GLP), the temperature range, and the device speed range in megahertz (for example, 20 is 200 MHz). Figure 4 provides a legend for reading the complete device name. For the C6203 device orderable part numbers (P/Ns), see the Texas Instruments web site on the Worldwide web at http://www.ti.com URL, or contact the nearest TI field sales office, or authorized distributor. TMS320 is a trademark of Texas Instruments.

Figure 4. SMJ320C6000 DSP Platform Device Nomenclature C6000  CPU (DSP core) architecture, instruction set, pipeline, and associated interrupts. includes information on internal data and program memories. TMS320C62x  /TMS320C67x  devices, associated development tools, and third-party support. Worldwide Web at http://www.ti.com uniform resource locator (URL). TMS320C67x is a trademark of Texas Instruments.

34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

bypasses the PLL to become the internal CPU clock. modes. Figure 6 shows the external PLL circuitry for a system with ONLY x1 (PLL bypass) mode. Table 15. Compatible CLKIN External Clock Sources

342 Corning Frequency Control

with the PLL components on a single side of the board without jumpers, switches, or components other than the ones shown. C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD . Figure 5. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode

NOTES: A. For a system with ONLY PLL x1 (bypass) mode, short the PLLF to PLLG. B. The 3.3-V supply for PLLV must be from the same 3.3-V power plane supplying the I/O voltage, DVDD . Figure 6. External PLL Circuitry for x1 (Bypass) PLL Mode Only Table 16. PLL Multiply and Bypass (x1) Options† Table 17. SMJ320C6203 PLL Component Selection Table† the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002

36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage. system-level design considerations System-level design considerations, such as bus contention, may require supply sequencing to be implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered down after), the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the output buffers are powered up, thus, preventing bus contention with other chips on the board. power-supply design considerations For systems using the C6000 DSP platform of devices, the core supply may be required to provide in excess of 2 A per DSP until the I/O supply is powered up. This extra current condition is a result of uninitialized logic within the DSP(s) and is corrected once the CPU sees an internal clock pulse. With the PLL enabled, as the I/O supply is powered on, a clock pulse is produced stopping the extra current draw from the supply. With the PLL disabled, as many as five external clock cycle pulses may be required to stop this extra current draw. A normal current state returns once the I/O power supply is turned on and the CPU sees a clock pulse. Decreasing the amount of time between the core supply power up and the I/O supply power up can minimize the effects of this current draw. A dual-power supply with simultaneous sequencing, such as available with TPS563xx controllers or PT69xx plug-in power modules, can be used to eliminate the delay between core and I/O power up [see the Using the TPS56300 to Power DSPs application report (literature number SLVA088)]. A Schottky diode can also be used to tie the core rail to the I/O rail, effectively pulling up the I/O power supply to a level that can help initialize the logic within the DSP. Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize inductance and resistance in the power delivery path. Additionally, when designing for high-performance applications utilizing the C6000 platform of DSPs, the PC board should include separate power planes for core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002 37POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 absolute maximum ratings over operating case temperature ranges (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions MIN NOM MAX UNIT CV DD Supply voltage, Core 1.43 1.5 1.57 V DV DD Supply voltage, I/O 3.14 3.3 3.46 V VSS Supply ground 0 0 0 V VIH High-level input voltage‡ 2 V VIL Low-level input voltage§ 0.8 V IOH High-level output current –8 mA IOL Low-level output current 8 mA TC Operating case temperature –55 125 /C0095C ‡ VIH is not production tested for: CLKMODE [2:0], CLKIN, XCLKIN, XCS. § VIL is not production tested for: CLKIN, TRST. electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage¶ DV DD = MIN, I OH = MAX 2.4 V VOL Low-level output voltage¶ DV DD = MIN, I OL = MAX 0.6 V II Input current# VI = VSS to DVDD ±10 uA IOZ Off-state output current|| VO = DVDD or 0 V ±10 uA IDD2V Supply current, CPU + CPU memory access/C0107 CV DD = NOM, CPU clock = 200 MHz 340 mA IDD2V Supply current, peripherals/C0107 CV DD = NOM, CPU clock = 200 MHz 235 mA IDD3V Supply current, I/O pins/C0107 CV DD = NOM, CPU clock = 200 MHz 45 mA C i Input capacitance 12 pF C o Output capacitance 15 pF ¶ VOH and VOL are not production tested for: CLKOUT1, EMU0, EMU1. # TMS and TDI are not included due to internal pullups. TRST is not included due to internal pulldown. ||TDO is not production tested. /C0107Measured with average activity (50% high / 50% low power). For more details on CPU, peripheral, and I/O activity, see the TMS320C6000 Power Consumption Summary application report (literature number SPRA486).

38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

Figure 7. Test Load Circuit for AC Timing Measurements All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels. Figure 8. Input and Output Voltage Reference Levels for ac Timing Measurements VOL MAX and VOH MIN for output clocks. Figure 9. Rise and Fall Transition Time Voltage Reference Levels

may be used to compensate any timing differences. but also tends to improve the input hold time margins (see Table 18 and Figure 10). board route delays and how they are perceived by the DSP and the external device. Table 18. IBIS Timing Parameters

1 Clock route delay

2 Minimum DSP hold time

3 Minimum DSP setup time

4 External device hold time requirement

5 External device setup time requirement

6 Control signal route delay

7 External device hold time

8 External device access time

9 DSP hold time requirement

10 DSP setup time requirement

11 Data route delay

† Control signals include data for Writes. ‡ Data signals are generated during Reads from an external device. Figure 10. IBIS Input/Output Timings

40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

*This parameter is not production tested. † The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. ‡ M = the PLL multiplier factor (x4, x6, x7, x8, x9, x10, or x11). § C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns. *This parameter is not production tested. † The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. Figure 11. CLKIN Timings

42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

*This parameter is not production tested. † P = 1/CPU clock frequency in ns. Figure 14. XFCLK Timings *This parameter is not production tested. time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input. programmed via the EMIF CE space control registers. # P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ||The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width.

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002 43POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 ASYNCHRONOUS MEMORY TIMING (CONTINUED) switching characteristics over recommended operating conditions for asynchronous memory cycles†‡§¶ (see Figure 15 – Figure 18) NO. PARAMETER MIN TYP MAX UNIT 1 tosu(SELV-AREL) Output setup time, select signals valid to ARE low RS x P – 2 ns 2 toh(AREH-SELIV) Output hold time, ARE high to select signals invalid *RH x P – 2 ns 5 tw(AREL) Pulse width, ARE low RST x P ns 8 td(ARDYH-AREH) Delay time, ARDY high to ARE high *3P *4P + 5 ns 12 tosu(SELV-AWEL) Output setup time, select signals valid to AWE low WS x P – 3 ns 13 toh(AWEH-SELIV) Output hold time, AWE high to select signals invalid *WH x P – 2 ns 14 tw(AWEL) Pulse width, AWE low WST x P ns 17 td(ARDYH-AWEH) Delay time, ARDY high to AWE high *3P *4P + 5 ns *This parameter is not production tested. † RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are programmed via the EMIF CE space control registers. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. § The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width. ¶ Select signals include: CEx, BE[3:0], EA[21:2], AOE; and for writes, include ED[31:0], with the exception that CEx can stay active for an additional 7P ns following the end of the cycle.

44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

HOLD = 1, then CEx stays active for six more cycles. This does not affect performance, it merely reflects the EMIF’s overhead. Figure 15. Asynchronous Memory Read Timing (ARDY Not Used) HOLD = 1, then CEx stays active for six more cycles. This does not affect performance, it merely reflects the EMIF’s overhead. Figure 16. Asynchronous Memory Read Timing (ARDY Used)

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002

46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

SYNCHRONOUS-BURST MEMORY TIMING timing requirements for synchronous-burst SRAM cycles (see Figure 19) NO. MIN MAX UNIT 7 tsu(EDV-CKO2H) Setup time, read EDx valid before CLKOUT2 high 2.0 ns 8 th(CKO2H-EDV) Hold time, read EDx valid after CLKOUT2 high 2.0 ns switching characteristics over recommended operating conditions for synchronous-burst SRAM cycles†‡ (see Figure 19 and Figure 20) NO. PARAMETER MIN MAX UNIT 1 tosu(CEV-CKO2H) Output setup time, CEx valid before CLKOUT2 high P – 0.8 ns 2 toh(CKO2H-CEV) Output hold time, CEx valid after CLKOUT2 high *P – 4 ns 3 tosu(BEV-CKO2H) Output setup time, BEx valid before CLKOUT2 high P – 0.8 ns 4 toh(CKO2H-BEIV) Output hold time, BEx invalid after CLKOUT2 high *P – 4 ns 5 tosu(EAV-CKO2H) Output setup time, EAx valid before CLKOUT2 high P – 0.8 ns 6 toh(CKO2H-EAIV) Output hold time, EAx invalid after CLKOUT2 high *P – 4 ns 9 tosu(ADSV-CKO2H) Output setup time, SDCAS/SSADS valid before CLKOUT2 high P – 0.8 ns 10 toh(CKO2H-ADSV) Output hold time, SDCAS/SSADS valid after CLKOUT2 high *P – 4 ns 11 tosu(OEV-CKO2H) Output setup time, SDRAS/SSOE valid before CLKOUT2 high P – 0.8 ns 12 toh(CKO2H-OEV) Output hold time, SDRAS/SSOE valid after CLKOUT2 high *P – 4 ns 13 tosu(EDV-CKO2H) Output setup time, EDx valid before CLKOUT2 high§ P – 1.2 ns 14 toh(CKO2H-EDIV) Output hold time, EDx invalid after CLKOUT2 high *P – 4 ns 15 tosu(WEV-CKO2H) Output setup time, SDWE/SSWE valid before CLKOUT2 high P – 0.8 ns 16 toh(CKO2H-WEV) Output hold time, SDWE/SSWE valid after CLKOUT2 high *P – 4 ns *This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ SDCAS /SSADS , SDRAS/SSOE , and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses. § For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate the ED enable time.

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002

48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

timing requirements for synchronous DRAM cycles (see Figure 21) NO. MIN MAX UNIT 7 tsu(EDV-CKO2H) Setup time, read EDx valid before CLKOUT2 high 1.2 ns 8 th(CKO2H-EDV) Hold time, read EDx valid after CLKOUT2 high 2.9 ns switching characteristics over recommended operating conditions for synchronous DRAM cycles for C6203B Rev. 2†‡ (see Figure 21–Figure 26) NO. PARAMETER MIN MAX UNIT 1 tosu(CEV-CKO2H) Output setup time, CEx valid before CLKOUT2 high P – 0.9 ns 2 toh(CKO2H-CEV) Output hold time, CEx valid after CLKOUT2 high *P – 4 ns 3 tosu(BEV-CKO2H) Output setup time, BEx valid before CLKOUT2 high P – 0.9 ns 4 toh(CKO2H-BEIV) Output hold time, BEx invalid after CLKOUT2 high *P – 4 ns 5 tosu(EAV-CKO2H) Output setup time, EAx valid before CLKOUT2 high P – 0.9 ns 6 toh(CKO2H-EAIV) Output hold time, EAx invalid after CLKOUT2 high *P – 4 ns 9 tosu(CASV-CKO2H) Output setup time, SDCAS/SSADS valid before CLKOUT2 high P – 0.9 ns 10 toh(CKO2H-CASV) Output hold time, SDCAS/SSADS valid after CLKOUT2 high *P – 4 ns 11 tosu(EDV-CKO2H) Output setup time, EDx valid before CLKOUT2 high§ P – 1.5 ns 12 toh(CKO2H-EDIV) Output hold time, EDx invalid after CLKOUT2 high *P – 4 ns 13 tosu(WEV-CKO2H) Output setup time, SDWE/SSWE valid before CLKOUT2 high P – 0.9 ns 14 toh(CKO2H-WEV) Output hold time, SDWE/SSWE valid after CLKOUT2 high *P – 4 ns 15 tosu(SDA10V-CKO2H) Output setup time, SDA10 valid before CLKOUT2 high P – 0.9 ns 16 toh(CKO2H-SDA10IV) Output hold time, SDA10 invalid after CLKOUT2 high *P – 4 ns 17 tosu(RASV-CKO2H) Output setup time, SDRAS/SSOE valid before CLKOUT2 high P – 0.9 ns 18 toh(CKO2H-RASV) Output hold time, SDRAS/SSOE valid after CLKOUT2 high *P – 4 ns *This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ SDCAS /SSADS , SDRAS/SSOE , and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses. § For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate the ED enable time.

50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

† SDCAS /SSADS , SDRAS/SSOE , and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses. Figure 23. SDRAM ACTV Command † SDCAS /SSADS , SDRAS/SSOE , and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses. Figure 24. SDRAM DCAB Command

52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

*This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. *This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS , SDRAS/SSOE , SDWE /SSWE , and SDA10. minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1. ‡ EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS , SDRAS/SSOE , SDWE /SSWE , and SDA10. Figure 27. HOLD/HOLDA Timing *This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. has been changed. During that time, RESET must be asserted to ensure proper device operation. See the Clock PLL section for PLL lock times. ||XD[31:0] are the boot configuration pins during device reset.

*This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. § XD[31:0] are the boot configuration pins during device reset. Figure 28. Reset Timing

54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

*This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. *This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. Figure 29. Interrupt Timing

*This parameter is not production tested. † XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses. ‡ XWE /XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses. NOTES: A. FIFO read (glueless) mode only available in XCE3. B. XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses. C. XWE /XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses. Figure 30. FIFO Read Timing (Glueless Read Mode)

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† XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses. ‡ XWE /XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses. Figure 31. FIFO Read Timing † XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses. ‡ XWE /XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses. Figure 32. FIFO Write Timing

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002 57POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING timing requirements for asynchronous peripheral cycles†‡§¶ (see Figure 33–Figure 36) NO. MIN MAX UNIT 3 tsu(XDV-XREH) Setup time, XDx valid before XRE high 4.5 ns 4 th(XREH-XDV) Hold time, XDx valid after XRE high 2.5 ns 6 tsu(XRDYH-XREL) Setup time, XRDY high before XRE low –[(RST – 3) x P – 6] ns 7 th(XREL-XRDYH) Hold time, XRDY high after XRE low (RST – 3) x P + 2 ns 9 tsu(XRDYL-XREL) Setup time, XRDY low before XRE low –[(RST – 3) x P – 6] ns 10 th(XREL-XRDYL) Hold time, XRDY low after XRE low (RST – 3) x P + 2 ns 11 tw(XRDYH) Pulse width, XRDY high *2P ns 15 tsu(XRDYH-XWEL) Setup time, XRDY high before XWE low –[(WST – 3) x P – 6] ns 16 th(XWEL-XRDYH) Hold time, XRDY high after XWE low (WST – 3) x P + 2 ns 18 tsu(XRDYL-XWEL) Setup time, XRDY low before XWE low –[(WST – 3) x P – 6] ns 19 th(XWEL-XRDYL) Hold time, XRDY low after XWE low (WST – 3) x P + 2 ns *This parameter is not production tested. † To ensure data setup time, simply program the strobe width wide enough. XRDY is internally synchronized. If XRDY does meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus, XRDY can be an asynchronous input. ‡ RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are programmed via the expansion bus XCE space control registers. § P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ¶ The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use XRDY input to extend strobe width.

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002

58 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED) switching characteristics over recommended operating conditions for asynchronous peripheral cycles†‡§¶ (see Figure 33–Figure 36) NO. PARAMETER MIN TYP MAX UNIT 1 tosu(SELV-XREL) Output setup time, select signals valid to XRE low RS x P – 2 ns 2 toh(XREH-SELIV) Output hold time, XRE low to select signals invalid *RH x P – 2 ns 5 tw(XREL) Pulse width, XRE low RST x P ns 8 td(XRDYH-XREH) Delay time, XRDY high to XRE high *3P *4P + 5 ns 12 tosu(SELV-XWEL) Output setup time, select signals valid to XWE low WS x P – 3 ns 13 toh(XWEH-SELIV) Output hold time, XWE low to select signals invalid *WH x P – 2 ns 14 tw(XWEL) Pulse width, XWE low WST x P ns 17 td(XRDYH-XWEH) Delay time, XRDY high to XWE high *3P *4P + 5 ns *This parameter is not production tested. † RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are programmed via the expansion bus XCE space control registers. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. § The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use XRDY input to extend strobe width. ¶ Select signals include: XCEx, XBE[3:0]/XA[5:2], XOE; and for writes, include XD[31:0], with the exception that XCEx can stay active for an additional 7P ns following the end of the cycle.

60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

† XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses. ‡ XWE /XWAIT operates as the write-enable signal XWE during expansion bus asynchronous peripheral accesses. § XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses. Figure 35. Expansion Bus Asynchronous Peripheral Write Timing (XRDY Not Used) † XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses. ‡ XWE /XWAIT operates as the write-enable signal XWE during expansion bus asynchronous peripheral accesses. § XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses. Figure 36. Expansion Bus Asynchronous Peripheral Write Timing (XRDY Used)

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002 61POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING timing requirements with external device as bus master (see Figure 37 and Figure 38) NO. MIN MAX UNIT 1 tsu(XCSV-XCKIH) Setup time, XCS valid before XCLKIN high 3.5 ns 2 th(XCKIH-XCS) Hold time, XCS valid after XCLKIN high 2.8 ns 3 tsu(XAS-XCKIH) Setup time, XAS valid before XCLKIN high 3.5 ns 4 th(XCKIH-XAS) Hold time, XAS valid after XCLKIN high 2.8 ns 5 tsu(XCTL-XCKIH) Setup time, XCNTL valid before XCLKIN high 3.5 ns 6 th(XCKIH-XCTL) Hold time, XCNTL valid after XCLKIN high 2.8 ns 7 tsu(XWR-XCKIH) Setup time, XW/R valid before XCLKIN high† 3.5 ns 8 th(XCKIH-XWR) Hold time, XW/R valid after XCLKIN high† 2.8 ns 9 tsu(XBLTV-XCKIH) Setup time, XBLAST valid before XCLKIN high‡ 3.5 ns 10 th(XCKIH-XBLTV) Hold time, XBLAST valid after XCLKIN high‡ 2.8 ns 16 tsu(XBEV-XCKIH) Setup time, XBE[3:0]/XA[5:2] valid before XCLKIN high§ 3.5 ns 17 th(XCKIH-XBEV) Hold time, XBE[3:0]/XA[5:2] valid after XCLKIN high§ 2.8 ns 18 tsu(XD-XCKIH) Setup time, XDx valid before XCLKIN high 3.5 ns 19 th(XCKIH-XD) Hold time, XDx valid after XCLKIN high 2.8 ns † XW/R input/output polarity selected at boot. ‡ XBLAST input polarity selected at boot § XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. switching characteristics over recommended operating conditions with external device as bus master¶ (see Figure 37 and Figure 38) NO. PARAMETER MIN MAX UNIT 11 td(XCKIH-XDLZ) Delay time, XCLKIN high to XDx low impedance *0 ns 12 td(XCKIH-XDV) Delay time, XCLKIN high to XDx valid 17 ns 13 td(XCKIH-XDIV) Delay time, XCLKIN high to XDx invalid *5 ns 14 td(XCKIH-XDHZ) Delay time, XCLKIN high to XDx high impedance *4P ns 15 td(XCKIH-XRY) Delay time, XCLKIN high to XRDY invalid# *5 *17 ns 20 td(XCKIH-XRYLZ) Delay time, XCLKIN high to XRDY low impedance *5 *17 ns 21 td(XCKIH-XRYHZ) Delay time, XCLKIN high to XRDY high impedance# *2P + 5 *3P + 17 ns *This parameter is not production tested. ¶ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. # XRDY operates as active-low ready input/output during host-port accesses.

62 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

‡ XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. ¶ XRDY operates as active-low ready input/output during host-port accesses. Figure 37. External Host as Bus Master— Read

‡ XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. ¶ XRDY operates as active-low ready input/output during host-port accesses. Figure 38. External Host as Bus Master— Write

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002

64 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443

EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED) timing requirements with C62x as bus master (see Figure 39, Figure 40, and Figure 41) NO. MIN MAX UNIT 9 tsu(XDV-XCKIH) Setup time, XDx valid before XCLKIN high 3.5 ns 10 th(XCKIH-XDV) Hold time, XDx valid after XCLKIN high 2.8 ns 11 tsu(XRY-XCKIH) Setup time, XRDY valid before XCLKIN high† 3.5 ns 12 th(XCKIH-XRY) Hold time, XRDY valid after XCLKIN high† 2.8 ns 14 tsu(XBFF-XCKIH) Setup time, XBOFF valid before XCLKIN high 3.5 ns 15 th(XCKIH-XBFF) Hold time, XBOFF valid after XCLKIN high 2.8 ns † XRDY operates as active-low ready input/output during host-port accesses. switching characteristics over recommended operating conditions with C62x as bus master‡ (see Figure 39, Figure 40, and Figure 41) NO. PARAMETER MIN MAX UNIT 1 td(XCKIH-XASV) Delay time, XCLKIN high to XAS valid *5 17 ns 2 td(XCKIH-XWRV) Delay time, XCLKIN high to XW/R valid§ *5 17 ns 3 td(XCKIH-XBLTV) Delay time, XCLKIN high to XBLAST valid¶ *5 17 ns 4 td(XCKIH-XBEV) Delay time, XCLKIN high to XBE[3:0]/XA[5:2] valid# *5 17 ns 5 td(XCKIH-XDLZ) Delay time, XCLKIN high to XDx low impedance *0 ns 6 td(XCKIH-XDV) Delay time, XCLKIN high to XDx valid 17 ns 7 td(XCKIH-XDIV) Delay time, XCLKIN high to XDx invalid *5 ns 8 td(XCKIH-XDHZ) Delay time, XCLKIN high to XDx high impedance *4P ns 13 td(XCKIH-XWTV) Delay time, XCLKIN high to XWE/XWAIT valid|| *5 17 ns *This parameter is not production tested. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. § XW/R input/output polarity selected at boot. ¶ XBLAST output polarity is always active low. # XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. ||XWE /XWAIT operates as XWAIT output signal during host-port accesses.

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‡ XBLAST output polarity is always active low. § XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. ||This diagram illustrates XBOFF timing. Bus arbitration timing is shown in Figure 44 and Figure 45. Figure 41. C62x as Bus Master— BOFF Operation||

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002 67POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 EXPANSION BUS ASYNCHRONOUS HOST-PORT TIMING timing requirements with external device as asynchronous bus master† (see Figure 42 and Figure 43) NO. MIN MAX UNIT 1 tw(XCSL) Pulse duration, XCS low 4P ns 2 tw(XCSH) Pulse duration, XCS high 4P ns 3 tsu(XSEL-XCSL) Setup time, expansion bus select signals‡ valid before XCS low 1 ns 4 th(XCSL-XSEL) Hold time, expansion bus select signals‡ valid after XCS low 3.4 ns 10 th(XRYL-XCSL) Hold time, XCS low after XRDY low *P + 1.5 ns 11 tsu(XBEV-XCSH) Setup time, XBE[3:0]/XA[5:2] valid before XCS high§ 1 ns 12 th(XCSH-XBEV) Hold time, XBE[3:0]/XA[5:2] valid after XCS high§ 3 ns 13 tsu(XDV-XCSH) Setup time, XDx valid before XCS high 1 ns 14 th(XCSH-XDV) Hold time, XDx valid after XCS high 3 ns *This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ Expansion bus select signals include XCNTL and XR/W. § XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. switching characteristics over recommended operating conditions with external device as asynchronous bus master† (see Figure 42 and Figure 43) NO. PARAMETER MIN MAX UNIT 5 td(XCSL-XDLZ) Delay time, XCS low to XDx low impedance *0 ns 6 td(XCSH-XDIV) Delay time, XCS high to XDx invalid *0 *12 ns 7 td(XCSH-XDHZ) Delay time, XCS high to XDx high impedance *4P ns 8 td(XRYL-XDV) Delay time, XRDY low to XDx valid *–4 *1 ns 9 td(XCSH-XRYH) Delay time, XCS high to XRDY high *0 12 ns *This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

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† XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. Figure 42. External Device as Asynchronous Master— Read † XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. Figure 43. External Device as Asynchronous Master— Write

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002

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MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements for McBSP†‡ (see Figure 46) NO. MIN MAX UNIT 2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P§ ns 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext *P–1¶ ns 5 t Setup time external FSR high before CLKR low CLKR int 9 ns5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low CLKR ext 2 ns 6 t Hold time e ternal FSR high after CLKR lo CLKR int 6 ns6 th(CKRL-FRH) Hold time, external FSR high after CLKR low CLKR ext 4 ns 7 t Set p time DR alid before CLKR lo CLKR int 8 ns7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low CLKR ext 0.5 ns 8 t Hold time DR alid after CLKR lo CLKR int 3 ns8 th(CKRL-DRV) Hold time, DR valid after CLKR low CLKR ext 5 ns 10 t Set p time e ternal FSX high before CLKX lo CLKX int 9 ns10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low CLKX ext 2 ns 11 t Hold time external FSX high after CLKX low CLKX int 6 ns11 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKX ext 4 ns *This parameter is not production tested. † CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. § The maximum bit rate for the C6203 device is 100 Mbps or CPU/2 (the slower of the two). Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 200 MHz (P = 5 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave. ¶ The minimum CLKR/X pulse duration is either (P–1) or 4 ns, whichever is larger. For example, when running parts at 200 MHz (P = 5 ns), use 4 ns as the minimum CLKR/X pulse duration. When running parts at 100 MHz (P = 10 ns), use (P–1) = 9 ns as the minimum CLKR/X pulse duration.

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002 71POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics over recommended operating conditions for McBSP†‡ (see Figure 46) NO. PARAMETER MIN MAX UNIT 1 td(CKSH-CKRXH) Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input *4 *16 ns 2 tc(CKRX) Cycle time, CLKR/X CLKR/X int *2P§¶ ns 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int *C – 2# *C + 2# ns 4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int *–3 *3 ns 9 t Delay time, CLKX high to internal FSX CLKX int *–3 3 ns9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid CLKX ext *–3 9 ns 12 t Disable time, DX high impedance following last data bit fromCLKX int *–1 *5 ns12 tdis(CKXH-DXHZ) Disable time, DX high im edance following last data bit from CLKX high CLKX ext *2 *9 ns 13 t Dela time CLKX high to DX alid CLKX int *–1 *4 ns13 td(CKXH-DXV) Delay time, CLKX high to DX valid CLKX ext *2 *11 ns 14 t Delay time, FSX high to DX valid ONLY applies when in data delay 0 FSX int *–1 *5 ns14 td(FXH-DXV) ONLY applies when in data delay 0 (XDATDLY = 00b) mode. FSX ext *0 *10 ns *This parameter is not production tested. † CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ Minimum delay times also represent minimum output hold times. § P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ¶ The maximum bit rate for the C6203 device is 100 Mbps or CPU/2 (the slower of the two). Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 200 MHz (P = 5 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave. # C = H or L S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit.

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Figure 46. McBSP Timings *This parameter is not production tested. Figure 47. FSR Timing When GSYNC = 1

*This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. *This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit. and FSR is inverted before being used internally. Figure 48. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0

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*This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. *This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. The maximum transfer rate for SPI mode is limited to the above AC timing constraints. and FSR is inverted before being used internally. Figure 49. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0

*This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. *This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. The maximum transfer rate for SPI mode is limited to the above AC timing constraints. and FSR is inverted before being used internally. Figure 50. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1

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*This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. *This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit. and FSR is inverted before being used internally. Figure 51. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1

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*This parameter is not production tested. † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. Figure 54. Power-Down Timing *This parameter is not production tested. *This parameter is not production tested. Figure 55. JTAG Test-Port Timing

/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0054/C0050/C0048/C0051 /C0070/C0073/C0088/C0069/C0068/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS033 – FEBRUARY 2002 79POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 MECHANICAL DATA GLP (S-CBGA-N429) CERAMIC BALL GRID ARRAY 0,15 1,27 M∅ 0,10 25,40 TYP 1816 15 171311 10 12 14 Y V W AA U R T N M P K H J F E G C A B D L Seating Plane 4164732/A 08/98 SQ27,20 26,80 0,50 0,700,60 0,90 1,00 1,22 3,30 MAX 1,27 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MO-156 D. Flip chip application only thermal resistance characteristics (S-CBGA package) NO °C/W Air Flow 1 R Θ JC Junction-to-Case, measured to the bottom of solder ball 3.0 N/A 2 R Θ JC Junction-to-Case, measured to the top of the package lid 7.3 N/A 3 R Θ JA Junction-to-Ambient 14.5 0 4 11.8 150 fpm 5 R Θ JMA Junction-to-Moving-Air 11.1 250 fpm R Θ JMA Junction to Moving Air 10.2 500 fpm

7 R Θ JB

Junction-to-Board, measured by soldering a thermocouple to one of the middle traces on the board at the edge of the package 6.2 N/A

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 5962-0051001QXA ACTIVE FC/CSP GLP 429 1 None Call TI Call TI SM320C6203GLPM20 ACTIVE FC/CSP GLP 429 1 None Call TI Call TI SMJ320C6203GLPM20 ACTIVE FC/CSP GLP 429 1 None Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - May not be currently available - please checkhttp://www.ti.com/productcontentfor the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 25-Feb-2005 Addendum-Page 1

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright  2005, Texas Instruments Incorporated

Selected Specification

Texas Instruments 5962-0051001QXA overview.

Summary

FIXED POINT SIGNAL PROCESSOR

Description

FIXED POINT SIGNAL PROCESSOR

Source title 5962-0051001QXA Datasheet(PDF) - Texas Instruments

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