5890

5890 ALLEGRO

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Frequently applied in non-impact printer systems, the UCN5890A, UCN5890LW, UCN5891A, and UCN5891LW are BiMOS II serial-input, latched source (high-side) drivers. The octal, high-current smart-power ICs merge an 8-bit CMOS shift register, associated CMOS latches, and CMOS control logic (strobe and output enable) with sourcing power Darlington outputs. Typical applications include multiplexed LED and incandescent displays, relays, solenoids, and similar peripheral loads to a maximum of -500 mA per output. Except for output voltage ratings, these smart high-side driver ICs are equivalent. The UCN5890A/LW are rated for operation with load supply voltages of 20 V to 80 V and a minimum output sustaining voltage of 50 V. The UCN5891A/LW are optimized for operation with supply voltages of 5 V to 50 V (35 V sustaining). BiMOS II devices have higher data-input rates than the original BiMOS circuits. With a 5 V supply, they will operate to at least 3.3 MHz. At 12 V, higher speeds are possible. The CMOS inputs are compatible with standard CMOS and NMOS logic levels. TTL circuits may require the use of appropri- ate pull-up resistors to ensure a proper input-logic high. A CMOS serial data output, allows cascading these devices in multiple drive-line applications required by many dot matrix, alphanumeric, and bar graph displays. Suffix ‘A’ devices are supplied in a standard dual in-line plastic package with copper lead frame for enhanced package power dissipation characteris- tics. Suffix ‘LW’ devices are supplied in a standard wide-body SOIC package for surface-mount applications. Similar driver, featuring reduced output saturation voltage, are the UCN5895A and A5895SLW. Complementary, 8-bit serial-input, latched sink drivers are the Series UCN5820A.

FEATURES

I 50 V or 80 V Source Outputs I Output Current to -500 mA I Output Transient-Suppression Diodes I To 3.3 MHz Data-lnput Rate I Low-Power CMOS Logic and Latches BIMOS II 8-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS Data Sheet26182.12C ABSOLUTE MAXIMUM RATINGS at TA = +25°C Output Voltage, VOUT Logic Supply Voltage Range, Driver Supply Voltage Range, V BB Input Voltage Range, Continuous Output Current, Allowable Package Power Dissipation, Operating Temperature Range, Storage Temperature Range, Caution: CMOS devices have input static protection, but are susceptible to damage when exposed to extremely high static electrical charges. Always order by complete part number, e.g., UCN5891LW .

5890 AND

Note the suffix ‘A’ devices (DIP) and the suffix ‘LW’ devices (SOIC) are electrically identical and share a common terminal number assignment. SERIAL DATA OUT SERIAL DATA IN OUTPUT ENABLE LOGIC SUPPLY STROBE CLOCK CLK VDD ST OE 1GROUND OUT OUT 2 OUT3 Dwg. PP-026-2A OUT5 OUT6 OUT7 OUT8 OUT 4 SHIFT REGISTER LATCHES VBB LOAD SUPPLY

5890 AND 5891

8-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000 Dwg. No. A-12,654 FUNCTIONAL BLOCK DIAGRAM 8-BIT SERIAL-PARALLEL SHIFT REGISTER GROUND STROBE SERIAL DATA IN CLOCK LATCHES MOS BIPOLAR VBB SERIAL DATA OUT VDD OUTPUT ENABLE OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 Number of UCN5890/91A Max. Allowable Duty Cycle Outputs On at at T A of IOUT = -200 mA 50 °C6 0 °C7 0 °C 8 53% 47% 41% 7 60% 54% 48% 6 70% 64% 56% 5 83% 75% 67% 4 100% 94% 84% 3 100% 100% 100% 2 100% 100% 100% 1 100% 100% 100% Copyright © 1985, 2000 Allegro MicroSystems, Inc. 50 75 100 125 150 2.5 0.5 AMBIENT TEMPERATURE IN °C 2.0 1.5 1.0 Dwg. GP-018B SUFFIX 'A', R = 60°C/WθJA SUFFIX 'LW', R = 80°C/W θJA ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS Dwg. EP-010-4A IN VDD TYPICAL INPUT CIRCUIT Dwg. No. A-12,648 VBB OUT TYPICAL OUTPUT DRIVER Number of UCN5890/91LW Max. Allowable Duty Cycle Outputs On at at T A of IOUT = -200 mA 50 °C6 0 °C7 0 °C 8 40% 35% 31% 7 45% 41% 36% 6 53% 48% 42% 5 62% 56% 50% 4 80% 71% 62% 3 100% 96% 84% 2 100% 100% 100% 1 100% 100% 100%

8-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS www.allegromicro.com ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 80 V (UCN5890A/LW) or 50 V (UCN5891A/LW), VDD = 5 V and 12 V (unless otherwise noted). Limits Characteristic Symbol V BB Test Conditions Min. Max. Units Output Leakage Current I CEX Max. T A = +25°C — -50 µA TA = +70°C — -100 µA Output Saturation Voltage V CE(SAT) 50 V I OUT = -100 mA — 1.8 V IOUT = -225 mA — 1.9 V IOUT = -350 mA — 2.0 V Output Sustaining Voltage V CE(sus) Max. I OUT = -350 mA, L = 2 mH, UCN5891A/LW 35 — V IOUT = -350 mA, L = 2 mH, UCN5890A/LW 50 — V Input Voltage V IN(1) 50 V V DD = 5.0 V 3.5 5.3 V VDD = 12 V 10.5 12.3 V VIN(0) 50 V V DD = 5 V to 12 V -0.3 +0.8 V Input Current I IN(1) 50 V V DD = VIN = 5.0 V — 50 µA VDD = VIN = 12 V — 240 µA Input lmpedance Z IN 50 V V DD = 5.0 V 100 — kΩ VDD = 12 V 50 — kΩ Max. Clock Frequency f c 50 V 3.3* — MHz Serial Data Output R OUT 50 V V DD = 5.0 V — 20 k Ω Resistance VDD = 12 V — 6.0 k Ω Turn-On Delay t PLH 50 V Output Enable to Output, I OUT = -350 mA — 2.0 µs Turn-Off Delay t PHL 50 V Output Enable to Output, I OUT = -350 mA — 10 µs Supply Current I BB 50 V All outputs on, All outputs open — 10 mA All outputs off — 200 µA lDD 50 V V DD = 5 V, All outputs off, Inputs = 0 V — 100 µA VDD = 12 V, All outputs off, Inputs = 0 V — 200 µA VDD = 5 V, One output on, All Inputs = 0 V — 1.0 mA VDD = 12 V, One output on, All Inputs = 0 V — 3.0 mA Diode Leakage Current I R Max. T A = +25°C — 50 µA TA = +70°C — 100 µA Diode Forward Voltage V F Open I F = 350 mA — 2.0 V NOTES: Turn-off delay is influenced by load conditions. Systems applications well below the specified output loading may requir e timing considerations for some designs, i.e., multiplexed displays or when used in combination with sink drivers in a totem pole configuration. Positive (negative) current is defined as going into (coming out of) the specified device pin. * Operation at a clock frequency greater than the specified minimum value is possible but not warranteed.

8-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS Worcester, Massachusetts 01615-0036 (508) 853-5000 Serial Shift Register Contents Serial Latch Contents Output Contents Data Clock Data Strobe Output Input Input I HH R 1 R2 ... R N-2 RN-1 RN-1 LL R 1 R2 ... R N-2 RN-1 RN-1 XR 1 R2 R3 ... R N-1 RN RN E F CLOCK DATA IN STROBE BLANKING OUTN A D B C G Serial Data present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUT- PUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is trans- ferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the OUTPUT ENABLE input be high during serial data entry. When the OUTPUT ENABLE input is high, all of the output buffers are disabled (off) without affecting the information stored in the latches or shift register. With the OUTPUT ENABLE input low, the outputs are controlled by the state of their respective latches. Dwg. No. A-12,649A TIMING REQUIREMENTS (TA = +25°C,VDD = 5 V, Logic Levels are VDD and Ground) A. Minimum Data Active Time Before Clock Pulse B. Minimum Data Active Time After Clock Pulse G. Typical Time Between Strobe Activation and Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable with increased supply voltage; operation at high temperatures will reduce the specified maximum clock frequency. TRUTH TABLE L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State

8-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS www.allegromicro.com TYPICAL APPLICATION SOLENOID OR RELAY DRIVER OUTPUT ENABLE OE DDVSHIFT REGISTER BBVLATCHES DATA OUT (ACTIVE LOW) +5V +48V CLOCK DATA IN STROBE UCN5890A Dwg. No. A-12,548 The products described here are manufactured under one or more Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsi- bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.

8-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS Worcester, Massachusetts 01615-0036 (508) 853-5000 UCN5890A and UCN5891A Dimensions in Inches (controlling dimensions) Dimensions in Millimeters (for reference only) 0.014 0.008 0.300 BSC Dwg. MA-001-16A in 0.430 MAX 1 8 0.280 0.240 0.210 MAX 0.070 0.045 0.015 MIN 0.022 0.014 0.100 BSC 0.005 MIN 0.150 0.115 0.775 0.735 0.355 0.204 7.62 BSC Dwg. MA-001-16A mm 10.92 MAX 1 8 7.11 6.10 5.33 MAX 1.77 1.15 0.39 MIN 0.558 0.356 2.54 BSC 0.13 MIN 3.81 2.93 19.68 18.67 NOTES: 1. Exact body and lead configuration at vendor ’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. 4. Supplied in standard sticks/tubes of 25 devices.

8-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS www.allegromicro.com 1 2 3 0.2992 0.2914 0.4133 0.3977 0.419 0.3940.020 0.0130.0926 0.1043 0.0040 MIN. 0.0125 0.0091 0.050 0.016 0° TO 8° Dwg. MA-008-16A in 0.050 BSC 16 9 916 1 2 3 7.60 7.40 10.50 10.10 10.65 10.000.51 0.332.65 2.35 0.10 MIN. 0.32 0.23 1.27 0.40 0° TO 8° Dwg. MA-008-16A mm 1.27 BSC UCN5890LW and UCN5891LW Dimensions in Inches (for reference only) Dimensions in Millimeters (controlling dimensions) NOTES: 1. Exact body and lead configuration at vendor ’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Supplied in standard sticks/tubes of 47 devices or add “TR” to part number for tape and reel.

8-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS Worcester, Massachusetts 01615-0036 (508) 853-5000 POWER INTERFACE DRIVERS Function Output Ratings* Part Number † SERIAL-INPUT LATCHED DRIVERS 8-Bit (saturated drivers) -120 mA 50 V‡ 5895 8-Bit 350 mA 50 V 5821 8-Bit 350 mA 80 V 5822 8-Bit 350 mA 50 V‡ 5841 8-Bit 350 mA 80 V‡ 5842 8-Bit (constant-current LED driver) 75 mA 17 V 6275 8-Bit (DMOS drivers) 250 mA 50 V 6595 8-Bit (DMOS drivers) 350 mA 50 V‡ 6A595 8-Bit (DMOS drivers) 100 mA 50 V 6B595 10-Bit (active pull-downs) -25 mA 60 V 5810-F and 6809/10 12-Bit (active pull-downs) -25 mA 60 V 5811 and 6811 16-Bit (constant-current LED driver) 75 mA 17 V 6276 20-Bit (active pull-downs) -25 mA 60 V 5812-F and 6812 32-Bit (active pull-downs) -25 mA 60 V 5818-F and 6818 32-Bit 100 mA 30 V 5833 32-Bit (saturated drivers) 100 mA 40 V 5832 PARALLEL-INPUT LATCHED DRIVERS 4-Bit 350 mA 50 V‡ 5800 8-Bit -25 mA 60 V 5815 8-Bit 350 mA 50 V‡ 5801 8-Bit (DMOS drivers) 100 mA 50 V 6B273 8-Bit (DMOS drivers) 250 mA 50 V 6273 SPECIAL-PURPOSE DEVICES Unipolar Stepper Motor Translator/Driver 1.25 A 50 V‡ 5804 Addressable 8-Bit Decoder/DMOS Driver 250 mA 50 V 6259 Addressable 8-Bit Decoder/DMOS Driver 350 mA 50 V‡ 6A259 Addressable 8-Bit Decoder/DMOS Driver 100 mA 50 V 6B259 Addressable 28-Line Decoder/Driver 450 mA 30 V 6817 * Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits. Negative current is defined as coming out of (sourcing) the output. † Complete part number includes additional characters to indicate operating temperature range and package style. ‡ Internal transient-suppression diodes included for inductive-load protection.