5881 ALLEGRO
Document overview
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Technical content
— FOR REFERENCE ONLY With 16 CMOS data latches (two sets of eight), CMOS control circuitry for each set of latches, and a bipolar saturated driver for each latch, the UCN5881EP provides low-power interface with maximum flexibility. The driver includes thermal shutdown circuitry to protect against damage from high junction temperatures and clamp diodes for inductive load transient suppression. The CMOS inputs cause minimal circuit loading and are compat- ible with standard CMOS, PMOS, and NMOS circuits. TTL or DTL circuits may require the use of appropriate pull up resistors. When reading back, each data input will sink 8 mA (if its corresponding latch is low) or source 400 µA (if its corresponding latch is high). The read back feature is for error checking. It allows the system to verify that data has been received and latched. The bipolar outputs are suitable for use with low-power relays, solenoids, and stepping motors. The very-low output saturation voltage makes this device well-suited for driving LED arrays. The output transistors are capable of sinking 50 mA and will maintain at least 20 V in the OFF state. Outputs may be paralleled for higher current capability. The UCN5881EP dual 8-bit latched sink driver is rated for opera- tion over the temperature range of -20°C to +85°C and is supplied in a plastic 44-lead chip carrier conforming to the JEDEC MS-007AB outline.
FEATURES
n 4.4 MHz Minimum Data-Input Rate n Low-Power CMOS Logic n 20 V, 50 mA (Max.) Outputs n Transient-Protected Outputs n Thermal Shutdown Protection n Low-Profile Leaded Chip Carrier 5881 BiMOS II DUAL 8-BIT LATCHED DRIVER WITH READ BACK Always order by complete part number: UCN5881EP . ABSOLUTE MAXIMUM RATINGS Output Sustaining Voltage, VCE(sus) . . . 15 V Input Voltage Range, Package Power Dissipation, Operating Temperature Range, Storage Temperature Range, Caution: CMOS devices have input static protection, but are susceptible to damage when exposed to extremely high static electrical charges. Dwg. No. A-14,225 Data Sheet 26180.16
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000 FUNCTIONAL BLOCK DIAGRAM (1 of 16 Channels) Output Latch Read/ln Strobe Clear Enable Read/Write Contents Output X X X 1 X X OFF 01 00 1 0 O F F 11 00 1 1 O N X 0 0 0 1 n-1 n-1 X X 1 X X 0 OFF nX 0X 0 n n n = Present Latch Contents n-1 = Previous Latch Contents X = Irrelevant50 75 100 125 150 2.5 0.5 ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS AMBIENT TEMPERATURE IN °C 2.0 1.5 1.0 Dwg. GP-025-1A 3.0 R = 46°C/WqJA Dwg. No. A-14,227 W Copyright © 1985, 1995, Allegro MicroSystems, Inc. TRUTH TABLE
Characteristic Symbol Test Conditions Min. Max. Units Output Leakage Current I CEX VOUT = 20 V — 50 µA Output Saturation Voltage V CE(SAT) IOUT = 10 mA — 0.1 V IOUT = 25 mA — 0.5 V Output Sustaining Voltage V CE(sus) IOUT = 25 mA, L = 2 mH 15 — V Input Voltage V IN(0) -0.3 0.8 V VIN(1) 3.5 5.3 V Input Current I IN(0) VIN = 0.8 V — -10 µA IIN(1) VIN = 5 V — 10 µA Readback Output Voltage V OUT(1) IOUT = -400 µA 3.5 — V VOUT(0) IOUT = 5.0 mA — 0.8 V Logic Supply Current l DD All Drivers ON — 14 mA All Drivers OFF — 3.0 mA Clamp Diode Leakage Current I R VR = 20 V — 50 µA Clamp Diode Forward Voltage V F IF = 50 mA — 1.5 V ELECTRICAL CHARACTERISTICS at TA = 25°C, VDD = 5 V (unless otherwise noted). A high on the READ/WRITE input allows the circuit to accept data in. Information then present at an input is transferred to its latch when the STROBE is high. A high CLEAR input will set all latches to the output OFF condition regardless of the data or STROBE input levels. A high OUTPUT ENABLE will set all outputs to the OFF condition regard- less of any other input conditions. When the OUTPUT ENABLE is low, the outputs de- pend on the state of their respective latches. A low on the READ/WRITE input will allow the latched data to be read back on the data input lines. Allow a minimum of 750 ns delay (will increase with capacitive loading) before reading back the state of the latches. The read back feature is for error checking applications and allows the system to verify that data has been received and latched. Dwg. No. A-14,228 TIMING CONDITIONS (VDD = 5.0 V, Logic Levels are V DD and Ground) A. Minimum Data Active Time Before Strobe Enabled B. Minimum Data Active Time After Strobe Disabled D. Typical Time Between Strobe Activation and Output E. Typical Time Between Strobe Activation and Output
Worcester, Massachusetts 01615-0036 (508) 853-5000 NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. Dwg. MA-005-44A mm 17.65 17.40 0.51 MIN 4.57 4.20 17.65 17.40 16.662 16.510 1.27 BSC 0.812 0.661 144 0.533 0.331 INDEX AREA 40 6 16.662 16.510 8.10 7.39 8.10 7.39 1828 Dwg. MA-005-44A in 0.020 MIN 0.050 BSC 144 0.021 0.013 INDEX AREA 2 6 1729 0.695 0.685 0.032 0.026 0.319 0.291 0.319 0.291 0.180 0.165 0.695 0.685 0.656 0.650 0.656 0.650 Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the design of its products. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. Dimensions in Inches (controlling dimensions) Dimensions in Millimeters (for reference only)