5829

5829 ALLEGRO

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— FOR REFERENCE ONL Y Intended primarily to drive high-current, dot matrix 9- and 24-wire printer solenoids, the UCN5829EB serial-input, latched sink driver provides a complete driver function with a minimum external parts count. Included on chip are constant-frequency PWM current control for each output driver, a user-defined output enable timeout, current sensing, and thermal shutdown. The 9-bit CMOS shift register and latches allow operation with most microprocessor/LSI-based systems. With a 5 V logic supply, these BiMOS devices will operate at data input rates greater than 3.3 MHz. The CMOS inputs cause minimum loading and are compatible with standard CMOS, PMOS, NMOS, and TTL circuits. A CMOS serial data output allows cascade connections in applications requiring additional drive lines as required for 24-wire printheads. The device features nine open-collector Darlington drivers, each rated at 50 V and 1.6 A. Current-control for each output is provided by an internal current-sensing resistor and a constant-frequency chopper circuit. An external high-side driver can be used to optimize print head performance. It is enabled by an on-chip driver during the output enable timeout. Internal logic sequencing prevents false output operation during power up. Other high-current devices for driving dot matrix printheads are the UDN2961B/W and UDN2962W. The UCN5829EB is supplied in a 44-lead power PLCC. Its batwing construction provides for maximum package power dissipation in a minimum-area, surface-mountable package.

FEATURES

I 1.6 A Continuous Output Current I 50 V Minimum Sustaining Voltage I Internal Current Sensing I Constant-Frequency PWM Current Control I Control for External High-Side Driver I To 3.3 MHz Data Input Rate I Low-Power CMOS Logic & Latches I Internal Pull-Ups for TTL Compatibility I User-Defined Output Enable Timeout I Internal Thermal Shutdown Circuitry 5829 9-BIT SERIAL-INPUT, LATCHED SINK DRIVER GND GND GND GND 17 29 NO CONNECTION NO CONNECTION OUT 9 OUT 8 OUT 7 OUT 6 OUT 5 OUT 4 OUT 3 OUT 2 OUT 1 CLK CURRENT CONTROL SHIFT REGISTER LATCHES ONE-SHOT NCNC V DD

18 HIGH-SIDE

R REFERENCE C EN CV Dw g. PP-028A Always order by complete part number: UCN5829EB . * Fault conditions that produce excessive junction temperature will activate device thermal shut- down circuitry. These conditions can be tolerated, but should be avoided. Caution: This CMOS device has input static protection but is susceptible to damage when exposed to extremely high static electrical charges. ABSOLUTE MAXIMUM RATINGS Output Current, IOUT(S) Input Voltage Range, Package Power Dissipation, Operating Temperature Range, Storage Temperature Range, Data Sheet 26185.50

9-BIT SERIAL-INPUT, LATCHED SINK DRIVER

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000 FUNCTIONAL BLOCK DIAGRAM DRIVER TWO OF NINE DRIVERS CHOP INHIBIT <<1 Ω ONE-SHOT P.O.R. SHIFT REGISTER LATCHES STROBE CLOCK SERIAL DATA IN SERIAL DATA OUT IN V S R Q OUT V CURRENT LEVEL CONTROL HIGH-SIDE DRIVER Dwg. FP-015A +5 V +5 V TO DRIVERS 1, 3, 5, 7, 9 TO DRIVERS 4, 6, 8 7-17 29-39 DDR EN ENC R CC C R = 5 kΩ CV REF ±1% 50 75 100 125 150 ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS TEMPERATURE IN °C Dwg. GP-020B 12.5 2.5 7.5 5.0 R = 30°C/W θJA R = 6°C/W θJT Copyright © 1991, 1995 Allegro MicroSystems, Inc.

9-BIT SERIAL-INPUT, LATCHED SINK DRIVER TYPICAL INPUT CIRCUITS TYPICAL OUTPUT DRIVER ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V, in Test Circuit/Typical Application (unless otherwise noted). Characteristic Symbol Test Conditions Min. Typ. Max. Units Output Power Drivers (OUT1 through OUT9 ) with VREF ≥4.5 V Output Leakage Current I OUT VOUT = 50 V — 1.0 100 µA Output Saturation Voltage V OUT(SAT) IOUT = 1.0 A — 1.0 1.5 V IOUT = 1.6 A — 1.5 1.9 V Output Sustaining Voltage V OUT(sus) IOUT = 1.6 A, L = 2.5 mH 50 — — V Control Logic HSD Output Saturation Voltage V CE(SAT) IC = 20 mA — 0.5 1.0 V Logic Input Voltage V IN(1) 3.5 — 5.3 V Logic Input Current I IN VIN = 5.0 V — — 1.0 µA VIN = 0.8 V — -90 -180 µA Reference Input Current I REF VREF = 3.0 V — 500 900 µA Logic Supply Current I DD All Drivers OFF — 15 25 mA All Drivers ON, No Load — 55 75 mA Maximum Clock Frequency f clk 3.3 5.0 — MHz Serial Data Output Voltage V OUT(1) IOUT = -200 µA 4.5 4.7 — V VOUT(0) IOUT = 200 µA — 250 — mV Clock to Serial Data Out Delay t PD C L = 30 pF — — 300 ns Thermal Shutdown Temperature T J — 165 — °C Limits (VREF = 2.0 V) Continued next page... Dwg. EP-010-3 IN VDD Dw g. EP-021-2 OUT N <<1 Ω

9-BIT SERIAL-INPUT, LATCHED SINK DRIVER Worcester, Massachusetts 01615-0036 (508) 853-5000 Characteristic Symbol Test Conditions Min. Typ. Max. Units Chopping Characteristics (TJ = +25°C to +150°C) with Fast Clamp Diodes Enable Timeout t EN R EN = 20 kΩ , CEN = 0.01 µF 190 200 210 µs Chopping Frequency f ch R C = 20 kΩ , CC = 250 pF 90 100 110 kHz Duty Cycle Range dc t on / ton + toff 15 — < 50 % Chop Current Level I TRIP VREF = 2.0 V, fch < 100 kHz 0.9 1.0 1.1 A VREF = 2.8 V, fch < 100 kHz 1.26 1.4 1.54 A Output Current Control Range V REF 1.0 — 3.2 V ITRIP 0.5 — 1.6 A Delay t d ITRIP to IOUT(P), TA = +25°C — 300 500 ns Chop Inhibit Voltage Range V REF 4.5 — VDD + 0.3 V Negative current is defined as coming out of (sourcing) the specified device terminal. ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V, in Test Circuit/Typical Application (unless otherwise noted). Limits EXTERNAL HIGH-SIDE DRIVERS CHARGE-PUMP CIRCUITRY FOR SINGLE-SUPPLY OPERATIONPMOSNMOS V + 10 VBB VBB Dwg. EP-027 VBB Dwg. EP-028 VBB 10 V 0.022 µF Dw g. EP-026

9-BIT SERIAL-INPUT, LATCHED SINK DRIVER 20 µF 5 kΩ ±1% 20 kΩ OUTPUTS SERIAL DATA IN SERIAL DATA OUTGROUND V DD RC C RC EN 250 pF 0.01 µF Dwg. EP-023A V DD HIGH-SIDE DRIVER (HSD) +36 V LOADS (9) POWER NMOS CLOCK STROBE V REF IN9 CHARGE PUMP R CV 20 kΩ TEST CIRCUIT AND TYPICAL APPLICATION TRUTH TABLE Serial Shift Register Serial Latch Output Data Clock Contents* Data Strobe Contents* Contents* HSD Input Input I 1 I2 … I9 Output Input I 1 I2 …I 9 I1 I2 …I 9 OUTPUT HH R 1 … R 8 R 7 LL R 1 … R 8 R 7 HX H L XR 1 R 2 … R 9 R 8 XX … XX H R 1 R 2 … R 9 P1 P2 … P9 P8 LP 1 P2 … P9 P1 P2 … P9 H * Serial Data Output connected to Input9. L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State

9-BIT SERIAL-INPUT, LATCHED SINK DRIVER Worcester, Massachusetts 01615-0036 (508) 853-5000 IOUT(P) A B C D E CLOCK DATA IN STROBE HIGH-SIDE DRIVER OUT LOAD CURRENT Dwg. WP-011A td I TRIP F G H TO IOUT(asym) t off t on TIMING CONDITIONS TA = +25°C, Logic Levels are VDD and Ground A. Minimum Data Active Time Before Clock Pulse B. Minimum Data Active Time After Clock Pulse * Chopping is disabled if VREF is greater than 4.5 V.

9-BIT SERIAL-INPUT, LATCHED SINK DRIVER APPLICATIONS INFORMATION The UCN5829EB is designed to drive high-current, 9- or 24-wire (3 devices cascaded) dot matrix impact printer solenoids. The internal CMOS control logic: 1) selects the operating channels from a 9- or 24-bit word previously loaded into the shift register, 2) controls the peak load current of the output drivers via nine constant-frequency switch-mode current choppers, 3) sets a user-defined print enable time, and 4) turns ON an external high-side driver during the print enable interval. Data present at the SERIAL DATA INPUT is transferred to the shift register on the low-to-high transition of the CLOCK input pulse. The data must appear at the input prior to the rising edge of the clock input waveform. On succeeding clock pulses, the registers shift data infor- mation towards the SERIAL DATA OUTPUT. Information present at any register is transferred to its respective latch on the high-to-low transition of the STROBE (serial-to-parallel conversion). Drivers that have a logic high stored in their latch will be enabled for a set time interval (t EN ) generated by an internal one-shot. The output current is internally sensed and controlled in a fixed-frequency chopper format. Between strobe pulses, a new data word can be clocked in for the next print enable cycle. PRINT ENABLE TIME A high-to-low transition of the STROBE input starts an internal one-shot which sets the print enable time (t EN ) of the output drivers and the external high-side driver. The print enable time is determined by an external resistor (50 kΩ max) and capacitor (100 pF min) at RC EN as tEN =R EN CEN The print enable time can also be controlled from a microproces- sor. In this mode, the internal one-shot is operated as an output disable function. In this mode, R EN and CEN are not used; instead a 10 kΩ series resistor is connected between RCEN and an externally generated output disable pulse. As before, on the high-to-low STROBE transition, the outputs will be enabled. They will remain enabled until a low-to-high logic (≥3.3 V) DISABLE transition at RC EN . When operating in a continuous chopping mode, and neither print enable timeout nor output disable are desired, RCEN should be grounded.

9-BIT SERIAL-INPUT, LATCHED SINK DRIVER Worcester, Massachusetts 01615-0036 (508) 853-5000 HIGH-SIDE DRIVER To reduce the current decay time at the end of a print enable cycle, an external high-side driver can be used and controlled by the HIGH-SIDE DRIVER (HSD) output. The HSD is designed to drive an external N-channel MOSFET (with accompanying charge pump circuitry). During the print enable time (t EN ), the internal high-side driver is OFF, allowing the external high-side driver to be ON. If the external high-side driver is a P-channel device (eliminating the need for charge-pump circuitry), the HSD signal must be inverted for correct operation. If an external high-side driver is used, an external ground clamp diode is also required. OUTPUT CURRENT CONTROL Each of the nine channels consists of a power Darlington sink driver, internal low-value current-sensing resistor, comparator, and an R/S flip-flop. The output current is sensed and controlled indepen- dently in each channel by means of a fixed-frequency chopper which sets the flip-flop and allows the output to turn ON. As the current increases in the load it is sensed by the internal sense resistor until the sense voltage equals the trip voltage of the comparator. At this time, the flip-flop is reset and the output is turned OFF. Over the range of V REF = 1.0 V to 3.2 V, the output current trip point is a linear function of the reference voltage: ITRIP = VREF /2 To ensure an accurate chop current level, an external 5 kΩ resistor (RCV ) is used. The actual load current peak will be slightly higher than the trip point (especially for low-inductance loads) because of the internal logic and switching delays (typically 300 ns). After turn- off, the load current decays, circulating through the load and an external clamp diode. The output driver will stay OFF until the next chop pulse sets the flip-flop, turning ON the output, and allowing load current to rise again. The cycle repeats, maintaining the average printhead current at the desired level. The chop pulse frequency is determined by an external resistor and capacitor at RC C :

2 RC CC

To reduce the power supply and ground noise developed when operating nine channels synchronously, the outputs are split into two groups (OUTPUTS 2, 4, 6, 8 and OUTPUTS 1, 3, 5, 7, 9) for chopping pulses. fch =

9-BIT SERIAL-INPUT, LATCHED SINK DRIVER The chopping function is disabled when VREF > 4.5 V. To prevent operation at higher than allowable current levels, VREF should not exceed 3.2 V, except to disable the chopping function. DUTY CYCLE LIMITS For correct operation of the UCN5829EB, the duty cycle must be between 15% and 50% with 20% to 40% recommended. The lower limit is due to internal lockout circuitry while the upper limit guarantees synchronous operation. The duty cycle (dc) can be calculated as t on IOUT(P) / IOUT(asym) + vd / vc ton + toff 1 + vd / vc where IOUT(asym) = the asymptotic current value = vc/RL vd = discharge voltage across the load = VHSD + VDIODE vc = charge voltage across the load = VBB - VOUT(SAT) - VHSD For most practical cases, correct operation can be achieved if I OUT(asym) / IOUT(P) > 2.5. GENERAL For applications with 9-wire printheads, SERIAL DATA OUT should be connected to IN9. For 24-wire printhead applications, three devices (eight channels per device) are cascaded by connecting SERIAL DATA OUT to the next SERIAL DATA IN. Each of the CMOS logic inputs have internal pull-up resistors for TTL compatibility. An external transient-protection flyback diode is required at each output. Fast recovery diodes are recommended to reduce power dissipation in the UCN5829EB. Internal filtering prevents false trigger- ing of the current sense comparator which can be caused by the recovery current spike of the diodes when the outputs turn ON. The SUPPLY terminal should be well decoupled with a capacitor placed as close as possible to the device. Internal power-ON reset circuitry prevents false output triggering during power up. Thermal protection circuitry is activated and turns OFF all drivers at a junction temperature of typically +165°C. The thermal shutdown is independent of all other functions. It should not be used as another control input but is intended only to protect the chip from catastrophic failures due to excessive junction temperatures. The output drivers are re-enabled when the junction temperature cools down to approximately +145°C. ≈dc =

9-BIT SERIAL-INPUT, LATCHED SINK DRIVER Worcester, Massachusetts 01615-0036 (508) 853-5000 TYPICAL APPLICATION Shown is a typical application with the UCN5829EB controlling a chop current of 1 A through a 3 mH, 9 Ω load. To check the duty cycle and IOUT(asym) /IOUT(P) restrictions where v d =V HSD + VDIODE ≈ 1.5 + 1.5 = 3 vc =V BB - VOUT(SAT) - VHSD = 36 - 1.5 - 1.5 = 33 IOUT(asym) =v c / RL = 33 / 9 = 3.67 then I OUT(asym) / IOUT(P) = 3.67 / 1 = 3.67 The condition of IOUT(asym) / IOUT(P) > 2.5 is met and the duty cycle will be within the proscribed limits. The actual duty cycle is IOUT(P) /IOUT(asym) + vd/vc 1.0/3.67 + 2.5/33 dc = = = 32% 1 + vd/vc 1 + 2.5/33 For a 50 kHz chopping frequency and a 250 µs print enable time, the remaining component values are with C C = 250 pF and CEN = 0.01 µF then R C = 1/(2 fch CC ) = 1/(2 x 50 x 103 x 250 x 10-12) = 40 kΩ and R EN = tEN / CEN = 250 x 10-6 / 10 x 10-9 = 25 kΩ

9-BIT SERIAL-INPUT, LATCHED SINK DRIVER NOTES: 1. Webbed lead frame. Leads 7 through 17 and 29 through 39 are internally one piece. 2. Exact body and lead configuration at vendor’s option within limits shown. 3. Lead spacing tolerance is non-cumulative. Dimensions in Inches (controlling dimensions) 1828 Dwg. MA-005-44A in 0.020 MIN 0.050 BSC 144 0.021 0.013 INDEX AREA 2 6 1729 0.695 0.685 0.032 0.026 0.319 0.291 0.319 0.291 0.180 0.165 0.695 0.685 0.656 0.650 0.656 0.650

9-BIT SERIAL-INPUT, LATCHED SINK DRIVER Worcester, Massachusetts 01615-0036 (508) 853-5000 Dwg. MA-005-44A mm 17.65 17.40 0.51 MIN 4.57 4.20 17.65 17.40 16.662 16.510 1.27 BSC 0.812 0.661 144 0.533 0.331 INDEX AREA 40 6 16.662 16.510 8.10 7.39 8.10 7.39 Dimensions in Millimeters (for reference only) NOTES: 1. Webbed lead frame. Leads 7 through 17 and 29 through 39 are internally one piece. 2. Exact body and lead configuration at vendor’s option within limits shown. 3. Lead spacing tolerance is non-cumulative. The products described here are manufactured under one or more Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsi- bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.