5818-F

5818-F ALLEGRO

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Technical content

Dwg. PP-059-2 OUT14 27 28NC OUT NC BLNK 17OUT V OUT3 OUT2 OUT32 OUT31 REGISTER LATCHES LATCHES REGISTER Designed primarily for use with vacuum-fluorescent displays, the UCN5818AF and UCN5818EPF smart power BiMOS II drivers combine CMOS shift registers, data latches, and control circuitry, with bipolar high- speed sourcing outputs and DMOS active pull-down circuitry. The high- speed shift register and data latches allow direct interfacing with microproces- sor LSI-based systems. A CMOS serial data output enables cascade connec- tions in applications requiring additional drive lines. Both devices feature

60 V and -40 mA output ratings, allowing them to be used in many other

peripheral power driver applications. These smart power drivers have been designed with BiMOS II logic for improved data entry rates. With a 5 V supply, it will operate to at least 3.3 MHz. At 12 V, higher speeds are possible. Use of these devices with TTL may require the use of appropriate pull-up resistors to ensure an input logic high. All devices can be operated over the ambient temperature range of - 20°C to +85°C. The UCN5818AF is supplied in a 40-pin plastic dual in-line package with 0.600" (15.24 mm) row spacing. A copper lead frame, reduced supply current requirement, and low output saturation voltage permits operation with minimum junction temperature rise. The ‘A’ package allows all 32 outputs to be operated at -25 mA continuously over the operating temperature range. For high-density packaging applications, the UCN5818EPF is furnished in a 44-lead plastic chip carrier (quad pack) for surface mounting on solder lands with 0.050" (1.27 mm) centers. The PLCC allows -25 mA continuous operation of all outputs simultaneously at ambient temperatures to 60 °C. Similar devices are available as the UCN5810AF/LWF (10 bits), UCN5811A (12 bits), and UCN5812AF/EPF (20 bits). UCN5818EPF BiMOS II 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS Always order by complete part number, e.g., UCN5818EPF .

FEATURES

I High-Speed Source Drivers I To 3.3 MHz Data Input Rate I Low-Output Saturation Voltages I Active DMOS Pull-Downs I Low-Power CMOS Logic and Latches I Reduced Supply Current Requirements I Improved Replacements for SN75518N/FN ABSOLUTE MAXIMUM RATINGS at TA = 25°C Continuous Output Current, Input Voltage Range, Package Power Dissipation, P D Operating Temperature Range, Storage Temperature Range, * Derate at rate of 28 mW/ °C above TA = +25°C † Derate at rate of 22 mW/ °C above TA = +25°C Caution: CMOS devices have input static protection but are susceptible to damage when exposed to extremely high static electrical charges. Data Sheet26182.28C 5818-F

32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000 MOS BIPOLAR OUT 1 OUT 2GROUND Dwg. FP-013-1OUT 3 OUTN CLOCK SERIAL DATA IN STROBE BLANKING SERIAL DATA OUTSERIAL-PARALLEL SHIFT REGISTER LATCHES VDD VBB LOGIC SUPPLY LOAD SUPPLY UCN5818AF FUNCTIONAL BLOCK DIAGRAM TYPICAL OUTPUT DRIVER Dwg. No. A-14,219 V OUT BB N TYPICAL INPUT CIRCUIT 50 75 100 125 150 2.5 0.5 ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS AMBIENT TEMPERATURE IN °C 2.0 1.5 1.0 Dwg. GP-025A 3.0 SUFFIX 'EP', R = 46°C/WθJA SUFFIX 'A', R = 36°C/WθJA Dwg. GP-025A LOAD SUPPLY BBV OUT2 OUT7 OUT8 Dwg. PP-029-4 OUT31 OUT 30 OUT25 SERIAL DATA OUT BLANKING LOGIC SUPPLY SERIAL DATA IN STROBE GROUND CLOCKCLK STBLNK OUT9 OUT10 OUT15 OUT16 OUT24 OUT 23 OUT22 OUT17 LATCHES REGISTER REGISTER LATCHES 33 8 OUT6 OUT1 OUT4 OUT3 OUT 32 OUT 20 OUT 18 OUT14OUT19 OUT21 OUT11 OUT12 OUT13 OUT5 OUT 29 OUT 28 OUT27 OUT26 DDV Dwg. EP-010-5 IN VDD Copyright © 1988, 2000 Allegro MicroSystems, Inc.

32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS www.allegromicro.com ELECTRICAL CHARACTERISTICS at TA = + 25°C, VBB = 60 V unless otherwise noted. Limits @ VDD = 5 V Limits @ V DD = 12 V Output Leakage Current I CEX VOUT = 0 V, TA = +70°C — -5.0 -15 — -5.0 -15 µA Output Voltage V OUT(1) IOUT = -25 mA 58 58.5 — 58 58.5 — V VOUT(0) IOUT = 1 mA — 2.0 3.0 ——— V IOUT = 2 mA ——— — 2.0 3.5 V Output Pull-Down Current I OUT(0) VOUT = 5 V to VBB 2.0 3.5 — ——— mA VOUT = 20 V to VBB ——— 8.0 13 — mA Input Voltage V IN(1) 3.5 — 5.3 10.5 — 12.3 V Input Current I IN(1) VIN = VDD — 0.05 0.5 — 0.1 1.0 µA Serial Data Output Voltage V OUT(1) IOUT = -200 µA 4.5 4.7 — 11.7 11.8 — V VOUT(0) IOUT = 200 µA — 200 250 — 100 200 mV Maximum Clock Frequency f clk 3.3* —— ——— MHz Supply Current I DD(1) All Outputs High — 100 300 — 200 500 µA IDD(0) All Outputs Low — 100 300 — 200 500 µA IBB(1) Outputs High, No Load — 3.0 6.0 — 3.0 6.0 mA IBB(0) Outputs Low — 10 100 — 10 100 µA Blanking to Output Delay t PHL CL = 30 pF, 50% to 50% — 2000 —— 1000 — ns tPLH CL = 30 pF, 50% to 50% — 1000 —— 850 — ns Output Fall Time t f CL = 30 pF, 90% to 10% — 1450 —— 650 — ns Output Rise Time t r CL = 30 pF, 10% to 90% — 650 —— 700 — ns Negative current is defined as coming out of (sourcing) the specified device terminal. * Operation at a clock frequency greater than the specified minimum value is possible but not warranteed.

32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS Worcester, Massachusetts 01615-0036 (508) 853-5000 TRUTH TABLE Serial Shift Register Contents Serial Latch Contents Output Contents Data Clock Data Strobe Input Input I HH R 1 R2 ... R N-2 RN-1 RN-1 LL R 1 R2 ... R N-2 RN-1 RN-1 XR 1 R2 R3 ... R N-1 RN RN L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State Serial Data present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUT- PUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is trans- ferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the BLANKING input be high during serial data entry. When the BLANKING input is high, the output source drivers are disabled (OFF); the DMOS sink drivers are ON, the information stored in the latches is not affected by the BLANKING input. With the BLANKING input low, the outputs are controlled by the state of their respective latches. TIMING REQUIREMENTS (TA = +25°C,VDD = 5 V, Logic Levels are VDD and Ground) A. Minimum Data Active Time Before Clock Pulse B. Minimum Data Active Time After Clock Pulse G. Typical Time Between Strobe Activation and Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable with increased supply voltage; operation at high temperatures will reduce the specified maximum clock frequency. E F CLOCK DATA IN STROBE BLANKING OUTN A D B C G Dwg. No. A-12,649A

32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS www.allegromicro.com UCN5818AF Dimensions in Inches (controlling dimensions) Dimensions in Millimeters (for reference only) NOTES: 1. Exact body and lead configuration at vendor ’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. 4. Supplied in standard sticks/tubes of 9 devices. 0.580 0.485 12 3 0.250 MAX 0.070 0.030 0.015 MIN 0.022 0.014 0.015 0.008 0.600 BSC Dwg. MA-003-40 in 0.100 BSC 0.005 MIN 0.200 0.115 0.700 MAX 2.095 1.980 14.73 12.32 12 3 6.35 MAX 1.77 0.77 0.39 MIN 0.558 0.356 0.381 0.204 15.24 BSC Dwg. MA-003-40 mm 2.54 BSC 0.13 MIN 5.08 2.93 17.78 MAX 53.2 50.3

32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS Worcester, Massachusetts 01615-0036 (508) 853-5000 UCN5818EPF Dimensions in Inches (controlling dimensions) Dimensions in Millimeters (for reference only) NOTES: 1. Exact body and lead configuration at vendor ’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Supplied in standard sticks/tubes of 27 devices or add “TR” to part number for tape and reel. 1828 Dwg. MA-005-44A in 0.020 MIN 0.050 BSC 144 0.021 0.013 INDEX AREA 2 6 1729 0.695 0.685 0.032 0.026 0.319 0.291 0.319 0.291 0.180 0.165 0.695 0.685 0.656 0.650 0.656 0.650 Dwg. MA-005-44A mm 17.65 17.40 0.51 MIN 4.57 4.20 17.65 17.40 16.662 16.510 1.27 BSC 0.812 0.661 144 0.533 0.331 INDEX AREA 16.662 16.510 8.10 7.39 8.10 7.39

32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS www.allegromicro.com The products described here are manufactured under one or more Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsi- bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.

32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS Worcester, Massachusetts 01615-0036 (508) 853-5000 POWER INTERFACE DRIVERS Function Output Ratings* Part Number † SERIAL-INPUT LATCHED DRIVERS 8-Bit (saturated drivers) -120 mA 50 V‡ 5895 8-Bit 350 mA 50 V 5821 8-Bit 350 mA 80 V 5822 8-Bit 350 mA 50 V‡ 5841 8-Bit 350 mA 80 V‡ 5842 8-Bit (constant-current LED driver) 75 mA 17 V 6275 8-Bit (DMOS drivers) 250 mA 50 V 6595 8-Bit (DMOS drivers) 350 mA 50 V‡ 6A595 8-Bit (DMOS drivers) 100 mA 50 V 6B595 10-Bit (active pull-downs) -25 mA 60 V 5810-F and 6809/10 12-Bit (active pull-downs) -25 mA 60 V 5811 and 6811 16-Bit (constant-current LED driver) 75 mA 17 V 6276 20-Bit (active pull-downs) -25 mA 60 V 5812-F and 6812 32-Bit (active pull-downs) -25 mA 60 V 5818-F and 6818 32-Bit 100 mA 30 V 5833 32-Bit (saturated drivers) 100 mA 40 V 5832 PARALLEL-INPUT LATCHED DRIVERS 4-Bit 350 mA 50 V‡ 5800 8-Bit -25 mA 60 V 5815 8-Bit 350 mA 50 V‡ 5801 8-Bit (DMOS drivers) 100 mA 50 V 6B273 8-Bit (DMOS drivers) 250 mA 50 V 6273 SPECIAL-PURPOSE DEVICES Unipolar Stepper Motor Translator/Driver 1.25 A 50 V‡ 5804 Addressable 8-Bit Decoder/DMOS Driver 250 mA 50 V 6259 Addressable 8-Bit Decoder/DMOS Driver 350 mA 50 V‡ 6A259 Addressable 8-Bit Decoder/DMOS Driver 100 mA 50 V 6B259 Addressable 28-Line Decoder/Driver 450 mA 30 V 6817 * Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits. Negative current is defined as coming out of (sourcing) the output. † Complete part number includes additional characters to indicate operating temperature range and package style. ‡ Internal transient-suppression diodes included for inductive-load protection.