5817

5817 ALLEGRO

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Shown For Reference OnlyReplaced by A6817SEP. 17 29 Dwg. PP-050 INC GNDIC GND IC IC CHIP ENABLE LOGIC SUPPLY GND GND INB 4-TO-14 LINE DECODER OUTPUT DRIVER BANK A OUTPUT DRIVER BANK B OUT B0 NC OUT A9 OUT A8 OUT A7 OUT A6 OUT A5 OUT A4 OUT A3 OUT A2 OUT A1 OUT A0 OUT B1 OUT B2 OUT B3 OUT B4 OUT B5 OUT B6 OUT B7 OUT B8 OUT B9 OUTPUT ENABLE B OUTPUT ENABLE A OUT B10 OUT B11 OUT B12 OUT B13 OUT A13 OUT A12 OUT A11 OUT A10 V DD IN (MSB)D IN (LSB)A Always order by complete part number:A5817SEP . ADDRESSABLE 28-LINE DECODER/DRIVER ABSOLUTE MAXIMUM RATINGS at TA = 25°C Input Voltage Range, Operating Temperature Range, Storage Temperature Range, *Derate at rate of 22 mW/°C above TA = 25°C. Caution: CMOS devices have input static protection but are susceptible to damage when exposed to extremely high static electrical charges. Data Sheet 26186.20 581 7 Intended for use in ink-jet printer applications, the A5817SEP addressable 28-line decoder/driver combines low-power CMOS inputs and logic with 28 high-current, high-voltage bipolar outputs. A 4-to-14 line decoder determines the selected output driver (n) in each 14-driver bank. Two independent output enable inputs (active low) then provide the final decoding to activate 1- or 2-of-28 outputs (OUT An and/or OUTBn). Special internal circuitry is programmed at the time of manufacture to adjust the output pulse timing and thereby the energy the device delivers to the ink-jet print head. The CMOS inputs cause minimal loading and are compatible with standard CMOS, PMOS, and NMOS logic. Use with TTL or DTL circuits may require appropriate pull-up resistors to ensure an input logic high. The internal CMOS logic operates from a 5 V supply. A CHIP ENABLE function is provided to lock out the drivers during system power up. The 28 bipolar power outputs are open-collector

30 V Darlington drivers capable of sinking 500 mA at ambient

temperatures up to 85°C. The A5817SEP is furnished in a 44-lead plastic chip carrier (quad pack) for minimum-area, surface-mount applications.

FEATURES

I Controlled Characteristics for Ink-Jet Printers I Addressable Data Entry I 30 V Minimum V(BR)CEX I CMOS, PMOS, NMOS Compatible Inputs I Low-Power CMOS Logic

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000 Dwg. FP-032 4-TO-14 LINE DECODER CHIP ENABLE IN (MSB)D IN (LSB)A IN B INC LOGIC SUPPLY OUTPUT ENABLE A OUTPUT ENABLE B OUT A0 OUT A1 OUT A2 OUT A11 OUT A12 OUT A13 OUT B0 OUT B1 OUT B2 OUT B11 OUT B12 OUT B13 TURN-ON DELAY TURN-ON DELAY FUNCTIONAL BLOCK DIAGRAM TYPICAL INPUT CIRCUIT TYPICAL OUTPUT DRIVER Dwg. EP-010-1 IN VDD Dwg. EP-021-7 OUT N W Copyright © 1993, Allegro MicroSystems, Inc.

ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5.0 V. Limits Characteristic Symbol Test Conditions Min Typ Max Units Output Drivers Output Leakage Current I CEX VCE = 30 V — <1.0 100 µA Output Saturation Voltage V CE(SAT) IOUT = 450 mA 0.85 1.15 1.45 V IOUT = 400 mA 0.8 1.1 1.4 V Output Breakdown Voltage V (BR)CEX R L = 56 Ω 30 — — V Unclamped Inductive — V CC = 30 V, L = 3 µH, RL = 56 Ω , See Note — Load Current I L = 500 mA, Test Fig. Turn-On Time t PHL VCC = 21 V, RL = 39 Ω 125 225 475 ns Fall Time t f VCC = 21 V, RL = 39 Ω —2 0—n s Turn-Off Time t PLH VCC = 21 V, RL = 39 Ω 175 250 400 ns Rise Time t r VCC = 21 V, RL = 39 Ω —5 0—n s Control Logic Logic Input Voltage V IN(1) 3.5 — — V VIN(0) — — 0.8 V Logic Input Current I IN(1) VIN = 5.0 V — <1.0 100 µA IIN(0) VIN = 0 V — <-1.0 -100 µA Input Resistance R IN 50 — — k Ω Supply Current I DD(ON) Two Outputs ON — 6.0 10.0 mA IDD(OFF) All Drivers OFF, All Inputs = 0 V, — — 600 µA OE A = OEB = VDD Note: Device will turn off and meet all specifications after test.

Worcester, Massachusetts 01615-0036 (508) 853-5000 OUTPUT ENABLE (A and/or B) INA-D A B ENABLEt PLHtPHLt OUTt 50% 10% 90% t 50% 10% 90% trf Dwg. WP-017 OUTPUT VOLTAGE N L V CC R Dwg. EP-044 IL OUT N UNCLAMPED INDUCTIVE LOAD CURRENT TEST FIGURE TIMING CONDITIONS (Logic Levels are VDD and Ground)

This device is intended specifically for, although certainly not limited to, driving ink-jet print heads. In this application, a certain minimum energy (a function of load voltage and output pulse duration) is required for proper operation, while excessive energy will degrade the life of the print head. The output pulse duration (t OUT ) is equal to tENABLE + tPLH – tPHL , where tPHL is adjusted during manufacture to compensate for variations in the output saturation voltage (VCE(SAT)). For the A5817SEP, the relationship between tOUT and tENABLE at TA = 25°C is: tOUT = tENABLE ([VCE(SAT) (actual) – VCE(SAT)(typical)] x 330 ns) + 25 ns + 110 ns. For most applications, this will result in a driver- contribution-to-energy-error of less than ±4%. A logic low on the CHIP ENABLE input will prevent the drivers from turning ON, regardless of the state of other inputs or the logic supply voltage. The CHIP ENABLE input has a slow response time and should not be used as a high-speed control line. For proper operation, all ground terminals should be connected to a common ground on the printed wiring board. The IC (Internal Connection) terminals are used to program the turn-on time of the device and MUST be left electrically unconnected (floating) for proper operation. DECODER TRUTH TABLE IND INC INB INA (MSB) (LSB) N 00000 00011 00102 00113 01004 01015 01106 01117 10008 10019 1010 1 0 1011 1 1 1100 1 2 1101 1 3

1110 ALL OFF

1111 ALL OFF

Depending on the four address inputs, the 4-to-14 line decoder selects one driver from each of the 14 output A and B banks of sink drivers according to the Decoder Truth Table. The state of the selected outputs is deter- mined by the OUTPUT ENABLE inputs as shown in the Enable Truth Table. CHIP OUTPUT OUTPUT OUTPUTS (OFF unless otherwise specified. ENABLE ENABLE A ENABLE B For the value of N see the Decoder Truth Table)

0 X X ALL OFF

1 0 0 OUT AN ON, OUT BN ON X = Irrelevant ENABLE TRUTH TABLE

Worcester, Massachusetts 01615-0036 (508) 853-5000 NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 1828 Dwg. MA-005-44A in 0.020 MIN 0.050 BSC 144 0.021 0.013 INDEX AREA 2 6 1729 0.695 0.685 0.032 0.026 0.319 0.291 0.319 0.291 0.180 0.165 0.695 0.685 0.656 0.650 0.656 0.650 Dwg. MA-005-44A mm 17.65 17.40 0.51 MIN 4.57 4.20 17.65 17.40 16.662 16.510 1.27 BSC 0.812 0.661 144 0.533 0.331 INDEX AREA 40 6 16.662 16.510 8.10 7.39 8.10 7.39 Dimensions in Inches (for reference only) Dimensions in Millimeters (controlling dimensions) Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the design of its products. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibil- ity for its use; nor for any infringements of patents or other rights of third parties which may result from its use.