5815

5815 ALLEGRO

Document overview

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Technical content

Designed primarily for use with high-voltage vacuum-fluorescent displays, the UCN5815A and UCN5815EP BiMOS II integrated circuits consist of eight npn Darlington source drivers with output pull- down resistors, a CMOS latch for each driver, and common STROBE, BLANKING, and ENABLE functions. BiMOS II devices have considerably better data-input rates than the original BiMOS circuits. With a 5 V logic supply, they will operate to at least 4.4 MHz. With a 12 V supply, significantly higher speeds are obtained. The CMOS inputs cause minimum loading and are compatible with standard CMOS and NMOS logic commonly found in microprocessor designs. TTL circuits may require the use of appropri- ate pull-up resistors. The bipolar outputs may be used as segment, dot (matrix), bar, or digit drivers in vacuum-fluorescent displays. All eight outputs can be activated simultaneously at ambient temperatures in excess of 75 °C. To simplify printed wiring board layout, output connections are opposite the inputs. A minimum component display subsystem, requiring few or no discrete components, can be assembled using the UCN5815A/EP with the UCN5810AF/EPF/LWF, UCN5812AF/EPF, or UCN5818AF/EPF serial-to-parallel latched drivers. Suffix ‘A’ devices are furnished in a standard 22-pin plastic DIP; suffix ‘EP’ indicates a 28-lead PLCC. BiMOS II 8-BIT LATCHED SOURCE DRIVERS UCN5815A

FEATURES

I To 4.4 MHz Date-lnput Rate I High-Voltage Source Outputs I CMOS, NMOS, TTL Compatible Inputs I Low-Power CMOS Latches I Internal Pull-Down Resistors I Wide Supply-Voltage Range Always order by complete part number: Part Number Package UCN5815A 22-Pin DIP UCN5815EP 28-Lead PLCC ABSOLUTE MAXIMUM RATINGS at +25°C Free-Air Temperature Logic Supply Voltage Range, Load Supply Voltage Range, Input Voltage Range, Continuous Output Current, Package Power Dissipation, P D Operating Temperature Range, Storage Temperature Range, * Derate linearly to 0 W at +150 °C. Caution: CMOS devices have input static protection but are susceptible to damage when exposed to extremely high static electrical charges. Data Sheet26183.10A* 5815 22 1 LOGIC SUPPLY ENABLE 1 BLANKING STROBE VDD 7 16 OUT1 OUT2 OUT3 OUT4 IN1 IN2 IN 3 IN 4 11 12 GROUND OUT5 OUT6 OUT7 Dwg. PP-015-3 OUT8 LOAD SUPPLY IN5 IN6 IN 7 IN 8 LATCHES VBB

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000 ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 60 V, VDD = 5 V and 12 V (unless otherwise noted). Limits Characteristic Symbol Test Conditions Min. Max. Units Output Off Voltage V OUT — 1.0 V Output On Voltage V OUT IOUT = -25 mA, VBB = 60 V 57.5 — V Output Pull-Down Current I OUT VOUT = VBB 400 850 µA Output Leakage Current I OUT TA = 70°C — -15 µA Input Voltage V IN(1) VDD = 5.0 V 3.5 5.3 V VDD = 12 V 10.5 12.3 V VIN(0) -0.3 +0.8 V Input Current I IN(1) VDD = VIN = 5.0 V — 100 µA VDD = VIN = 12 V — 240 µA Input lmpedance Z IN VDD = 5.0 V 50 — k Ω Supply Current l BB All outputs on, All outputs open — 10.5 mA All outputs off, All outputs open — 100 µA l DD VDD = 5.0 V, All outputs off, All inputs = 0 V — 100 µA VDD = 12 V, All outputs off, All inputs = 0 V — 200 µA VDD = 5.0 V, One output on, All inputs = 0 V — 1.0 mA VDD = 12 V, One output on, All inputs = 0 V — 3.0 mA NOTE: Positive (negative) current is defined as going into (coming out of) the specified device pin. TYPICAL INPUT CIRCUIT TYPICAL OUTPUT DRIVER IN VDD Dwg. No. EP-010-4A Dwg. No. EP-021-3 OUT 100 K VBB Copyright © 1984, 2000 Allegro MicroSystems, Inc.

Dwg. No. A-14,357 Information present at an input is trans- ferred to its latch when the STROBE and ENABLE are high. The latches will continue to accept new data as long as both STROBE and ENABLE are held high. With either STROBE or ENABLE in the low state, no information can be loaded into the latches. When the BLANKING input is high, all of the output buffers are disabled (off) without affecting the information stored in the latches. With the BLANKING input low, the outputs are controlled by the state of the latches. Dwg. No. A-10,991 TIMING CONDITIONS (VDD = 5 V, TA = +25°C, Logic Levels are VDD and Ground) A. Minimum Data Active Time Before Strobe Enabled B. Minimum Data Active Time After Strobe Disabled D. Typical Time Between Strobe Activation and Output E. Typical Time Between Strobe Activation and Output INPUTS OUT N INN STROBE ENABLE BLANK T-1 T 0 110 X 0 1 110 X 1 XX X 1 X 0 X0 X 0 1 1 X0 X 0 0 0 XX 0 0 1 1 XX 0 0 0 0 X = irrelevant T-1 = previous output state T = present output state TRUTH TABLE Timing is representative of a 4.4 MHz data input rate. Higher speeds may be attainable with increased supply voltage; operation at high temperatures will reduce the specified maximum clock frequency.

Worcester, Massachusetts 01615-0036 (508) 853-5000 UCN5815A Dimensions in Inches (cvontrolling dimensions) Dimensions in Millimeters (for reference only) NOTES: 1. Exact body and lead configuration at vendor ’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. 4. Supplied in standard sticks/tubes of 17 devices. 12 3 11 0.380 0.330 0.210 MAX 0.070 0.030 0.015 MIN 0.022 0.014 0.100 BSC 0.005 MIN 0.160 0.115 0.015 0.008 0.400 BSC Dwg. MA-002-22 in 0.500 MAX 1.120 1.050 12 3 11 9.65 8.39 5.33 MAX 0.070 0.030 28.44 26.67 0.39 MIN 0.558 0.356 2.54 BSC 0.13 MIN 4.06 2.93 0.381 0.204 10.16 BSC Dwg. MA-002-22 mm 12.70 MAX

(controlling dimensions NOTES: 1. Exact body and lead configuration at vendor ’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Supplied in standard sticks/tubes of 38 devices or add “TR” to part number for tape and reel. Dimensions in Millimeters (for reference only) 18 12 0.020 MIN 0.050 BSC 128 INDEX AREA Dwg. MA-005-28A in 0.026 0.032 0.013 0.021 19 11 0.165 0.180 0.495 0.485 0.456 0.450 0.495 0.485 0.456 0.450 0.219 0.191 0.219 0.191 0.51 MIN 4.57 4.20 1.27 BSC 12.57 12.32 11.582 11.430 128 INDEX AREA Dwg. MA-005-28A mm 0.812 0.661 0.331 0.533 12.57 12.32 26 18 12 11.58 11.43 5.56 4.85 5.56 4.85

Worcester, Massachusetts 01615-0036 (508) 853-5000 POWER INTERFACE DRIVERS Function Output Ratings* Part Number † SERIAL-INPUT LATCHED DRIVERS 8-Bit (saturated drivers) -120 mA 50 V‡ 5895 8-Bit 350 mA 50 V 5821 8-Bit 350 mA 80 V 5822 8-Bit 350 mA 50 V‡ 5841 8-Bit 350 mA 80 V‡ 5842 8-Bit (constant-current LED driver) 75 mA 17 V 6275 8-Bit (DMOS drivers) 250 mA 50 V 6595 8-Bit (DMOS drivers) 350 mA 50 V‡ 6A595 8-Bit (DMOS drivers) 100 mA 50 V 6B595 10-Bit (active pull-downs) -25 mA 60 V 5810-F and 6809/10 12-Bit (active pull-downs) -25 mA 60 V 5811 and 6811 16-Bit (constant-current LED driver) 75 mA 17 V 6276 20-Bit (active pull-downs) -25 mA 60 V 5812-F and 6812 32-Bit (active pull-downs) -25 mA 60 V 5818-F and 6818 32-Bit 100 mA 30 V 5833 32-Bit (saturated drivers) 100 mA 40 V 5832 PARALLEL-INPUT LATCHED DRIVERS 4-Bit 350 mA 50 V‡ 5800 8-Bit -25 mA 60 V 5815 8-Bit 350 mA 50 V‡ 5801 8-Bit (DMOS drivers) 100 mA 50 V 6B273 8-Bit (DMOS drivers) 250 mA 50 V 6273 SPECIAL-PURPOSE DEVICES Unipolar Stepper Motor Translator/Driver 1.25 A 50 V‡ 5804 Addressable 8-Bit Decoder/DMOS Driver 250 mA 50 V 6259 Addressable 8-Bit Decoder/DMOS Driver 350 mA 50 V‡ 6A259 Addressable 8-Bit Decoder/DMOS Driver 100 mA 50 V 6B259 Addressable 28-Line Decoder/Driver 450 mA 30 V 6817 * Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits. Negative current is defined as coming out of (sourcing) the output. † Complete part number includes additional characters to indicate operating temperature range and package style. ‡ Internal transient-suppression diodes included for inductive-load protection.