5812

5812-F ALLEGRO

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 8

Technical content

FEATURES

I High-Speed Source Drivers I 60 V Source Outputs I To 3.3 MHz Data Input Rate I Low Output-Saturation Voltages I Low-Power CMOS Logic and Latches BiMOS II 20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS The UCN5812AF/EPF combine a 20-bit CMOS shift register, data latches, and control circuitry with high-voltage bipolar source drivers and active DMOS pull-downs for reduced supply current requirements. Although designed primarily for vacuum-fluorescent displays, the high-voltage, high- current outputs also allow them to be used in other peripheral power driver applications. They are improved versions of the original UCN5812A/EP. The CMOS shift register and latches allow direct interfacing with microprocessor-based systems. With a 5 V supply, they will operate to at least 3.3 MHz. At 12 V, higher speeds are possible. Especially useful for inter-digit blanking, the BLANKING input disables the output source drives and turns on the DMOS sink drivers. Use with TTL may require the use of appropriate pull-up resistors to ensure an input logic high. A CMOS serial data output enables cascade connections in applications requiring additional drive lines. Similar devices are available as the UCN5810AF/LWF (10 bits), UCN5811A (12 bits), and UCN5818AF/EPF (32 bits). The output source drivers are high-voltage pnp-npn Darlingtons with a minimum breakdown of 60 V and are capable of sourcing up to 40 mA. The DMOS active pull-downs are capable of sinking up to 15 mA. The UCN5812AF is supplied in a 28-pin dual in-line plastic package with 0.600" (15.24 mm) row spacing. For surface mounting, the UCN5812EPF is furnished in 28-lead plastic chip carrier (quad pack) with 0.050"(1.22 mm) centers. Copper lead-frames, reduced supply current requirements and lower output saturation voltages, allow continuous operation, with all outputs sourcing 25 mA, of the UCN5812AF over the operating temperature range, and the UCN5812EPF up to +75 °C. All devices are also available for opera- tion between -40°C and +85°C. To order, change the prefix from ‘UCN’ to ‘UCQ’. Always order by complete part number, e.g., UCN5812AF . Data Sheet26182.26B I Active DMOS Pull-Downs I Reduced Supply Current Requirements I Improved Replacement for TL5812 ABSOLUTE MAXIMUM RATINGS at TA = 25°C Continuous Output Current Range, Input Voltage Range, Package Power Dissipation, P D Operating Temperature Range, Storage Temperature Range, * Derate at rate of 25 mW/ °C above TA = +25°C † Derate at rate of 15 mW/ °C above TA = +25°C Caution: Allegro CMOS devices have input static protection but are susceptible to damage when exposed to extremely high static electrical charges. Note that the UCN5812AF (dual in-line package) and UCN5812EPF (PLCC package) are electri- cally identical and share a common terminal number assignment. UCN5812EPF 16 28 VDD Dwg. PP-059-1 OUT10 OUT20 OUT11 OUT19 REGISTER LATCHES VBBCLOCK ST CLK SERIAL DATA OUT LOAD SUPPLY SERIAL DATA IN STROBE GROUND LOGIC SUPPLY BLANKING 18OUT9 OUT1 OUT2 OUT8 OUT18 OUT12 LATCHES REGISTER 5812-F

20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000 UCN5812AF FUNCTIONAL BLOCK DIAGRAM TYPICAL OUTPUT DRIVERTYPICAL INPUT CIRCUIT Dwg. No. A-14,219 V OUT BB N MOS BIPOLAR OUT 1 OUT 2GROUND Dwg. FP-013-1OUT 3 OUT N CLOCK SERIAL DATA IN STROBE BLANKING SERIAL DATA OUTSERIAL-PARALLEL SHIFT REGISTER LATCHES VDD VBB LOGIC SUPPLY LOAD SUPPLY 10 19 LOAD SUPPLY BBV OUT 2 OUT7 OUT8 Dwg. PP-029-7 OUT19 OUT18 OUT13 14 27 SERIAL DATA OUT BLANKING LOGIC SUPPLY STROBE GROUND CLOCKCLK STBLNK OUT9 OUT 10 OUT12 OUT11 LATCHES REGISTER REGISTER LATCHES 32 6 SERIAL DATA IN OUT 6 OUT 1 OUT 4 OUT 3 OUT20 OUT5 OUT 17 OUT 16 OUT15 OUT14 DDV Dwg. EP-010-5 IN VDD Copyright © 1988, 2000 Allegro MicroSystems, Inc.

20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS www.allegromicro.com Limits @ VDD = 5 V Limits @ V DD = 12 V Output Leakage Current I CEX VOUT = 0 V, TA = +70°C — -5.0 -15 — -5.0 -15 µA Output Voltage V OUT(1) IOUT = -25 mA, VBB = 60 V 58 58.5 — 58 58.5 — V VOUT(0) IOUT = 1 mA — 2.0 3.0 ——— V IOUT = 2 mA ——— — 2.0 3.5 V Output Pull-Down Current I OUT(0) VOUT = 5 V to VBB 2.0 3.5 — ——— mA VOUT = 20 V to VBB ——— 8.0 13 — mA Input Voltage V IN(1) 3.5 — 5.3 10.5 — 12.3 V Input Current I IN(1) VIN = VDD — 0.05 0.5 — 0.1 1.0 µA Serial Data V OUT(1) IOUT = -200 µA 4.5 4.7 — 11.7 11.8 — V VOUT(0) IOUT = 200 µA — 200 250 — 100 200 mV Maximum Clock Frequency f clk 3.3* —— ——— MHz Supply Current I DD(1) All Outputs High — 100 300 — 200 500 µA IDD(0) All Outputs Low — 100 300 — 200 500 µA IBB(1) Outputs High, No Load — 1.5 4.0 — 1.5 4.0 mA IBB(0) Outputs Low — 10 100 — 10 100 µA Blanking to Output Delay t PHL CL = 30 pF, 50% to 50% — 2000 —— 1000 — ns tPLH CL = 30 pF, 50% to 50% — 1000 —— 850 — ns Output Fall Time t f CL = 30 pF, 90% to 10% — 1450 —— 650 — ns Output Rise Time t r CL = 30 pF, 10% to 90% — 650 —— 700 — ns Negative current is defined as coming out of (sourcing) the specified device pin. * Operation at a clock frequency greater than the specified minimum value is possible but not warranteed. ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 60 V (unless otherwise noted).

20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS Worcester, Massachusetts 01615-0036 (508) 853-5000 TRUTH TABLE Serial Shift Register Contents Serial Latch Contents Output Contents Data Clock Data Strobe Input Input I 1 I2 I3 …I N-1 IN Output Input I 1 I2 I3 …I N-1 IN Blanking I 1 I2 I3 …I N-1 IN HH R 1 R2 … RN-2 RN-1 RN-1 LL R 1 R2 … RN-2 RN-1 RN-1 XR 1 R2 R3 … RN-1 RN RN XXX … XX X L R 1 R2 R3 … RN-1 RN P1 P2 P3 … PN-1 PN PN HP 1 P2 P3 … PN-1 PN LP 1 P2 P3 … PN1 PN XXX … XX H LLL … LL L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State Dwg. No. 12,649A Serial Data present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input pulse. On succeed- ing CLOCK pulses, the registers shift data information towards the SERIAL DATA OUT- PUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is trans- ferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the BLANKING input be high during serial data entry. When the BLANKING input is high, the output source drivers are disabled (OFF); the DMOS sink drivers are ON, the information stored in the latches is not affected by the BLANKING input. With the BLANKING input low, the outputs are controlled by the state of their respective latches. E F CLOCK DATA IN STROBE BLANKING OUTN A D B C G TIMING REQUIREMENTS (TA = +25°C,VDD = 5 V, Logic Levels are VDD and Ground) A. Minimum Data Active Time Before Clock Pulse B. Minimum Data Active Time After Clock Pulse G. Typical Time Between Strobe Activation and Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable with increased supply voltage; operation at high temperatures will reduce the specified maximum clock frequency.

20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS www.allegromicro.com UCN5812AF Dimensions in Inches (controlling dimensions) NOTES: 1. Exact body and lead configuration at vendor ’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. 4. Supplied in standard sticks/tubes of 12 devices. Dimensions in Millimeters (for reference only) 14.73 12.32 12 3 6.35 MAX 1.77 0.77 0.39 MIN 0.558 0.356 0.381 0.204 15.24 BSC Dwg. MA-003-28 mm 2.54 BSC 0.13 MIN 5.08 2.93 17.78 MAX 39.7 35.1 12 3 0.250 MAX 0.070 0.030 0.015 MIN 0.022 0.014 0.015 0.008 0.600 BSC Dwg. MA-003-28 in 0.100 BSC 0.005 MIN 0.200 0.115 0.700 MAX 1.565 1.380 0.580 0.485

20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS Worcester, Massachusetts 01615-0036 (508) 853-5000 UCN5812EPF Dimensions in Inches (controlling dimensions) NOTES: 1. Exact body and lead configuration at vendor ’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Supplied in standard sticks/tubes of 38 devices or add “TR” to part number for tape and reel. 0.51 MIN 4.57 4.20 1.27 BSC 12.57 12.32 11.582 11.430 128 INDEX AREA Dwg. MA-005-28A mm 0.812 0.661 0.331 0.533 12.57 12.32 18 12 11.58 11.43 5.56 4.85 5.56 4.85 18 12 0.020 MIN 0.050 BSC 128 INDEX AREA Dwg. MA-005-28A in 0.026 0.032 0.013 0.021 19 11 0.165 0.180 0.495 0.485 0.456 0.450 0.495 0.485 0.456 0.450 0.219 0.191 0.219 0.191 Dimensions in Millimeters (for reference only)

20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS www.allegromicro.com The products described here are manufactured under one or more Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsi- bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.

20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS Worcester, Massachusetts 01615-0036 (508) 853-5000 POWER INTERFACE DRIVERS Function Output Ratings* Part Number † SERIAL-INPUT LATCHED DRIVERS 8-Bit (saturated drivers) -120 mA 50 V‡ 5895 8-Bit 350 mA 50 V 5821 8-Bit 350 mA 80 V 5822 8-Bit 350 mA 50 V‡ 5841 8-Bit 350 mA 80 V‡ 5842 8-Bit (constant-current LED driver) 75 mA 17 V 6275 8-Bit (DMOS drivers) 250 mA 50 V 6595 8-Bit (DMOS drivers) 350 mA 50 V‡ 6A595 8-Bit (DMOS drivers) 100 mA 50 V 6B595 10-Bit (active pull-downs) -25 mA 60 V 5810-F and 6809/10 12-Bit (active pull-downs) -25 mA 60 V 5811 and 6811 16-Bit (constant-current LED driver) 75 mA 17 V 6276 20-Bit (active pull-downs) -25 mA 60 V 5812-F and 6812 32-Bit (active pull-downs) -25 mA 60 V 5818-F and 6818 32-Bit 100 mA 30 V 5833 32-Bit (saturated drivers) 100 mA 40 V 5832 PARALLEL-INPUT LATCHED DRIVERS 4-Bit 350 mA 50 V‡ 5800 8-Bit -25 mA 60 V 5815 8-Bit 350 mA 50 V‡ 5801 8-Bit (DMOS drivers) 100 mA 50 V 6B273 8-Bit (DMOS drivers) 250 mA 50 V 6273 SPECIAL-PURPOSE DEVICES Unipolar Stepper Motor Translator/Driver 1.25 A 50 V‡ 5804 Addressable 8-Bit Decoder/DMOS Driver 250 mA 50 V 6259 Addressable 8-Bit Decoder/DMOS Driver 350 mA 50 V‡ 6A259 Addressable 8-Bit Decoder/DMOS Driver 100 mA 50 V 6B259 Addressable 28-Line Decoder/Driver 450 mA 30 V 6817 * Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits. Negative current is defined as coming out of (sourcing) the output. † Complete part number includes additional characters to indicate operating temperature range and package style. ‡ Internal transient-suppression diodes included for inductive-load protection.