5811

5811 ALLEGRO

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Technical content

BiMOS II 12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS Designed primarily for use with vacuum-fluorescent displays, the UCN5811A smart power BiMOS II driver features low-output saturation voltages and high output switching speed. These devices contain CMOS shift registers, data latches, and control circuitry, and bipolar high-speed sourcing outputs with DMOS active pull-down circuitry. The high-speed shift register and data latches allow direct interface with microprocessor-based systems. A CMOS serial data output enables cascade connections in applications requir- ing additional drive lines. The UCN5811A features 60 V and -40 mA output ratings, allowing it to be used in many other peripheral power driver applications. It can be used as an improved replacement tor the SN75512B. The Allegro devices do not require special power-up sequencing. The UCN5811A has been designed with BiMOS II logic for improved data entry rates. With a 5 V supply, it will operate to at least 3.3 MHz. At 12 V, higher speeds are possible. Use of this device with TTL may require the use of appropriate pull-up resistors to ensure a proper input logic high. This device is supplied in a 20-pin plastic dual in-line package. It can be operated over the ambient temperature range of -20 °C to +85°C. Copper lead frames and low output saturation voltages allow all outputs to be operated at 25 mA continuously at ambient temperatures of up to 76 °C.

FEATURES

I To 3.3 MHz Data Input Rate I Low-Power CMOS Logic and Latches I High-Speed Source Drivers I Active Pull-Downs I Low-Output Saturation Voltages I Improved Replacement for SN75512B Always order by complete part number: UCN5811A . Data Sheet26182.20B ABSOLUTE MAXIMUM RATINGS at TA = 25°C Continuous Output Current, Input Voltage Range, Package Power Dissipation, Operating Temperature Range, Storage Temperature Range, SERIAL DATA OUT SERIAL DATA IN BLANKING LOGIC SUPPLY STROBE CLOCK OUT1 OUT2 OUT11 OUT 12 LOAD SUPPLYBBV VDD ST GROUND CLK BLNK OUT9 OUT10 OUT3 Dwg. PP-029-5 OUT8 OUT7 OUT6 OUT5 OUT4 REGISTER LATCHES 581 1

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000 5811 BiMOS II 12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS TYPICAL OUTPUT DRIVER FUNCTIONAL BLOCK DIAGRAM Dwg. W-182 TIMING WAVESHAPES Dwg. W-184 TYPICAL INPUT CIRCUIT Dwg. EP-010-5 IN VDD 50 75 100 125 150 2.5 0.5 ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS 2.0 1.5 1.0 AMBIENT TEMPERATURE IN °C Dwg. GS-004-1 R = 55 °C/W θJA MOS BIPOLAR OUT 1 OUT 2GROUND Dwg. FP-013-1OUT 3 OUT N CLOCK SERIAL DATA IN STROBE BLANKING SERIAL DATA OUTSERIAL-PARALLEL SHIFT REGISTER LATCHES VDD VBB LOGIC SUPPLY LOAD SUPPLY Copyright © 1985, 2000 Allegro MicroSystems, Inc.

SERIAL-INPUT, LATCHED SOURCE DRIVERS www.allegromicro.com ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 60 V (unless otherwise noted). Limits @ VDD = 5 V Limits @ V DD = 12 V Output Leakage Current I CEX VOUT = 0 V, TA = +70°C — -5.0 -15 — -5.0 -15 µA Output Voltage V OUT(H) IOUT = -25 mA, VBB = 60 V 58 58.5 — 58 58.5 — V VOUT(L) IOUT = 1 mA — 2.0 3.0 — — — V IOUT = 2 mA — — — — 2.0 3.0 V Output Pull-Down Current I OUT(L) VOUT = 10 V to VBB 2.5 4.0 — — — — mA VOUT = 40 V to VBB — — — 15 18 — mA Input Voltage V IN(1) 3.5 — 5.3 10.5 — 12.3 V Input Current I IN(1) VIN = VDD — 0.05 0.5 — 0.1 1.0 µA Serial Data Output Voltage V OUT(H) IOUT = -200 µA 4.5 4.7 — 11.7 11.8 — V VOUT(L) IOUT = 200 µA — 200 250 — 100 200 mV Maximum Clock Frequency f clk 3.3* — — — — — MHz Supply Current I DD(H) All Outputs High — 3.0 5.0 — 15 20 mA IDD(L) All Outputs Low — 2.5 4.0 — 7.0 10 mA IBB(H) Outputs High, No Load — 7.5 12 — 7.5 12 mA IBB(L) Outputs Low — 10 100 — 10 100 µA Blanking to Output Delay t PHL CL = 30 pF — 300 550 — 125 150 ns tPLH CL = 30 pF — 250 450 — 170 200 ns Output Fall Time t f CL = 30 pF — 1000 1250 — 250 300 ns Output Rise Time t r CL = 30 pF — 150 170 — 150 170 ns Negative current is defined as coming out of (sourcing) the specified device pin. * Operation at a clock frequency greater than the specified minimum value is possible but not warranteed.

Worcester, Massachusetts 01615-0036 (508) 853-5000 5811 BiMOS II 12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS Serial Data present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUT- PUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is trans- ferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the BLANKING input be high during serial data entry. When the BLANKING input is high, the output source drivers are disabled (OFF); the DMOS sink drivers are ON, the information stored in the latches is not affected by the BLANKING input. With the BLANKING input low, the outputs are controlled by the state of their respective latches. E F CLOCK DATA IN STROBE BLANKING OUTN A D B C G Dwg. No. 12,649A TIMING REQUIREMENTS (TA = +25°C,VDD = 5 V, Logic Levels are VDD and Ground) A. Minimum Data Active Time Before Clock Pulse B. Minimum Data Active Time After Clock Pulse G. Typical Time Between Strobe Activation and Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable with increased supply voltage; operation at high temperatures will reduce the specified maximum clock frequency. TRUTH TABLE Serial Shift Register Contents Serial Latch Contents Output Contents Data Clock Data Strobe Input Input I HH R 1 R2 ... R N-2 RN-1 RN-1 LL R 1 R2 ... R N-2 RN-1 RN-1 XR 1 R2 R3 ... R N-1 RN RN L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State

SERIAL-INPUT, LATCHED SOURCE DRIVERS www.allegromicro.com 0.014 0.008 0.300 BSC Dwg. MA-001-20 in 0.430 MAX 1 10 0.280 0.240 0.210 MAX 0.070 0.045 0.015 MIN 0.022 0.014 0.100 BSC 0.005 MIN 0.150 0.115 1.060 0.980 UCN5811A Dimensions in Inches (controlling dimensions) NOTES: 1. Exact body and lead configuration at vendor ’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. 4. Supplied in standard sticks/tubes of 18 devices.

Worcester, Massachusetts 01615-0036 (508) 853-5000 5811 BiMOS II 12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS 0.355 0.204 7.62 BSC Dwg. MA-001-20 mm 10.92 MAX 1 10 7.11 6.10 5.33 MAX 1.77 1.15 0.39 MIN 0.558 0.356 2.54 BSC 0.13 MIN 3.81 2.93 26.92 24.89 UCN5811A Dimensions in Millimeters (for reference only) NOTES: 1. Exact body and lead configuration at vendor ’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. 4. Supplied in standard sticks/tubes of 18 devices.

SERIAL-INPUT, LATCHED SOURCE DRIVERS www.allegromicro.com The products described here are manufactured under one or more Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsi- bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.

Worcester, Massachusetts 01615-0036 (508) 853-5000 5811 BiMOS II 12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS POWER INTERFACE DRIVERS Function Output Ratings* Part Number † SERIAL-INPUT LATCHED DRIVERS 8-Bit (saturated drivers) -120 mA 50 V‡ 5895 8-Bit 350 mA 50 V 5821 8-Bit 350 mA 80 V 5822 8-Bit 350 mA 50 V‡ 5841 8-Bit 350 mA 80 V‡ 5842 8-Bit (constant-current LED driver) 75 mA 17 V 6275 8-Bit (DMOS drivers) 250 mA 50 V 6595 8-Bit (DMOS drivers) 350 mA 50 V‡ 6A595 8-Bit (DMOS drivers) 100 mA 50 V 6B595 10-Bit (active pull-downs) -25 mA 60 V 5810-F and 6809/10 12-Bit (active pull-downs) -25 mA 60 V 5811 and 6811 16-Bit (constant-current LED driver) 75 mA 17 V 6276 20-Bit (active pull-downs) -25 mA 60 V 5812-F and 6812 32-Bit (active pull-downs) -25 mA 60 V 5818-F and 6818 32-Bit 100 mA 30 V 5833 32-Bit (saturated drivers) 100 mA 40 V 5832 PARALLEL-INPUT LATCHED DRIVERS 4-Bit 350 mA 50 V‡ 5800 8-Bit -25 mA 60 V 5815 8-Bit 350 mA 50 V‡ 5801 8-Bit (DMOS drivers) 100 mA 50 V 6B273 8-Bit (DMOS drivers) 250 mA 50 V 6273 SPECIAL-PURPOSE DEVICES Unipolar Stepper Motor Translator/Driver 1.25 A 50 V‡ 5804 Addressable 8-Bit Decoder/DMOS Driver 250 mA 50 V 6259 Addressable 8-Bit Decoder/DMOS Driver 350 mA 50 V‡ 6A259 Addressable 8-Bit Decoder/DMOS Driver 100 mA 50 V 6B259 Addressable 28-Line Decoder/Driver 450 mA 30 V 6817 * Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits. Negative current is defined as coming out of (sourcing) the output. † Complete part number includes additional characters to indicate operating temperature range and package style. ‡ Internal transient-suppression diodes included for inductive-load protection.