5810-F

5810-F ALLEGRO

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BiMOS II 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS Always order by complete part number, e.g., UCN5810AF . The UCN5810AF, UCN5810EPF, and UCN5810LWF combine a 10-bit CMOS shift register and accompanying data latches, control circuitry, bipolar sourcing outputs with DMOS active pull-downs. Designed primarily to drive vacuum-fluorescent displays, the 60 V and -40 mA output ratings also allow these devices to be used in many other peripheral power driver applications. The UCN5810AF/EPF/LWF feature reduced supply requirements (active DMOS pull-downs) and lower saturation voltages when compared with the original UCN5810A. The CMOS shift register and latches allow direct interfacing with microprocessor-based systems. With a 5 V supply, they will operate to at least 3.3 MHz. At 12 V, higher speeds are possible. Use with TTL may require appropriate pull-up resistors to ensure an input logic high. A CMOS serial data output enables cascade connections in applications requiring additional drive lines. Similar devices are available as the UCN5811A (12 bits), UCN5812AF/EPF (20 bits), and UCN5818AF/EPF (32 bits). The UCN5810AF/EPF/LWF output source drivers are NPN Darlingtons capable of sourcing up to 40 mA. The DMOS active pull-downs are capable of sinking up to 15 mA. For inter-digit blanking, all of the output drivers can be disabled and the DMOS sink drivers turned on by the BLANKING input high. The UCN5810AF is furnished in an 18-pin dual in-line plastic package. The UCN5810EPF is furnished in a 20-lead plastic chip carrier. The UCN5810LWF is furnished in a wide-body, small-outline plastic package (SOIC) with gull-wing leads. Copper lead frames, reduced supply current requirements, and lower output saturation voltages allow all devices to source 25 mA from all outputs continuously, over the entire operating temperature range. All devices are also available for operation between -40 °C and +85°C. To order, change the prefix from ‘UCN’ to ‘UCQ’.

FEATURES

I High-Speed Source Drivers I 60 V Minimum Output Breakdown I Improved Replacements for TL4810B UCN5810AF Data Sheet26182.24C 91 0 SERIAL DATA OUT LOAD SUPPLY SERIAL DATA IN BLANKINGLOGIC SUPPLY STROBE GROUND CLOCK CLK V ST BLNK DD BBV OUT 9 OUT 10 OUT1 OUT 2 OUT 3 Dwg. PP-029 OUT8 OUT7 OUT6 OUT 5 OUT4 LATCHES REGISTER REGISTER LATCHES ABSOLUTE MAXIMUM RATINGS at TA = 25°C Continuous Output Current Range, Input Voltage Range, Package Power Dissipation, P D Operating Temperature Range, Storage Temperature Range, *Derate linearly to 0 W at +150 °C. Caution: CMOS devices have input static protection but are susceptible to damage when exposed to extremely high static electrical charges. Note that the UCN5810AF (dual in-line package) and UCN5810LWF (small-outline IC package) are electrically identical and share a common pin number assignment. I Low Output Saturation Voltages I Low-Power CMOS Logic and Latches I To 3.3 MHz Data Input Rate I Active DMOS Pull-Downs 5810 -F

10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000 FUNCTIONAL BLOCK DIAGRAM UCN5810EPF TYPICAL INPUT CIRCUIT TYPICAL OUTPUT DRIVER Dwg. No. A-14,219 50 75 100 125 150 2.5 0.5 ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS AMBIENT TEMPERATURE IN °C 2.0 1.5 1.0 SUFFIX 'A', R = 60°C/WθJA SUFFIX 'EP', R = 59°C/WθJA Dwg. GP-024B SUFFIX 'LW', R = 80°C/WθJA Dwg. GP-024A SERIAL DATA OUT LOAD SUPPLY SERIAL DATA IN BLANKING OUT OUT10 OUT 1 OUT 2 OUT3 Dwg. PP-029-1 LOGIC SUPPLY STROBE GROUND CLOCK CLK V ST BLNKDD BBV OUT8 OUT 7 OUT6 OUT 5 OUT4 LATCHES REGISTER REGISTER LATCHES UCN5810LWF 13 19 STROBE V DD Dwg. PP-059 OUT1 OUT10 OUT5 OUT6 LATCHES REGISTER REGISTER LATCHES V BB CLOCK NC GROUND LOGIC SUPPLY SERIAL DATA OUT LOAD SUPPLY NC SERIAL DATA IN BLANKINGST CLK BLNK Dwg. PP-029-1 V OUT BB N MOS BIPOLAR OUT 1 OUT 2GROUND Dwg. FP-013-1OUT 3 OUT N CLOCK SERIAL DATA IN STROBE BLANKING SERIAL DATA OUTSERIAL-PARALLEL SHIFT REGISTER LATCHES VDD VBB LOGIC SUPPLY LOAD SUPPLY Dwg. EP-010-4A IN VDD Copyright © 1988, 2000 Allegro MicroSystems, Inc.

10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS www.allegromicro.com Limits @ VDD = 5 V Limits @ V DD = 12 V Output Leakage Current I CEX VOUT = 0 V, TA = +70°C — -5.0 -15 — -5.0 -15 µA Output Voltage V OUT(1) IOUT = -25 mA 58 58.5 — 58 58.5 — V VOUT(0) IOUT = 1 mA — 1.0 1.5 — — — V IOUT = 2 mA — — — — 1.0 1.5 V Output Pull-Down Current I OUT(0) VOUT = 5 V to VBB 2.0 3.5 — — — — mA VOUT = 20 V to VBB ——— 8 . 0 1 3— m A Input Voltage V IN(1) 3.5 — 5.3 10.5 — 12.3 V Input Current I IN(1) VIN = VDD — — 100 — — 240 µA Serial Data Output Voltage V OUT(1) IOUT = -200 µA 4.5 4.7 — 11.7 11.8 — V VOUT(0) IOUT = 200 µA — 200 250 — 100 200 mV Maximum Clock Frequency f clk 3.3* — — — — — MHz Supply Current I DD(1) All Outputs High — 100 300 — 200 500 µA IDD(0) All Outputs Low — 100 300 — 200 500 µA IBB(1) Outputs High, No Load — 0.7 2.0 — 0.7 2.0 mA IBB(0) Outputs Low — 10 100 — 10 100 µA Blanking to Output Delay t PHL CL = 30 pF, 50% to 50% — 2000 — — 1000 — ns tPLH CL = 30 pF, 50% to 50% — 1000 — — 850 — ns Output Fall Time t f CL = 30 pF, 90% to 10% — 1450 — — 650 — ns Output Rise Time t r CL = 30 pF, 10% to 90% — 650 — — 700 — ns Negative current is defined as coming out of (sourcing) the specified device pin. * Operation at a clock frequency greater than the specified minimum value is possible but not warranteed. ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 60 V unless otherwise noted.

10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS Worcester, Massachusetts 01615-0036 (508) 853-5000 TRUTH TABLE Serial Shift Register Contents Serial Latch Contents Output Contents Data Clock Data Strobe Input Input I HH R 1 R2 ... R N-2 RN-1 RN-1 LL R 1 R2 ... R N-2 RN-1 RN-1 XR 1 R2 R3 ... R N-1 RN RN L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State Serial Data present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUT- PUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is trans- ferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the BLANKING input be high during serial data entry. When the BLANKING input is high, the output source drivers are disabled (OFF); the DMOS sink drivers are ON. The information stored in the latches is not affected by the BLANKING input. With the BLANKING input low, the outputs are controlled by the state of their respective latches. TIMING REQUIREMENTS (TA = +25°C,VDD = 5 V, Logic Levels are VDD and Ground) A. Minimum Data Active Time Before Clock Pulse B. Minimum Data Active Time After Clock Pulse G. Typical Time Between Strobe Activation and Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable with increased supply voltage; operation at high temperatures will reduce the specified maximum clock frequency. E F CLOCK DATA IN STROBE BLANKING OUTN A D B C G Dwg. No. A-12,649A

10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS www.allegromicro.com UCN5810AF Dimensions in Inches (controlling dimensions) Dimensions in Millimeters (for reference only) NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. 4. Supplied in standard sticks/tubes of 21 devices. 0.014 0.008 0.300 BSC Dwg. MA-001-18A in 0.430 MAX 1 9 0.280 0.240 0.210 MAX 0.070 0.045 0.015 MIN 0.022 0.014 0.100 BSC 0.005 MIN 0.150 0.115 0.920 0.880 0.355 0.204 7.62 BSC Dwg. MA-001-18A mm 10.92 MAX 1 9 7.11 6.10 5.33 MAX 1.77 1.15 0.39 MIN 0.558 0.356 2.54 BSC 0.13 MIN 3.81 2.93 23.37 22.35

10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS Worcester, Massachusetts 01615-0036 (508) 853-5000 UCN5810EPF Dimensions in Inches (controlling dimensions) Dimensions in Millimeters (for reference only) 913 0.020 MIN 0.180 0.165 0.050 BSC 120 2 Dwg. MA-005-20A in 0.395 0.385 0.356 0.350 0.032 0.026 0.021 0.013 814 0.356 0.350 0.395 0.385 INDEX AREA 0.169 0.141 0.169 0.141 913 0.51 MIN 4.57 4.20 1.27 BSC 120 2 Dwg. MA-005-20A mm 10.03 9.78 9.042 8.890 0.812 0.661 0.533 0.331 814 9.042 8.890 10.03 9.78 INDEX AREA 4.29 3.58 4.29 3.58 NOTES: 1. Exact body and lead configuration at vendor ’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Supplied in standard sticks/tubes of 48 devices or add “TR” to part number for tape and reel.

10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS www.allegromicro.com UCN5810LWF Dimensions in Inches (for reference only) Dimensions in Millimeters (controlling dimensions) NOTES: 1. Exact body and lead configuration at vendor ’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Supplied in standard sticks/tubes of 41 devices or add “TR” to part number for tape and reel. 0° TO 8° 1 2 30.020 0.013 0.0040 MIN. 0.0125 0.0091 0.050 0.016 Dwg. MA-008-18A in 0.050 BSC 18 10 0.419 0.394 0.2992 0.2914 0.4625 0.44690.0926 0.1043 0° TO 8° 2 30.51 0.33 0.10 MIN. 0.32 0.23 1.27 0.40 Dwg. MA-008-18A mm 1.27 BSC 7.60 7.40 10.65 10.00 11.75 11.352.65 2.35

10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS Worcester, Massachusetts 01615-0036 (508) 853-5000 The products described here are manufactured under one or more Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsi- bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.