5800

5800 ALLEGRO

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Technical content

5800 AND 5801

Always order by complete part number, e.g.,UCN5801EP . The UCN5800A/L and UCN5801A/EP/LW latched-input BiMOS ICs merge high-current, high-voltage outputs with CMOS logic. The CMOS input section consists of 4 or 8 data (‘D’ type) latches with associated common CLEAR, STROBE, and OUTPUT ENABLE circuitry. The power outputs are bipolar npn Darlingtons. This merged technology provides versatile, flexible interface. These BiMOS power interface ICs greatly benefit the simplification of computer or micropro- cessor I/O. The UCN5800A and UCN5800L each contain four latched drivers; the UCN5801A, UCN5801EP, and UCN5801LW contain eight latched drivers. The UCN5800A/L and UCN5801A/EP/LW supersede the original BiMOS latched-input driver ICs (UCN4400A and UCN4801A). These second-generation devices are capable of much higher data input rates and will typically operate at better than 5 MHz with a 5 V logic supply. Circuit operation at 12 V affords substantial improvement over the 5 MHz figure. The CMOS inputs are compatible with standard CMOS and NMOS circuits. TTL circuits may mandate the addition of input pull-up resis- tors. The bipolar Darlington outputs are suitable for directly driving many peripheral/power loads: relays, lamps, solenoids, small dc motors, etc. All devices have open-collector outputs and integral diodes for inductive load transient suppression. The output transistors are capable of sinking 500 mA and will withstand at least 50 V in the OFF state. Because of limitations on package power dissipation, the simul- taneous operation of all drivers at maximum rated current can only be accomplished by a reduction in duty cycle. Outputs may be paralleled for higher load current capability. The UCN5800A is furnished in a standard 14-pin DIP; the UCN5800L and UCN5801LW in surface-mountable SOICs; the UCN5801A in a 22-pin DIP with 0.400" (10.16 mm) row centers; the UCN5801EP in a 28-lead PLCC.

FEATURES

n To 4.4 MHz Data Input Rate n High-Voltage, High-Current Outputs n CMOS, NMOS, TTL Compatible Inputs n Output Transient Protection n Internal Pull-Down Resistors n Low-Power CMOS Latches n Automotive Capable SUPPLY GROUND CLEAR OUT 1 OUT 2 OUT 3 Dwg. PP-014A OUT 4 141 COMMON OUTPUT ENABLE IN1 STROBE IN2 IN3 IN4 VDD LATCHES Data Sheet 26180.10B ABSOLUTE MAXIMUM RATINGS at +25°C Free-Air Temperature Input Voltage Range, Continuous Collector Current, Package Power Dissipation, Operating Temperature Range, Storage Temperature Range, Caution: CMOS devices have input static protection but are susceptible to damage when exposed to extremely high static electrical charges. Note the UCN5800A (DIP) and the UCN5800L (SOIC) are electrically identical and share a common terminal number assignment.

5800 AND

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000 FUNCTIONAL BLOCK DIAGRAM Copyright © 1985, 1997, Allegro MicroSystems, Inc. 50 75 100 125 150 2.5 0.5 ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS AMBIENT TEMPERATURE IN °C 2.0 1.5 1.0 Dwg. GP-023-1 22-PIN DIP, R = 50°C/WqJA 28-LEAD PLCC, R = 55°C/WqJA 14-PIN DIP, R = 60°C/WqJA 14-LEAD SOIC, R = 95°C/WqJA 24-LEAD SOIC, R = 68°C/WqJA COMMON GROUND STROBE OUTPUT ENABLE INN COMMON MOS CONTROL TYPICAL MOS LATCH TYPICAL BIPOLAR DRIVE OUT N Dwg. FP-016-1 CLEAR SUPPLY VDD TYPICAL INPUT CIRCUIT Dwg. EP-010-4A IN VDD

ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V (unless otherwise noted). Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units Output Leakage Current I CEX VCE = 50 V, TA = +25°C— — 5 0 µA VCE = 50 V, TA = +70°C — — 100 µA Collector-Emitter V CE(SAT) IC = 100 mA — 0.9 1.1 V IC = 200 mA — 1.1 1.3 V IC = 350 mA, VDD = 7.0 V — 1.3 1.6 V Input Voltage V IN(0) — — 1.0 V VIN(1) VDD = 12 V 10.5 — — V VDD = 10 V 8.5 — — V VDD = 5.0 V (See Note) 3.5 — — V Input Resistance r IN VDD = 12 V 50 200 — k Ω VDD = 10 V 50 300 — k Ω VDD = 5.0 V 50 600 — k Ω Supply Current I DD(ON) VDD = 12 V, Outputs Open — 1.0 2.0 mA VDD = 10 V, Outputs Open — 0.9 1.7 mA VDD = 5.0 V, Outputs Open — 0.7 1.0 mA IDD(OFF) VDD = 12 V, Outputs Open, Inputs = 0 V — — 200 µA VDD = 5.0 V, Outputs Open, Inputs = 0 V — 50 100 µA Clamp Diode I R VR = 50 V, TA = +25°C— — 5 0 µA VR = 50 V, TA = +70°C — — 100 µA Clamp Diode Forward Voltage V F IF = 350 mA — 1.7 2.0 V NOTE: Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to ensure a minimum logic “1”. Saturation Voltage Leakage Current (Each Stage) (Total) GROUND OUTPUT ENABLE STROBE K ST V DD OE Dwg. PP-037 LATCHES NC NC NC NC NC NC SUPPLY CLAMP DIODE COMMON C CLEAR OUT 1 IN8 OUT 8 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 IN1 IN2 IN3 IN4 IN5 IN6 IN7 UCN5801EP (additional pinout diagrams are on next page)

Worcester, Massachusetts 01615-0036 (508) 853-5000 TRUTH TABLE OUTN INN STROBE CLEAR ENABLE t-1 t 0 100 X O F F 1 100 X O N X X1X X O F F X X X 1 X OFF X 0 0 0 ON ON X 0 0 0 OFF OFF X = irrelevant. t-1 = previous output state. t = present output state. OUTPUT CLEAR STROBE OUTPUT ENABLE INN OUT N A C BC B G D E F A C B G E TIMING CONDITIONS (Logic Levels are VDD and Ground) A.Minimum Data Active Time Before Strobe Enabled B.Minimum Data Active Time After Strobe Disabled D.Typical Time Between Strobe Activation and E.Minimum Time Between Strobe Activation and Information present at an input is transferred to its latch when the STROBE is high. A high CLEAR input will set all latches to the output OFF condition regardless of the data or STROBE input levels. A high OUTPUT ENABLE will set all outputs to the OFF condition, regardless of any other input conditions. When the OUTPUT ENABLE is low, the outputs depend on the state of their respective latches. Dwg. No. A-10,895A UCN5801A 22 1 SUPPLY CLEAR 1 OUTPUT ENABLE STROBE VDD 7 16 OUT 1 OUT 2 OUT 3 OUT 4 IN1 IN2 IN3 IN4 11 12 GROUND OUT 5 OUT 6 OUT 7 Dwg. PP-015 OUT 8 COMMON IN5 IN6 IN7 IN8 LATCHES 22 3 SUPPLY CLEAR 1 OUTPUT ENABLE STROBE VDD

22 OUT 1

Dwg. PP-015-1 OUT 8 COMMON IN5 IN6 IN7 IN8 LATCHES NO CONNECTION NO CONNECTIONNCNC12 13 UCN5801LW

UNIPOLAR STEPPER-MOTOR DRIVE Dwg. No. B-1537 7 8 OUT 2 OUT 3 OUT 4 OUT 1 +30 V IN 1 IN 2 IN 3 IN 4 STROBE CLEAR OUTPUT ENABLE (ACTIVE LOW) LATCHES UCN-5800A VDD VDD +30 V µρ STROBE IN 1 IN 2 IN 3 IN 4 OUT 1 OUT 2 OUT 3 OUT 4 Dwg. GP-060 STROBE IN 1 IN 2 IN 3 IN 4 OUT 1 OUT 2 OUT 3 OUT 4 Dwg. GP-060-1 UNIPOLAR WAVE DRIVE UNIPOLAR 2-PHASE DRIVE

Worcester, Massachusetts 01615-0036 (508) 853-5000 UCN5800A Dimensions in Inches (controlling dimensions) Dimensions in Millimeters (for reference only) NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. 0.014 0.008 0.300 BSC Dwg. MA-001-14A in 0.430 MAX 0.100 BSC 1 7 0.280 0.240 0.210 MAX 0.070 0.045 0.015 MIN 0.022 0.014 0.005 MIN 0.150 0.115 0.775 0.735 0.355 0.204 7.62 BSC Dwg. MA-001-14A mm 10.92 MAX 1 7 7.11 6.10 5.33 MAX 1.77 1.15 0.39 MIN 0.558 0.356 2.54 BSC 0.13 MIN 3.81 2.93 19.68 18.67

NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 0° TO 8°0.3444 0.3367 0.2440 0.2284 0.050 0.016 Dwg. MA-007-14 in 0.050 BSC 0.0098 0.0075 0.1574 0.1497 0.020 0.013 0.0688 0.0532 0.0040 MIN. 14 8 8.75 8.55 6.20 5.80 1.27 0.40 0° TO 8° Dwg. MA-007-14A mm 1.27 BSC 0.25 0.19 1 2 3 4.00 3.80 0.51 0.33 1.75 1.35 0.10 MIN. 14 8 UCN5800L Dimensions in Inches (for reference only) Dimensions in Millimeters (controlling dimensions)

Worcester, Massachusetts 01615-0036 (508) 853-5000 UCN5801A Dimensions in Inches (controlling dimensions) Dimensions in Millimeters (for reference only) NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. 12 3 11 9.65 8.39 5.33 MAX 0.070 0.030 28.44 26.67 0.39 MIN 0.558 0.356 2.54 BSC 0.13 MIN 4.06 2.93 0.381 0.204 10.16 BSC Dwg. MA-002-22 mm 12.70 MAX 12 3 11 0.380 0.330 0.210 MAX 0.070 0.030 0.015 MIN 0.022 0.014 0.100 BSC 0.005 MIN 0.160 0.115 0.015 0.008 0.400 BSC Dwg. MA-002-22 in 0.500 MAX 1.120 1.050

(controlling dimensions) Dimensions in Millimeters (for reference only) NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 18 12 0.020 MIN 0.050 BSC 128 INDEX AREA Dwg. MA-005-28A in 0.026 0.032 0.013 0.021 19 11 0.165 0.180 0.495 0.485 0.456 0.450 0.495 0.485 0.456 0.450 0.219 0.191 0.219 0.191 0.51 MIN 4.57 4.20 1.27 BSC 12.57 12.32 11.582 11.430 128 INDEX AREA Dwg. MA-005-28A mm 0.812 0.661 0.331 0.533 12.57 12.32 18 12 11.58 11.43 5.56 4.85 5.56 4.85

Worcester, Massachusetts 01615-0036 (508) 853-5000 UCN5801LW Dimensions in Inches (for reference only) Dimensions in Millimeters (controlling dimensions) NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 0° TO 8° 1 2 30.020 0.013 0.0040 MIN. 0.0125 0.0091 0.050 0.016 Dwg. MA-008-24A in 0.050 BSC 24 13 0.2992 0.2914 0.419 0.394 0.6141 0.59850.0926 0.1043 0° TO 8° 2 30.51 0.33 0.10 MIN. 0.32 0.23 1.27 0.40 Dwg. MA-008-24A mm 1.27 BSC 7.60 7.40 10.65 10.00 15.60 15.202.65 2.35

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Worcester, Massachusetts 01615-0036 (508) 853-5000 BiMOS II (Series 5800) & DABiC IV (Series 6800) INTELLIGENT POWER INTERFACE DRIVERS SELECTION GUIDE Function Output Ratings * Part Number SERIAL-INPUT LATCHED DRIVERS 8-Bit (saturated drivers) -120 mA 50 Và 5895 8-Bit 350 mA 50 V 5821 8-Bit 350 mA 80 V 5822 8-Bit 350 mA 50 Và 5841 8-Bit 350 mA 80 Và 5842 9-Bit 1.6 A 50 V 5829 10-Bit (active pull-downs) -25 mA 60 V 5810-F and 6809/10 12-Bit (active pull-downs) -25 mA 60 V 5811 and 6811 20-Bit (active pull-downs) -25 mA 60 V 5812-F and 6812 32-Bit (active pull-downs) -25 mA 60 V 5818-F and 6818 32-Bit 100 mA 30 V 5833 32-Bit (saturated drivers) 100 mA 40 V 5832 PARALLEL-INPUT LATCHED DRIVERS 4-Bit 350 mA 50 Và 5800 8-Bit -25 mA 60 V 5815 8-Bit 350 mA 50 Và 5801 SPECIAL-PURPOSE FUNCTIONS Unipolar Stepper Motor Translator/Driver 1.25 A 50 Và 5804 Addressable 28-Line Decoder/Driver 450 mA 30 V 6817 * Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits. Negative current is defined as coming out of (sourcing) the output. † Complete part number includes additional characters to indicate operating temperature range and package style. ‡ Internal transient-suppression diodes included for inductive-load protection. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the design of its products. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.