56800E

56852 NXP

Document overview

• Manufacturer or author: Provided By www.digicamel.com(free datasheet download site)
• PDF pages: 48

Technical content

16-bit Digital Signal Controllers freescale.com 56852 Data Sheet Technical Data DSP56852 Rev. 8

56852 Technical Data, Rev. 8 Freescale Semiconductor 3

56852 Block Diagram

16 x 16 + 36 → 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators Address Generation Unit Bit Manipulation Unit PLL Clock Generator 16-Bit 56800E Core XTAL EXTAL Interrupt Controller COP/ Watch- dog

1 Quad

or A17, A18

2 CLKO

muxed (A20) External Bus Interface Unit RESETIRQA IRQB VDD VSSIO VDDA VSSA WR Enable RD Enable CS[2:0] muxed (GPIOA) A0-16 MODE D0-D12[12:0] Program Memory 6144 x 16 SRAM Boot ROM 1024 x 16 ROM Data Memory 4096 x 16 SRAM PDB PDB XAB1 XAB2 XDB2 CDBR SSI or SPI or GPIOC SCI or GPIOE IPBus Bridge (IPBB) muxed (D13-15) 3 6 A17-18 muxed (timer pins) A19 muxed (CS3) D13-15 muxed (Mode A,B,C) VDDIO Integration Module System P O R O S C Decoding Peripherals Peripheral Address Decoder Peripheral Device Selects System Address Decoder RW Control IPAB IPWDB IPRDB System Device System Bus Control R/W ControlMemory PAB PAB CDBW CDBR CDBW Clock resets VSS SSI or SPI or GPIOC External Data Bus Switch Bus Control External Address Bus Switch DSP56852 General Description

• 120 MIPS at 120MHz
• 6K x 16-bit Program SRAM
• 4K x 16-bit Data SRAM
• 1K x 16-bit Boot ROM
• 21 External Memory Address lines, 16 data lines and four chip selects
• One (1) Serial Port Interf ace (SPI) or one (1) Improved Synchronous Serial Interface (ISSI)
• One (1) Serial Commun ication Interface (SCI)
• Interrupt Controller
• General Purpose 16-bit Quad Timer
• JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging
• Computer Operating Properly (COP)/Watchdog Timer
• 81-pin MAPBGA package
• U p t o 1 1 G P I O

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1.1 56852 Features

1.1.1 Core

• Efficient 16-bit engine with dual Harvard architecture
• 120 Million Instructions Per Second (MIPS) at 120MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Four (4) 36-bit accumulators including extension bits
• 16-bit bidirectional shifter
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Three (3) internal address buses and one (1) external address bus
• Four (4) internal data buses and one (1) external data bus
• Instruction set supports both DSP and controller functions
• Four (4) hardware interrupt levels
• Five (5) software interrupt levels
• Controller-style addressing modes and instructions for compact code
• Efficient C Compiler and local variable support
• Software subroutine and interrupt stac k with depth limited only by memory
• JTAG/Enhanced OnCE debug programming interface

1.1.2 Memory

• Harvard architecture permits as many as three simultaneous accesses to program and data memory
• On-chip memory includes: —6 K × 16-bit Program SRAM —4 K × 16-bit Data SRAM —1 K × 16-bit Boot ROM
• 21 External Memory Address lines, 16 data lines an d four (4) programmable chip select signals

1.1.3 Peripheral Circuits for DSP56852

• General Purpose 16-bit Quad Timer with two external pins*
• One (1) Serial Communication Interface (SCI)*
• One (1) Serial Port Interface (SPI) or one (1) Improved Synchronous Serial Interface (ISSI) module*
• Interrupt Controller
• Computer Operating Properly (COP)/Watchdog Timer
• JTAG/Enhanced On-Chip Emulation (EOnCE) for unobtrusive, real-time debugging
• 81-pin MAPBGA package
• U p t o 1 1 G P I O * Each peripheral I/O can be used alternately as a General Purpose I/O if not needed

56852 Description

56852 Technical Data, Rev. 8 Freescale Semiconductor 5

1.1.4 Energy Information

• Fabricated in high-density CMOS with 3.3V , TTL-compatible digital inputs
• Wait and Stop modes available 1.2 56852 Description The 56852 is a member of the 56800E core-based family of controllers. It combines, on a single chip, the processing power of a Digital Signal Processor (DSP) and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56852 is well-suited for many applications. The 56852 includes many peripherals especially useful for low-end Internet appliance applications and low-end client applications such as telephony; portable devices; Internet audio; and point-of-sale systems such as noise suppression; ID tag readers; sonic/subsonic detectors; security access devices; remote metering; and sonic alarms. The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction se t allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly effi cient for C-Compilers, enabling rapid development of optimized control applications. The 56852 supports program execution from either internal or external memories. Two data operands can be accessed from the on-ch ip Data RAM per instruction cycle. The 56852 also provi des two external dedicated interrupt lines, and up to 11 General Purpose Input/Output (GPI O) lines, depending on peripheral configuration. The 56852 includes 6K words of Progra m RAM, 4K words of Data RAM a nd 1K of Boot RAM. It also supports program execution from external memory. This controller also provides a full set of standard programmable peri pherals that include one improved Synchronous Serial Interface (SSI) or one Serial Peripheral Interface (SPI), one Serial Communications Interface (SCI), and one Quad Timer. The SSI, SPI, SCI I/O and three chip selects can be used as General Purpose Input/Outputs when its primary function is not required. The SSI and SPI share I/O, so, at most, one of these two peripherals can be in use at any time.

1.3 State of the Art Development Environment

• Processor Expert TM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system.
• The Code Warrior Integrated Development Environm ent is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development.

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1.4 Product Documentation

The four documents listed in Table 1-1 are required for a complete description of and proper design with the 56852. Documentation is availabl e from local Freescale distribu tors, Freescale se miconductor sales offices, Freescale Literature Distribution Centers, or online at www.freescale.com.

1.5 Data Sheet Conventions

This data sheet uses the following conventions: Table 1-1 DSP56852 Chip Documentation Topic Description Order Number DSP56800E Reference Manual Detailed description of the 56800E architecture, 16-bit controller core processor and the instruction set DSP56800ERM DSP56852 User’s Manual Detailed description of memory, peripherals, and interfaces of the 56852 DSP56852UM DSP56852 Technical Data Sheet Electrical and timing specifications, pin descriptions, and package descriptions (this document) DSP56852 DSP56852 Errata Details any chip issues that might be present DSP56852E OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low. “asserted” A high true (active high) signal is high or a low true (active low) signal is low. “deasserted” A high true (active high) signal is low or a low true (active low) signal is high. Examples: Signal/Symbol Logic State Signal State Voltage1 1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. PIN True Asserted VIL/VOL PIN False Deasserted VIH/VOH PIN True Asserted VIH/VOH PIN False Deasserted VIL/VOL

56852 Technical Data, Rev. 8 Freescale Semiconductor 7 Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the 56852 are organized into functional groups, as shown in Table 2-1 and as illustrated in Figure 2-1. In Table 3-1, each table row describes the package pin and the signal or signals present. 1. VDD = VDD CORE, VSS = VSS CORE, VDDIO= VDD IO, VSSIO = VSS IO, VDDA = VDD ANA, VSSA = VSS ANA 2. CLKOUT is muxed Address pin A20. 3. Four Address pins are multiplexed with the timer, CS3 and CLKOUT pins. 4. CS3 is multiplexed with external Address Bus pin A19. 5. Mode pins are multiplexed with External Data pins D13-D15 like A17and A18. 6. Four of these pins are multiplexed with SSI. 7. Two of these pins are multiplexed with 2 bits of the External Address Bus A17and A18. Table 2-1 Functional Group Pin Allocations Functional Group Number of Pins Power (VDD, VDDIO, or VDDA) 101 Ground (VSS, VSSIO,or VSSA) 101 Phase Lock Loop (PLL) and Clock 22 External Bus Signals 393 External Chip Select* 34 Interrupt and Program Control 35 Synchronous Serial Interface (SSI) Port* 6 Serial Communications Interface (SCI) Port* 2 Serial Peripheral Interface (SPI) Port 06 Quad Timer Module Port 07 JTAG/Enhanced On-Chip Emulation (EOnCE) 6 *Alternately, GPIO pins

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Figure 2-1 56852 Signals Identified by Functional Group 56852 Logic Power I/O Power SCI Reset JTAG/Enhanced OnCE VDD VSS VDDIO VSSIO VDDA VSSA A0–16 A17(TI/O) A18(TI/O) A19(CS3) CLKO(A20) GPIOA0(CS0) GPIOA1(CS1) GPIOA2(CS2) D0-D12 D13-D15/MODEA-C RD WRBus Control RXD(GPIOE0) TXD(GPIOE1) GPIOC0(STXD) GPIOC1(SRXD) SCLK(GPIOC2)(STCK) SS (GPIOC3)(STFS) MISO(GPIOC4)(SRCK) MOSI(GPIOC5)(SRFS) IRQA IRQB XTAL EXTAL RESET TCK TDI TDO TMS TRST DE SSI SPI Chip Select Address Bus Analog Power1 Interrupt Request Oscillator Data Bus

56852 Technical Data, Rev. 8 Freescale Semiconductor 9 Part 3 Signals and Package Information All digital inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are enabled by default. Exceptions: 1. When a pin has GPIO functionality, the pull-up may be disabled under software control. 2. Mode pins D13, D14 and D15 have no pull-up. 3. TCK has a weak pull-down circuit always active. 4. Bidirectional I/O pullups automatically disable when the output is enabled. This table is presented consistently with the Signals Identified by Functional Group figure. 1. BOLD entries in the Type column represents the state of the pin just out of reset. 2. Ouput(Z) means an output in a High-Z condition. Table 3-1. 56852 Signal and Package Information for the 81-pin MAPBGA Pin No. Signal Name Type Description E1 VDD VDD Logic Power —These pins provide power to the internal structures of the chip, and should all be attached to VDD.J5 VDD E9 VDD D1 VSS VSS Logic Power - GND—These pins provide grounding for the internal structures of the chip and should all be attached to VSS.J4 VSS F9 VSS C1 VDDIO VDDIO I/O Power —These pins provide power for all I/O and ESD structures of the chip, and should all be attached to VDDIO.H1 VDDIO J7 VDDIO G9 VDDIO B9 VDDIO A4 VDDIO B1 VSSIO VSSIO I/O Power - GND—These pins provide grounding for all I/O and ESD structures of the chip and should all be attached to VSS.G1 VSSIO J6 VSSIO J9 VSSIO C9 VSSIO A5 VSSIO B5 VDDA VDDA Analog Power—These pins supply an analog power source B6 VSSA VSSA Analog Ground—This pin supplies an analog ground.

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E4 A0 Output(Z) Address Bus (A0–A16)— These pins specify a word address for external program or data memory addresses.F2 A1 F3 A2 F4 A3 F1 A4 G3 A5 G2 A6 J1 A7 H2 A8 H3 A9 J2 A10 H4 A11 G4 A12 J3 A13 F5 A14 H5 A15 E5 A16 F6 A17 TIO0 Output(Z) Input/Output Address Bus (A17) Timer I/O (0)—Can be programmed as either a timer input source or as a timer output flag. G5 A18 TIO1 Output(Z) Input/Output Address Bus (A18) Timer I/O (1)—Can be programmed as either a timer input source or as a timer output flag. H6 A19 CS3 Output(Z) Output Address Bus (A19) External Chip Select 3 —When enabled, a CSx signal is asserted for external memory accesses that fall within a programmable address range. J8 CLKO A20 Output Output Output clock (CLKO)—User programmable clock out reference Address Bus— A20 D2 CS0 GPIOA0 Output Input/Output Chip Select 0 (CS0) —When enabled, a CSx signal is asserted for external memory accesses that fall within a programmable address range. Port A GPIO (0) —A general purpose IO pin. Table 3-1. 56852 Signal and Package Information for the 81-pin MAPBGA (Continued) Pin No. Signal Name Type Description

56852 Technical Data, Rev. 8 Freescale Semiconductor 11 D3 CS1 GPIOA1 Output Input/Output Chip Select 1 (CS1) —When enabled, a CSx signal is asserted for external memory accesses that fall within a programmable address range. Port A GPIO (1) —A general purpose IO pin. C3 CS2 GPIOA2 Output Input/Output Chip Select 2 (CS2)—When enabled, a CSx signal is asserted for external memory accesses that fall within a programmable address range. Port A GPIO (2) —A general purpose IO pin. G7 D0 Input/Output Data Bus (D0–D12) —specify the data for external program or data memory accesses. D0–D15 are tri-stated when the external bus is inactive. H7 D1 H8 D2 G8 D3 H9 D4 F8 D5 F7 D6 G6 D7 E8 D8 E7 D9 E6 D10 D8 D11 D7 D12 D9 D13 MODE A Input/Output Data Bus (D13–D15) — specify the data for external program or data memory accesses. D0–D15 are tri-stated when the external bus is inactive. Mode Select—During the bootstrap proces s the MODE A, MODE B, and MODE C pins select one of the eight bootstrap modes. These pins are sampled at the end of reset. Note: Any time POR and EXTERNAL resets are active, the state of MODE A, B and C pins get asynchronously transferred to the SIM Control Register [14:12] ($1FFF08) respectively. These bits determine the mode in which the part will boot up. Note: Software and COP resets do not update the SIM Control Register. C8 D14 MODE B A9 D15 MODE C E2 RD Output Bus Control– Read Enable (RD)—is asserted during external memory read cycles. When RD is asserted low, pins D0–D15 become inputs and an external device is enabled onto the data bus. When RD is deasserted high, the external data is latched inside the controller. RD can be connected directly to the OE pin of a Static RAM or ROM. Table 3-1. 56852 Signal and Package Information for the 81-pin MAPBGA (Continued) Pin No. Signal Name Type Description

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E3 WR Output Bus Control–Write Enable (WR)— is asserted during external memory write cycles. When WR is asserted low, pins D0–D15 become outputs and the controller puts data on the bus. When WR is deasserted high, the external data is latched inside the external device. When WR is asserted, it qualifies the A0–A15 pins. WR can be connected directly to the WE pin of a Static RAM. B4 RXD GPIOE0 Input Input/Output SCI Receive Data (RXD)— This input receives byte-oriented serial data and transfers it to the SCI receive shift register. Port E GPIO (0)—A general purpose I/O pin. D4 TXD GPIOE1 Output(Z) Input/Output SCI Transmit Data (TXD)— This signal transmits data from the SCI transmit data register. Port E GPIO (1)—A general purpose I/O pin. B2 GPIOC0 STXD Input/Output Output Port C GPIO (0)—This pin is a General Purpose I/O (GPIO) pin when the SSI is not in use. SSI Transmit Data (STXD)— This output pin transmits serial data from the SSI Transmitter Shift Register. A2 GPIOC1 SRXD Input/Output Input Port C GPIO (1)—This pin is a General Purpose I/O (GPIO) pin when the SSI is not in use. SSI Receive Data (SRXD)— This input pin receives serial data and transfers the data to the SSI Receive Shift Register. A3 SCLK GPIOC2 STCK Input/Output Input/Output Input/Output SPI Serial Clock (SCLK)—In Master mode, this pin serves as an output, clocking slaved listeners. In Slave mode, this pin serves as the data clock input. Port C GPIO (2)—This pin is a General Pur pose I/O (GPIO) pin that can individually be programmed as input or output pin. SSI Serial Transfer Clock (STCK)— This bidirectional pin provides the serial bit rate clock for the transmit section of the SSI. The clock signal can be continuous or gated. B3 SS GPIOC3 STFS Input Input/Output Input/Output SPI Slave Select (SS)—In Master mode, this pin is used to arbitrate multiple masters. In Slave mode, this pin is used to select the slave. Port C GPIO (3)—This pin is a General Pur pose I/O (GPIO) pin that can individually be programmed as input or output pin. SSI Serial Transfer Frame Sync (STFS) — This bidirectional pin is used to count the number of words in a frame while transmitting. A programmable frame rate divider and a word length divider are used for frame rate sync signal generation. Table 3-1. 56852 Signal and Package Information for the 81-pin MAPBGA (Continued) Pin No. Signal Name Type Description

56852 Technical Data, Rev. 8 Freescale Semiconductor 13 C4 MISO GPIOC4 SRCK Input/Output Input/Output Input/Output SPI Master In/Slave Out (MISO)—This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. Port C GPIO (4)—This pin is a General Pur pose I/O (GPIO) pin that can individually be programmed as input or output pin. SSI Serial Receive Clock (SRCK)— This bidirectional pin provides the serial bit rate clock for the receive section of the SSI. The clock signal can be continuous or gated. C5 MOSI GPIOC5 SRFS Input/ Output (Z) Input/Output Input/Output SPI Master Out/Slave In (MOSI)—This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge that the slave device uses to latch the data. Port C GPIO (5)—This pin is a General Pur pose I/O (GPIO) pin that can individually be programmed as input or output pin. SSI Serial Receive Frame Sync (SRFS)— This bidirectional pin is used to count the number of words in a frame while receiving. A programmable frame rate divider and a word length divider are used for frame rate sync signal generation. A1 IRQA Input External Interrupt Request A (IRQA)—The IRQA Schmitt trigger input is a synchronized external interrupt request that indicates that an external device is requesting service. It can be programmed to be level-sensitive or negative-edge- triggered. C2 IRQB Input External Interrupt Request B (IRQB)—The IRQB Schmitt trigger input is an external interrupt request that indicates that an external device is requesting service. It can be programmed to be level-sensitive or negative-edge-triggered. A6 EXTAL Input External Crystal Oscillator Input (EXTAL)—This input should be connected to an external crystal. If an external clock source other than a crystal oscillator is used, EXTAL must be tied off. A7 XTAL Input/Output Crystal Oscillator Output (XTAL)—This output connects the internal crystal oscillator output to an external crystal. If an external clock source other than a crystal oscillator is used, XTAL must be used as the input. Table 3-1. 56852 Signal and Package Information for the 81-pin MAPBGA (Continued) Pin No. Signal Name Type Description

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D5 RESET Input Reset (RESET)—This input is a direct hardware reset on the processor. When RESET is asserted low, the controller is initialized and placed in the Reset state. A Schmitt trigger input is used for noise immunity. When the RESET pin is deasserted, the initial Chip Operating mode is latched from the D[15:13] pins. The internal reset signal will be deasserted synchronous with the internal clocks, after a fixed number of internal clocks. To ensure complete hardware reset, RESET and TRST should be asserted together. The only exception occurs in a debugging environment when a hardware reset is required and it is necessary not to reset the JTAG/Enhanced OnCE module. In this case, assert RESET, but do not assert TRST. C6 TCK Input Test Clock Input (TCK)—This input pin provides a gated clock to synchronize the test logic and shift serial data to the JTAG/Enhanced OnCE port. The pin is connected internally to a pull-down resistor. B7 TDI Input Test Data Input (TDI)—This input pin provides a serial input data stream to the JTAG/Enhanced OnCE port. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. A8 TDO Output Test Data Output (TDO)—This tri-statable output pin provides a serial output data stream from the JTAG/Enhanced OnCE port. It is driven in the Shift-IR and Shift-DR controller states, and changes on the falling edge of TCK. C7 TMS Input Test Mode Select Input (TMS)—This input pin is used to sequence the JTAG TAP controller’s state machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. Note: Always tie the TMS pin to VDD through a 2.2K resistor. D6 TRST Input Test Reset (TRST)—As an input, a low signal on this pin provides a reset signal to the JTAG TAP controller. To ensure complete hardware reset, TRST should be asserted whenever RESET is asserted. The only exception occurs in a debugging environment, since the Enhanced OnCE/JTAG module is under the control of the debugger. In this case it is not necessary to assert TRST when asserting RESET. Outside of a debugging environment RESET should be permanently asserted by grounding the signal, thus disabling the Enhanced OnCE/JTAG module on the device. Note: For normal operation, connect TRST directly to VSS. If the design is to be used in a debugging environment, TRST may be tied to VSS through a 1K resistor. B8 DE Input/Output Debug Even (DE)— is an open-drain, bidirectional, active low signal. As an input, it is a means of entering Debug mode of operation from an external command controller. As an output, it is a means of acknowledging that the chip has entered Debug mode. Table 3-1. 56852 Signal and Package Information for the 81-pin MAPBGA (Continued) Pin No. Signal Name Type Description

56852 Technical Data, Rev. 8 Freescale Semiconductor 15 Part 4 Specifications

4.1 General Characteristics

The 56852 is fabricated in high-dens ity CMOS with 5-volt tolerant TT L-compatible digital inputs. The term “5-volt tolerant” refers to the capability of an I/O pin, bui lt on a 3.3V comp atible process technology, to withstand a voltage up to 5.5V wit hout damaging the device. Many systems have a mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V- compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ±10% during normal operation without causing damage). This 5V-tol erant capability therefore offers the power savings of 3.3V I/O levels while being able to receive 5V levels without being damaged. Absolute maximum ratings given in Table 4-1 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device. The 56852 DC/AC electrical specificat ions are preliminar y and are from desi gn simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published afte r complete characterization and device qualificati ons have been completed. CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.

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Table 4-1 Absolute Maximum Ratings Characteristic Symbol Min Max Unit Supply voltage, core VDD 1. V DD must not exceed VDDIO VSS – 0.3 VSS + 2.0 V Supply voltage, IO Supply voltage, analog VDDIO VDDIO 2. V DDIO and VDDA must not differ by more that 0.5V VSSIO – 0.3 VSSA – 0.3 VSSIO + 4.0 VDDA + 4.0 V Digital input voltages Analog input voltages (XTAL, EXTAL) VIN VINA VSSIO – 0.3 VSSA – 0.3 VSSIO + 5.5 VDDA + 0.3 V Current drain per pin excluding VDD, VSS, VDDA, VSSA,VDDIO, VSSIO I — 10 mA Junction temperature TJ -40 120 °C Storage temperature range TSTG -55 150 °C Table 4-2 Recommended Operating Conditions Characteristic Symbol Min Max Unit Supply voltage for Logic Power VDD 1.62 1.98 V Supply voltage for I/O Power VDDIO 3.0 3.6 V Supply voltage for Analog Power VDDA 3.0 3.6 V Ambient operating temperature TA -40 85 °C PLL clock frequency1 1. Assumes clock source is direct clock to EXTAL or crys tal oscillator running 2-4MHz PLL must be enabled, locked, and selected. The actual frequency depends on the source clock frequency and programming of the CGM module. fpll — 240 MHz Operating Frequency2 2. Master clock is derived from one of the following four sources: fclk = fxtal when the source clock is the direct clock to EXAL fclk = fpll when PLL is selected fclk = fosc when the source clock is the crystal oscillator and PLL is not selected fclk = fextal when the source clock is the direct clock to EXAL and PLL is not selected fop — 120 MHz Frequency of peripheral bus fipb — 60 MHz Frequency of external clock fclk — 240 MHz Frequency of oscillator fosc 2 4 MHz Frequency of clock via XTAL fxtal — 240 MHz Frequency of clock via EXTAL fextal 2 4 MHz

56852 Technical Data, Rev. 8 Freescale Semiconductor 17

4.2 DC Electrical Characteristics

Table 4-3 Thermal Characteristics1 1. See Section 6.1 for more detail. Characteristic 81-pin MAPBGA Symbol Value Unit Thermal resistance junction-to-ambient (estimated) θJA 36.9 °C/W I/O pin power dissipation PI/O User Determined W Power dissipation PD PD = (IDD × VDD) + PI/O W Maximum allowed PD PDMAX (TJ – TA) / RθJA 2. TJ = Junction Temperature TA = Ambient Temperature W Table 4-4 DC Electrical Characteristics Operating Conditions: VSS = VSSIO = VSSA = 0V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL < 50pF, fop = 120MHz Characteristic Symbol Min Typ Max Unit Input high voltage (XTAL/EXTAL) VIHC VDDA – 0.8 VDDA VDDA + 0.3 V Input low voltage (XTAL/EXTAL) VILC -0.3 — 0.5 V Input high voltage VIH 2.0 — 5.5 V Input low voltage VIL -0.3 — 0.8 V Input current low (pullups disabled) IIL -1 — 1 μA Input current high (pullups disabled) IIH -1 — 1 μA Output tri-state current low IOZL -10 — 10 μA Output tri-state current high IOZH -10 — 10 μA Output High Voltage at IOH VOH VDDIO – 0.7 — — V Output Low Voltage at IOL VOL — — 0.4 V Output High Current at VOH IOH 8 — 16 mA Output Low Current at VOL IOL 8 — 16 mA Input capacitance CIN — 8 — pF Output capacitance COUT — 12 — pF

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VDD supply current (Core logic, memories, peripherals) Run 1 Deep Stop2 Light Stop3 IDD 0.02 3.4 2.5 mA mA mA VDDIO supply current (I/O circuity) Run5 Deep Stop2 IDDIO 300 mA μA VDDA supply current (analog circuity) Deep Stop2 IDDA — 60 120 μA Low Voltage Interrupt6 VEI — 2.5 2.85 V Low Voltage Interrupt Recovery Hysteresis VEIH — 50 — mV Power on Reset7 POR — 1.5 2.0 V Note: Run (operating) IDD measured using external square wave clock source (fosc = 4MHz) into XTAL. All inputs 0.2V from rail; no DC loads; outputs unloaded. All ports configured as inputs; measured with all modules enabled. PLL set to 240MHz out. 1. Running Core, performing 50% NOP and 50% FIR. Clock at 120 MHz. 2. Deep Stop Mode - Operation frequency = 4 MHz, PLL set to 4 MHz, crystal oscillator. 3. Light Stop Mode - Operation frequency = 120 MH z, PLL set to 240 MHz, crystal oscillator. 4. I DD includes current for core logic, internal memories, and all internal peripheral logic circuitry. 5. Running core and performing external memory access. Clock at 120 MHz. 6. When V DD drops below VEI max value, an interrupt is generated. 7. Power-on reset occurs whenever the digital supply drops below 1.8V. While power is ramping up, this signal remains active as long as the internal 2.5V is below 1.8V, no matter how long the ramp up rate is. The internally regulated voltage is typically 100mV less than VDD during ramp up until 2.5V is reached, at which time it self-regulates. Table 4-4 DC Electrical Characteristics (Continued) Operating Conditions: VSS = VSSIO = VSSA = 0V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL < 50pF, fop = 120MHz Characteristic Symbol Min Typ Max Unit

Supply Voltage Sequencing and Separation Cautions 56852 Technical Data, Rev. 8 Freescale Semiconductor 19 Figure 4-1 Maximum Run IDDTOTAL vs. Frequency (see Notes 1. and 5. in Table 4-4)

4.3 Supply Voltage Sequencing and Separation Cautions

Figure 4-2 shows two situations to avoid in sequencing the VDD and VDDIO, VDDA supplies. Note: 1. VDD rising before VDDIO, VDDA 2. VDDIO, VDDA rising much faster than VDD Figure 4-2 Supply Voltage Sequencing and Separation Cautions 120 150 20 40 60 80 100 120 IDD (mA) EMI Mode5 MAC Mode1 3.3V 1.8V Time0 Supplies Stable VDD VDDIO, VDDA DC Power Supply Voltage

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VDD should not be allowed to rise early (1). This is usually avoided by running the regulator for the VDD supply (1.8V) from the voltage generated by the 3.3V VDDIO supply, see Figure 4-3. This keeps VDD from rising faster than VDDIO. VDD should not rise so late that a large voltage difference is allo wed between the tw o supplies (2). Typically this situation is avoided by using external discrete diodes in series between supplies, as shown in Figure 4-3. The series diodes forward bias when the difference between V DDIO and V DD reaches approximately 2.1, causing V DD to rise as V DDIO ramps up. When the V DD regulator begins proper operation, the difference between supplies will typically be 0.8V and conduction through the diode chain reduces to essentially leakage current. During supply se quencing, the following general relationship should be adhered to: VDDIO > VDD > (VDDIO - 2.1V) In practice, VDDA is typically connected directly to VDDIO with some filtering. Figure 4-3 Example Circuit to Control Supply Sequencing

4.4 AC Electrical Characteristics

Timing waveforms in Section 4.2 are tested with a VIL maximum of 0.8V and a VIH minimum of 2.0V for all pins except XTAL, which is te sted using the input levels in Section 4.2. In Figure 4-4 the levels of VIH and VIL for an input signal are shown. Figure 4-4 Input Signal Measurement References 3.3V Regulator 1.8V Regulator Supply VDD VDDIO,VDDA VIH VILFall Time Input Signal Note: The midpoint is VIL + (VIH – VIL)/2. Midpoint1 Low High 90% 50% 10% Rise Time

56852 Technical Data, Rev. 8 Freescale Semiconductor 21 Figure 4-5 shows the definitions of the following signal states:

• Active state, when a bus or signal is driven, and enters a low impedance state
• Tri-stated, when a bus or signal is placed in a high impedance state
• Data Valid state, when a signal level has reached V OL or VOH
• Data Invalid state, when a signal level is in transition between VOL and VOH Figure 4-5 Signal States

4.5 External Clock Operation

The 56852 system clock can be derived from a crystal or an external system clock signal. To generate a reference frequency using the intern al oscillator, a reference crysta l must be connected between the EXTAL and XTAL pins.

4.5.1 Crystal Oscillato r for Use with PLL

The internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency range specified for the external crystal in Table 4-6. In Figure 4-6 a typical crystal os cillator circuit is shown. Follow the crystal supplier’ s recommendations when selecti ng a crystal, because crystal parameters determine the component values required to provide maximum stability and reliable start-up. The crystal and associated components should be mounted as close as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. Figure 4-6 Crystal Oscillator Data Invalid State Data1 Data2 Valid Data Tri-stated Data3 Valid Data2 Data3 Data1 Valid Data Active Data Active Sample External Crystal Parameters: Rz = 10MΩ TOD_SEL bit in CGM may be set to 0 or 1. 0 is recommended. Crystal Frequency = 2–4MHz (optimized for 4MHz) EXTAL XTAL Rz

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4.5.2 High Speed External Clock Source (> 4MHz)

The recommended method of connecting an external clock is given in Figure 4-7. The external clock source is connected to XTAL and the EXTA L pin is held at ground (recommended), VDDA, or VDDA/2. The TOD_SEL bit in CGM must be set to 1. Figure 4-7 Connecting a High Speed External Clock Signal using XTAL

4.5.3 Low Speed External Clock Source (2-4MHz)

The recommended method of connecting an external clock is given in Figure 4-8. The external clock source is connected to XTAL and the EXTAL pin is held at VDDA/2. The TOD_SEL bit in CGM may be set to 0 or 1. 0 is recommended. Figure 4-8 Connecting a Low Speed External Clock Signal using XTAL Table 4-5 External Clock Operation Timing Requirements4 Operating Conditions: VSS = VSSIO = VSSA = 0V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL £ 50pF, fop = 120MHz Characteristic Symbol Min Typ Max Unit Frequency of operation (external clock driver)1 1. See Figure 4-7 for details on using the recommended connection of an external clock driver. fosc 0 — 240 MHz Clock Pulse Width4 tPW 6.25 — — ns External clock input rise time2, 4 2. External clock input rise time is measured from 10 to 90 percent. trise — — TBD ns External clock input fall time3, 4 3. External clock input fall time is measured from 90 to 10percent. 4. Parameters listed are guaranteed by design. tfall — — TBD ns 56852 XTAL EXTAL External GND,VDDA, Clock (up to 240MHz) or VDDA/2 56852 XTAL EXTAL External Clock (2-4MHz) VDDA/2

External Memory Interface Timing 56852 Technical Data, Rev. 8 Freescale Semiconductor 23 Figure 4-9 External Clock Timing

4.6 External Memory Interface Timing

The External Memory Interface is designed to access static memory and peripheral devices. Figure 4-10 shows sample timing and parameters that are detailed in Table 4-7. The timing of each parameter consists of both a fixed delay portion and a clock related portion; as well as user controlled wait states. The equation: t = D + P * (M + W) should be used to determine the actual time of each parameter. The terms in the above equation are defined as: t parameter delay time D fixed portion of the delay, due to on-chip path delays. P the period of the system clock, wh ich determines the execution rate of the part (i.e. when the device is operating at 120 MHz, P = 8.33 ns). M Fixed portion of a clock period inherent in the desi gn. This number is adjusted to account for possible clock duty cycle derating. W the sum of the applicable wait state contro ls. See the “Wait State Controls” column of Table 4-7 for the applicable controls for each parameter. See the EMI chapter of the 83x Peripheral Manual for details of what each wait state field controls. Table 4-6 PLL Timing Operating Conditions: VSS = VSSIO = VSSA = 0V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL £ 50pF, fop = 120MHz Characteristic Symbol Min Typ Max Unit External reference crystal frequency for the PLL1 1. An externally supplied reference clock should be as free as possibl e from any phase jitter for the PLL to work correctly. The PLL is optimized for 4MHz input crystal. fosc 2 4 4 MHz PLL output frequency fclk 40 — 240 MHz PLL stabilization time 2 2. This is the minimum time required after the PL L setup is changed to ensure reliable operation. tplls — 1 10 ms External Clock VIH VIL Note: The midpoint is VIL + (VIH – VIL)/2. 90% 50% 10% 90% 50% 10% tPW tPW tfall trise

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Some of the parameters contain tw o sets of numbers. These paramete rs have two diff erent paths and clock edges that must be considered. Check both sets of numbers and use the smaller result. The appropriate entry may change if the operating frequency of the part changes. The timing of write cycles is different when WWS = 0 than when WWS > 0. Therefore, some parameters contain two sets of numbers to account for this difference. The “Wait States Configuration” column of Table 4-7 should be used to make the appropriate selection. Figure 4-10 External Memory Interface Timing tDRD tRDD tAD tDOH tDOS tDWR tRDWR tWAC tWRRDtWR tAWR tWRWR tARDD tRDA tRDRD tRD tARDA Data Out Data In A0-Axx,CS RD WR D0-D15 Note: During read-modify-write instructions and internal instructions, the address lines do not change state.

External Memory Interface Timing 56852 Technical Data, Rev. 8 Freescale Semiconductor 25 Table 4-7 External Memory Interface Timing Characteristic Symbol Wait States Configuration D M Wait States Controls Unit Address Valid to WR Asserted tAWR WWS=0 -0.75 0.50 WWSS ns WWS>0 -1.50 0.69 WR Width Asserted to WR Deasserted tWR WWS=0 -0.52 0.19 WWS ns WWS>0 -0.13 0.00 Data Out Valid to WR Asserted tDWR WWS=0 -1.86 0.00 WWSS ns WWS=0 - 6.03 0.25 WWS>0 -1.73 0.19 WWS>0 -4.29 0.50 Valid Data Out Hold Time after WR Deasserted tDOH -1.71 0.25 WWSH ns Valid Data Out Set Up Time to WR Deasserted tDOS -2.38 0.19 WWS,WWSS ns -4.42 0.50 Valid Address after WR Deasserted tWAC -1.44 0.25 WWSH RD Deasserted to Address Invalid tRDA - 0.51 0.00 RWSH ns Address Valid to RD Deasserted tARDD -2.03 1.00 RWSS,RWS ns Valid Input Data Hold after RD Deasserted tDRD 0.00 N/A1 1. N/A since device captures data before it deasserts RD — ns RD Assertion Width tRD -0.97 1.00 RWS ns Address Valid to Input Data Valid tAD -10.13 1.00 RWSS,RWS ns -13.22 1.19 Address Valid to RD Asserted tARDA - 1.06 0.00 RWSS ns RD Asserted to Input Data Valid tRDD -9.06 1.00 RWSS,RWS ns -12.65 1.19 WR Deasserted to RD Asserted tWRRD -0.70 0.25 WWSH,RWSS ns RD Deasserted to RD Asserted tRDRD -0.172 2. If RWSS = RWSH = 0, RD does not deassert duri ng back-to-back reads and D = 0.00 should be used.

0.00 RWSS,RWSH ns

WR Deasserted to WR Asserted tWRWR WWS=0 -0.47 0.75 WWSS, WWSH ns WWS>0 -0.07 1.00 RD Deasserted to WR Asserted tRDWR 0.10 0.50 MDAR, BMDAR, RWSH, WWSS ns -0.31 0.69

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4.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Table 4-8 Reset, Stop, Wait, Mode Select, and Interrupt Timing 1, 2 Operating Conditions: VSS = VSSIO = VSSA = 0V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL < 50pF, fop = 120MHz 1. In the formulas, T = clock cycle. For f op = 120MHz operation and fipb = 60MHz, T = 8.33ns. 2. Parameters listed are guaranteed by design. Characteristic Symbol Min Max Unit See Figure RESET Assertion to Address, Data and Control Signals High Impedance tRAZ — 11 ns 4-11 Minimum RESET Assertion Duration3 3. At reset, the PLL is disabled and bypassed. The part is then put into run mode and t clk assumes the period of the source clock, txtal, textal or tosc. tRA 30 — ns 4-11 RESET Deassertion to First External Address Output tRDA — 120T ns 4-11 Edge-sensitive Interrupt Request Width tIRW 1T + 3 — ns 4-12 IRQA, IRQB Assertion to External Data Memory Access Out Valid, caused by first instruction execution in the interrupt service routine tIDM 18T — ns 4-13 tIDM -FAST 14T — IRQA, IRQB Assertion to General Purpose Output Valid, caused by first instruction execution in the interrupt service routine tIG 18T — ns 4-13 tIG -FAST 14T — IRQA Low to First Valid Interrupt Vector Address Out recovery from Wait State4 4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This i s not the minimum required so that the IRQA interrupt is accepted. tIRI 22T — ns 4-14 tIRI -FAST 18T — Delay from IRQA Assertion (exiting Stop) to External Data Memory5 5. The interrupt instruction fetch is visible on the pins only in Mode 3. tIW 1.5T — ns 4-15 Delay from IRQA Assertion (exiting Wait) to External Data Memory Fast6 Normal7 6. Fast stop mode: Fast stop recovery applies when external clocking is in use (direct clocking to XTAL) or when fast stop mode recovery is requested (OMR bit 6 is set to 1). In both cases the PLL and the master clock are unaffected by stop mode entry. Recovery takes one less cycle and tclk will continue same value it had before stop mode was entered. 7. Normal stop mode: As a power saving feature, normal stop mo de disables and bypasses the PLL. Stop mode will then shut down the master clock, recovery will take an extra cycle (to restart the clock), and tclk will resume at the input clock source rate. tIF 18T 22ET — ns ns 4-15 RSTO pulse width8 normal operation internal reset mode 8. ET = External Clock period, For an exte rnal crystal frequency of 8MHz, ET=125 ns. tRSTO 128ET 8ET 4-16

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Figure 4-14 Interrupt from Wait State Timing Figure 4-15 Recovery from Stop State Using Asynchronous Interrupt Timing Figure 4-16 Reset Output Timing Instruction Fetch IRQA, IRQB First Interrupt VectorA0–A20, CS, RD, WR tIRI Not IRQA Interrupt Vector IRQA A0–A20, CS, RD, WR First Instruction Fetch tIW tIF RESET tRSTO

Serial Peripheral Interface (SPI) Timing 56852 Technical Data, Rev. 8 Freescale Semiconductor 29

4.8 Serial Peripheral Interface (SPI) Timing

Operating Conditions: VSS = VSSIO = VSSA = 0V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL < 50pF, fop = 120MHz 1. Parameters listed are guaranteed by design. Characteristic Symbol Min Max Unit See Figure Cycle time Master Slave tC ns ns 4-17, 4-18, 4-19, 4-20 Enable lead time Master Slave tELD 12.5 ns ns 4-20 Enable lag time Master Slave tELG 12.5 ns ns 4-20 Clock (SCLK) high time Master Slave tCH 12.5 ns ns 4-17, 4-18, 4-19, 4-20 Clock (SCLK) low time Master Slave tCL 12.5 ns ns 4-20 Data setup time required for inputs Master Slave tDS ns ns 4-17, 4-18, 4-19, 4-20 Data hold time required for inputs Master Slave tDH ns ns 4-17, 4-18, 4-19, 4-20 Access time (time to data active from high-impedance state) Slave tA 5 15 ns ns 4-20 Disable time (hold time to high-impedance state) Slave tD 2 9 ns ns 4-20 Data Valid for outputs Master Slave (after enable edge) tDV ns ns 4-17, 4-18, 4-19, 4-20 Data invalid Master Slave tDI ns ns 4-17, 4-18, 4-19, 4-20 Rise time Master Slave tR 11.5 10.0 ns ns 4-17, 4-18, 4-19, 4-20 Fall time Master Slave tF 9.7 9.0 ns ns 4-17, 4-18, 4-19, 4-20

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Figure 4-17 SPI Master Timing (CPHA = 0) Figure 4-18 SPI Master Timing (CPHA = 1) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) MOSI (Output) MSB in Bits 14–1 LSB in Master MSB out Bits 14–1 Master LSB out SS (Input) SS is held High on master tC tR tF tCH tCL tF tR tCH tCH tDV tDH tDS tDI tDI(ref) tF tR tCL SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) MOSI (Output) MSB in Bits 14–1 LSB in Master MSB out Bits 14– 1 Master LSB out SS (Input) SS is held High on master tR tF tC tCH tCL tCH tCL tF tDS tDH tR tDItDV(ref) tDV tF tR

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4.9 Quad Timer Timing

Table 4-10 Timer Timing1, 2 Operating Conditions: VSS = VSSIO = VSSA = 0V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz 1. In the formulas listed, T = clock cycle. For f op = 120MHz operation and fipb = 60MHz, T = 8.33ns 2. Parameters listed are guaranteed by design. Characteristic Symbol Min Max Unit Timer input period PIN 2T + 3 — ns Timer input high/low period PINHL 1T + 3 — ns Timer output period POUT 2T - 3 — ns Timer output high/low period POUTHL 1T - 3 — ns Timer Inputs Timer Outputs PINHL PINHLPIN POUTHLPOUTHLPOUT

Synchronous Serial Interface (SSI) Timing 56852 Technical Data, Rev. 8 Freescale Semiconductor 33

4.10 Synchronous Serial Interface (SSI) Timing

Table 4-11 SSI Master Mode1 Switching Characteristics Operating Conditions: VSS = VSSIO = VSSA = 0V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL < 50pF, fop = 120MHz 1. Master mode is internally generated clocks and frame syncs Parameter Symbol Min Typ Max Units STCK frequency fs 152 MHz STCK period3 tSCKW 66.7 ns STCK high time tSCKH 33.4 ns STCK low time tSCKL 33.4 ns Output clock rise/fall time 4 ns Delay from STCK high to STFS (bl) high - Master4 tTFSBHM -1.0 -0.1 ns Delay from STCK high to STFS (wl) high - Master4 tTFSWHM -1.0 -0.1 ns Delay from SRCK high to SRFS (bl) high - Master4 tRFSBHM 0.1 1.0 ns Delay from SRCK high to SRFS (wl) high - Master4 tRFSWHM 0.1 1.0 ns Delay from STCK high to STFS (bl) low - Master4 tTFSBLM -1.0 -0.1 ns Delay from STCK high to STFS (wl) low - Master4 tTFSWLM -1.0 -0.1 ns Delay from SRCK high to SRFS (bl) low - Master4 tRFSBLM -0.1 0.1 ns Delay from SRCK high to SRFS (wl) low - Master4 tRFSWLM -0.1 0.1 ns STCK high to STXD enable from high impedance - Master tTXEM 0 1 ns STCK high to STXD valid - Master tTXVM 0 1 ns STCK high to STXD not valid - Master tTXNVM -0.1 0 ns STCK high to STXD high impedance - Master tTXHIM -4 0 ns SRXD Setup time before SRCK low - Master tSM 4 ns SRXD Hold time after SRCK low - Master tHM 4 ns Synchronous Operation (in addition to standard internal clock parameters) SRXD Setup time before STCK low - Master tTSM 4 SRXD Hold time after STCK low - Master tTHM 4

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Figure 4-22 Master Mode Timing Diagram 2. Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for a 120MHz part. 3. All the timings for the SSI are given for a non-inverted se rial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR) and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync has been inverted, all the timings remain valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS in the tables and in the figures. 4. bl = bit length; wl = word length tTHM tTSM tHMtSM tRFSWLMtRFSWHM tRFBLMtRFSBHM tTXHIMtTXNVM tTXVM tTXEM tTFSWLMtTFSWHM tTFSBLMtTFSBHM tSCKL tSCKW tSCKH First Bit Last Bit STCK output STFS (bl) output STFS (wl) output STXD SRCK output SRFS (bl) output SRFS (wl) output SRXD

Synchronous Serial Interface (SSI) Timing 56852 Technical Data, Rev. 8 Freescale Semiconductor 35 Table 4-12 SSI Slave Mode1 Switching Characteristics Operating Conditions: VSS = VSSIO = VSSA = 0V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Parameter Symbol Min Typ Max Units STCK frequency fs 152 MHz STCK period3 tSCKW 66.7 ns STCK high time tSCKH 33.44 ns STCK low time tSCKL 33.44 ns Output clock rise/fall time 4 ns Delay from STCK high to STFS (bl) high - Slave5 tTFSBHS -1 29 ns Delay from STCK high to STFS (wl) high - Slave5 tTFSWHS -1 29 ns Delay from SRCK high to SRFS (bl) high - Slave5 tRFSBHS -1 29 ns Delay from SRCK high to SRFS (wl) high - Slave5 tRFSWHS -1 29 ns Delay from STCK high to STFS (bl) low - Slave5 tTFSBLS -29 29 ns Delay from STCK high to STFS (wl) low - Slave5 tTFSWLS -29 29 ns Delay from SRCK high to SRFS (bl) low - Slave5 tRFSBLS -29 29 ns Delay from SRCK high to SRFS (wl) low - Slave5 tRFSWLS -29 29 ns STCK high to STXD enable from high impedance - Slave tTXES — 15 ns STCK high to STXD valid - Slave tTXVS 4 15 ns STFS high to STXD enable from high impedance (first bit) - Slave tFTXES 4 15 ns STFS high to STXD valid (first bit) - Slave tFTXVS 4 15 ns STCK high to STXD not valid - Slave tTXNVS 4 15 ns STCK high to STXD high impedance - Slave tTXHIS 4 15 ns SRXD Setup time before SRCK low - Slave tSS 4 — ns

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Figure 4-23 Slave Mode Clock Timing SRXD Hold time after SRCK low - Slave tHS 4 — ns Synchronous Operation (in addition to standard external clock parameters) SRXD Setup time before STCK low - Slave tTSS 4 — ? SRXD Hold time after STCK low - Slave tTHS 4 — ? 1. Slave mode is externally generated clocks and frame syncs 2. Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for a 120MHz part. 3. All the timings for the SSI are given for a non-inverted se rial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR) and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync has been inverted, all the timings remain valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS in the tables and in the figures. 4. 50 percent duty cycle 5. bl = bit length; wl = word length Table 4-12 SSI Slave Mode1 Switching Characteristics (Continued) Operating Conditions: VSS = VSSIO = VSSA = 0V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Parameter Symbol Min Typ Max Units tTHStTSStHStSS tRFSWLS tRFSWHS tRFSBLStRFSBHS tTXHIS tTXNVS tFTXVS tTXVS tFTXES tTXES tTFSWLStTFSWHS tTFSBLS tTFSBHS tSCKL tSCKW tSCKH First Bit Last Bit STCK input STFS (bl) input STFS (wl) input STXD SRCK input SRFS (bl) input SRFS (wl) input SRXD

Serial Communication Interface (SCI) Timing 56852 Technical Data, Rev. 8 Freescale Semiconductor 37

4.11 Serial Communication Interface (SCI) Timing

Figure 4-24 RXD Pulse Width Figure 4-25 TXD Pulse Width Figure 4-26 Bus Wake-up Detection Table 4-13 SCI Timing4 Operating Conditions: VSS = VSSIO = VSSA = 0V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Characteristic Symbol Min Max Unit Baud Rate1 1. f MAX is the frequency of operation of the system clock in MHz. BR — (fMAX)/(32) Mbps RXD2 Pulse Width 2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1. RXDPW 0.965/BR 1.04/BR ns TXD3 Pulse Width 3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1. 4. Parameters listed are guaranteed by design. TXDPW 0.965/BR 1.04/BR ns RXD SCI receive data pin (Input) RXDPW TXD SCI receive data pin (Input) TXDPW MSCAN_RX CAN receive data pin (Input) T WAKE-UP

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4.12 JTAG Timing

Figure 4-27 Test Clock Input Timing Diagram Table 4-14 JTAG Timing1, 3 Operating Conditions: VSS = VSSIO = VSSA = 0V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz 1. Timing is both wait state and frequency dependent. Fo r the values listed, T = clock cycle. For120MHz operation, T = 8.33 ns Characteristic Symbol Min Max Unit TCK frequency of operation2 2. TCK frequency of operation must be less than 1/4 the processor rate. 3. Parameters listed are guaranteed by design. fOP DC 30 MHz TCK cycle time tCY 33.3 — ns TCK clock pulse width tPW 16.6 — ns TMS, TDI data setup time tDS 3 — ns TMS, TDI data hold time tDH 3 — ns TCK low to TDO data valid tDV — 12 ns TCK low to TDO tri-state tTS — 10 ns TRST assertion time tTRST 35 — ns DE assertion time tDE 4T — ns TCK (Input) VM VIL VM = VIL + (VIH – VIL)/2 VM VIH tPWtPW tCY

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4.13 GPIO Timing

Operating Conditions: VSS = VSSIO = VSSA = 0V, VDD = 1.7-1.9V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Characteristic Symbol Min Max Unit GPIO input period PIN 2T + 3 — ns GPIO input high/low period PINHL 1T + 3 — ns GPIO output period POUT 2T - 3 — ns GPIO output high/low period POUTHL 1T - 3 — ns GPIO Inputs GPIO Outputs PINHL PINHLPIN POUTHLPOUTHLPOUT

56852 Technical Data, Rev. 8 Freescale Semiconductor 41 Part 5 56852 Packaging & Pinout Information This section contains package and pin-out information for the 81-pin MAPBGA configuration of the 56852. Figure 5-1 Bottom-View, 56852 81-pin MAPBGA Package METALLIZED MARK FOR PIN 1 IDENTIFICATION IN THIS AREA A B C D E F G H J 123456789 IRQAGPIOC1SCKVDDIOVSSIOTD0 EXTAL VDDATDI GPIOC0SSRXD IRQB VDDIO VSSIO TXD V SSCS0 MOSI MISO CS1 D14 TMS TCK D15 DE VSSAVDDIO VSSIO CS2 RESET RD VDD D13 D12 TRST D8VDD D11 D10D9 A16 VSS D6 A0 WR VSSIOD3VDDIO D5 A17 D0 D7 A18 A12 A14 A3 A6A5 A15 A8 VDDIOA11 A9D2 A19D1D4 VSSIO CLKO V DDIO VSSIO VDD VSS A13 A10 XTAL A4A2

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Table 5-1 56852 Pin Identification by Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name E4 A0 D2 CS0 A6 EXTAL H1 VDDIO F2 A1 D3 CS1 B6 VSSA J7 VDDIO F3 A2 C3 CS2 D1 VSS G9 VDDIO F4 A3 G7 D0 J4 VSS B9 VDDIO F1 A4 H7 D1 F9 VSS A4 VDDIO G3 A5 H8 D2 B1 VSSIO E2 RD G2 A6 G8 D3 G1 VSSIO D5 RESET J1 A7 H9 D4 J6 VSSIO B4 RXD H2 A8 F8 D5 J9 VSSIO A3 SCK H3 A9 F7 D6 C9 VSSIO A2 GPIOC1 J2 A10 G6 D7 A5 VSSIO B3 SS H4 A11 E8 D8 A1 IRQA B2 GPIOC0 G4 A12 E7 D9 C2 IRQB C6 TCK J3 A13 E6 D10 C4 MISO B7 TDI F5 A14 D8 D11 C5 MOSI A8 TDO H5 A15 D7 D12 B5 VDDA C7 TMS E5 A16 D9 D13 E1 VDD D6 TRST F6 A17 C8 D14 J5 VDD D4 TXD G5 A18 A9 D15 E9 VDD E3 WR H6 A19 B8 DE C1 VDDIO A7 XTAL J8 CLKO - - - - - -

Thermal Design Considerations 56852 Technical Data, Rev. 8 Freescale Semiconductor 43 Part 6 Design Considerations

6.1 Thermal Design Considerations

An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation: Equation 1: T J = TA + (PD x RθJA) Where: TA = ambient temperature °C RθJA = package junction-to-ambient thermal resistance °C/W PD = power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: Equation 2: R θJA = RθJC + RθCA Where: RθJA = package junction-to-ambient thermal resistance °C/W RθJC = package junction-to-case thermal resistance °C/W RθCA = package case-to-ambient thermal resistance °C/W RθJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RθCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting ar rangement on the Printed Ci rcuit Board (PCB), or otherwise change the thermal dissipation capability of the area su rrounding the device on the PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For cera mic packages, in situations where the heat flow is split between a path to the case a nd an alternate path through the PCB, analysis of the device thermal performance may need the additional modeli ng capability of a sy stem level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from RθJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. A complicating factor is the existe nce of three common definitions fo r determining the junction-to-case thermal resistance in plastic packages:

• Measure the thermal resistance from the junction to th e outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation across the surface.
• Measure the thermal resistance from the junction to where the leads are attached to the case. This definition is approximately equal to a junction to board thermal resistance.
• Use the value obtained by the equation (T J – TT)/PD where TT is the temperature of the package case determined by a thermocouple.

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As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a pr actical standpoint, that va lue is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual. Hence, the new thermal metric, Thermal Characterization Parameter, or ΨJT, has been defined to be (TJ – TT)/PD. This value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy.

6.2 Electrical Design Considerations

Use the following list of considerations to assure correct operation:

• Provide a low-impedance path from the board power supply to each V DD pin on the device, and from the board ground to each VSS (GND) pin.
• The minimum bypass requirement is to place six 0.01–0.1 μF capacitors positioned as close as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the ten VDD/VSS pairs, including VDDA/VSSA.
• Ensure that capacitor leads and associated prin ted circuit traces that connect to the chip VDD and VSS (GND) pins are less than 0.5 inch per capacitor lead.
• Use at least a four-layer Printed Circui t Board (PCB) with two inner layers for VDD and GND.
• Bypass the V DD and GND layers of the PCB with approximately 100μF, preferably with a high-grade capacitor such as a tantalum capacitor.
• Because the device’s output signals have fast rise and fall times, PCB trace lengths should be minimal.
• Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and GND circuits.
• All inputs must be terminated (i.e., no t allowed to float) using CMOS levels. CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.

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• Take special care to minimize noise levels on the V DDA and VSSA pins.
• When using Wired-OR mode on the SPI or the IRQx pins, the user must provide an external pull-up device.
• Designs that utilize the TRST pin for JTAG port or Enhance OnCE module functionality (such as development or debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means to assert TRST independently of RESET. Designs that do not require debugging functionality, such as consumer products, should tie these pins together.
• The internal POR (Power on Reset) will reset the part at power on with reset asserted or pulled high but requires that TRST be asserted at power on.

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Part 7 Ordering Information Table 7-1 lists the pertinent information needed to pl ace an order. Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order parts. *This package is RoHS compliant. Table 7-1 56852 Ordering Information Part Supply Voltage Package Type Pin Count Frequency (MHz) Order Number DSP56852 1.8–3.3 V Mold Array Process Ball Grid Array (MAPBGA) 81 120 DSP56852VF120 DSP56852 1.8–3.3 V Mold Array Process Ball Grid Array (MAPBGA) 81 120 DSP56852VFE *

Electrical Design Considerations 56852 Technical Data, Rev. 8 Freescale Semiconductor 47

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