552-02S RENESAS

Document overview

  • Manufacturer or author: mamiller
  • PDF pages: 13

Technical content

Features

  • Low RMS Additive Phase Jitter: 50fs
  • Low output skew: 50ps
  • Operating Voltages of 1.8V to 3.3V
  • Packaged in 16-pin TSSOP and 16-pin VFQFN, Pb-free
  • Input clock multiplexer simplifies clock selection
  • Output Enable pin tri-states outputs
  • Input/Output clock frequency up to 200 MHz
  • Low power CMOS technology
  • 3.3V tolerant inputs
  • Extended temperature (-40°C to +105°C) Block Diagram OE INA INB SELA

LOW SKEW 2-INPUT MUX AND 1 TO 8 CLOCK BUFFER 2 APRIL 18, 2017 552-02S DATASHEET Pin Assignments Input Source Select Pin Descriptions External Components A minimum number of external components are required for proper operation. Decoupling capacitors of 0.01F should be connected between VDD on pin 2 and GND on pin 7, and between VDD on pin 15 and GND on pin 10, as close to the device as possible. A 33  series terminating resistor should be used on each clock output if the trace is longer than 1 inch. To achieve the low output skews that the 552-02S is capable of, careful attention must be paid to board layout. Essentially, all 8 outputs must have identical terminations, identical loads, and identical trace geometries. If they do not, the output skew will be degraded. For example, using a 30series termination on one output (with 33 on the others) will cause at least 15ps of skew. SELA Input 0I N B 1I N A Pin Number Pin Name Pin Type Pin Description 1 OE Input Output Enable. Tri-states outputs when low. Internal pull-up resistor. 3 Q0 Output Clock Output 0. 4 Q1 Output Clock Output 1. 5 Q2 Output Clock Output 2. 6 Q3 Output Clock Output 3. 7 GND Power Connect to ground. 8 INB Input Clock Input B. 3.3V tolerant. 9 INA Input Clock Input A. 3.3V tolerant. 10 GND Power Connect to ground. 11 Q4 Output Clock Output 4. 12 Q5 Output Clock Output 5. 13 Q6 Output Clock Output 6. 14 Q7 Output Clock Output 7. 16 SELA Input Selects either INA or INB. Internal pull-up resistor. OE VDD VDD Q3 Q4 INA GND GND INB SELA

16 Pin TSSOP

APRIL 18, 2017 3 LOW SKEW 2-INPUT MUX AND 1 TO 8 CLOCK BUFFER 552-02S DATASHEET Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 552-02S. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Recommended Operation Conditions Item Rating Supply Voltage, VDD 3.465V All Inputs and Outputs -0.5 V to 3.465V Ambient Operating Temperature, Extended -40 to +105°C Storage Temperature -65 to +150 C Junction Temperature 175 C Soldering Temperature 260 C Parameter Min. Typ. Max. Units Ambient Operating Temperature, Extended -40 – +105 C Power Supply Voltage (measured in respect to GND) +1.71 +3.465 V

LOW SKEW 2-INPUT MUX AND 1 TO 8 CLOCK BUFFER 4 APRIL 18, 2017 552-02S DATASHEET VDD=1.8 V ±5%, Ambient temperature -40°C to +105°C, unless stated otherwise VDD=2.5 V ±5%, Ambient temperature -40°C to +105°C, unless stated otherwise VDD=3.3 V ±5%, Ambient temperature -40°C to +105°C, unless stated otherwise Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 1.71 1.89 V Input High Voltage, INA, INB V IH Note 1 0.7xVDD 1.89 V Input Low Voltage, INA, INB V IL Note 1 0.3xVDD V Input High Voltage, OE, SELA V IH 0.7xVDD VDD V Input Low Voltage, OE, SELA V IL 0.3xVDD V Output High Voltage V OH IOH = -10 mA 1.3 V Output Low Voltage V OL IOL = 10 mA 0.35 V Operating Supply Current IDD No load, 135 MHz 32 mA Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 2.375 2.625 V Input High Voltage, INA, INB V IH Note 1 0.7xVDD 2.625 V Input Low Voltage, INA, INB V IL Note 1 0.3xVDD V Input High Voltage, OE, SELA V IH 0.7xVDD VDD V Input Low Voltage, OE, SELA V IL 0.3xVDD V Output High Voltage V OH IOH = -16 mA 1.8 V Output Low Voltage V OL IOL = 16 mA 0.5 V Operating Supply Current IDD No load, 135 MHz 43 mA Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 3.135 3.465 V Input High Voltage, INA, INB V IH Note 1 0.7xVDD 3.465 V Input Low Voltage, INA, INB V IL Note 1 0.3xVDD V Input High Voltage, OE, SELA V IH 0.7xVDD VDD V Input Low Voltage, OE, SELA V IL 0.3xVDD V Output High Voltage V OH IOH = -25 mA 2.2 V Output Low Voltage V OL IOH = 25 mA 0.7 V Operating Supply Current IDD No load, 135 MHz 55 mA

APRIL 18, 2017 5 LOW SKEW 2-INPUT MUX AND 1 TO 8 CLOCK BUFFER 552-02S DATASHEET VDD = 1.8V ±5%, Ambient Temperature -40°C to +105°C, unless stated otherwise VDD = 2.5V ±5%, Ambient Temperature -40°C to +105°C, unless stated otherwise VDD = 3.3V ±5%, Ambient Temperature -40°C to +105°C, unless stated otherwise Notes: 1. With rail-to-rail input clock. 2. Between any two outputs with equal loading. 3. Propagation delay matching through the part. 4. Duty cycle on outputs will match incoming clock duty cycle. Consult IDT for tight duty cycle clock generators. Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency 0 200 MHz Output Rise Time t OR 0.36 to 1.44 V, CL=5 pF 1 1.5 ns Output Fall Time t OF 1.44 to 0.36 V, CL=5 pF 1 1.5 ns Start-up Time t START-UP Part start-up time for valid outputs after VDD ramp-up 2m s Propagation Delay Note 1 135MHz 2 2.5 3 ns Buffer Additive Phase Jitter, RMS 125MHz , Integration Range: 12KHz-20MHz 50 65 ps Output to output skew Note 2 Rising edges at VDD/2 0 65 ps Input A to Input B skew Note 3 0 50 ps Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency 0 200 MHz Output Rise Time t OR 0.5 to 2.0 V, CL=5 pF 0.6 1.0 ns Output Fall Time t OF 2.0 to 0.5 V, CL=5 pF 0.6 1.0 ns Start-up Time t START-UP Part start-up time for valid outputs after VDD ramp-up 2m s Propagation Delay Note 1 135MHz 2 2.7 3.5 ns Buffer Additive Phase Jitter, RMS 125MHz , Integration Range: 12KHz-20MHz 50 65 ps Output to output skew Note 2 Rising edges at VDD/2 0 65 ps Input A to Input B skew Note 3 0 50 ps Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency 0 200 MHz Output Rise Time t OR 0.66 to 2.64 V, CL=5 pF 0.6 1.0 ns Output Fall Time t OF 2.64 to 0.66 V, CL=5 pF 0.6 1.0 ns Start-up Time t START-UP Part start-up time for valid outputs after VDD ramp-up 2m s Propagation Delay Note 1 135MHz 2 2.5 3 ns Buffer Additive Phase Jitter, RMS 125MHz , Integration Range: 12KHz-20MHz 50 65 ps Output to output skew Note 2 Rising edges at VDD/2 0 65 ps Input A to Input B skew Note 3 0 50 ps

LOW SKEW 2-INPUT MUX AND 1 TO 8 CLOCK BUFFER 6 APRIL 18, 2017 552-02S DATASHEET Package Outline and Dimensions (16-pin VFQFN)

APRIL 18, 2017 7 LOW SKEW 2-INPUT MUX AND 1 TO 8 CLOCK BUFFER 552-02S DATASHEET Package Outline and Dimensions, cont. (16-pin VFQFN)

LOW SKEW 2-INPUT MUX AND 1 TO 8 CLOCK BUFFER 8 APRIL 18, 2017 552-02S DATASHEET Package Outline and Dimensions (16-pin TSSOP)

APRIL 18, 2017 9 LOW SKEW 2-INPUT MUX AND 1 TO 8 CLOCK BUFFER 552-02S DATASHEET Package Outline and Dimensions (16-pin TSSOP), cont.

LOW SKEW 2-INPUT MUX AND 1 TO 8 CLOCK BUFFER 10 APRIL 18, 2017 552-02S DATASHEET Package Outline and Dimensions (16-pin TSSOP), cont.

APRIL 18, 2017 11 LOW SKEW 2-INPUT MUX AND 1 TO 8 CLOCK BUFFER 552-02S DATASHEET

Ordering Information

“G” after the two-letter package code denotes Pb-Free configuration, RoHS compliant. Marking Diagrams Notes: 1. “**” is the lot sequence. 2. “Y YWW” or “Y” is the last digit(s) of the year and week that the part was assembled. 3. “ $” denotes the mark code. 4. “ LOT” denotes lot number. 5. “G ” after the two-letter package code denotes RoHS compliant package. 6. “I” denotes extended temperature range device. Bottom ma rking: country of origin (TSSOP only).

Revision History

Part / Order Number Marking Shippi ng Packaging Package Temperature 552-02SPGGI TBD Tubes 16-pin TSSOP -40°C to +105°C 552-02SPGGI8 Tape and Reel 16-pin TSSOP -40°C to +105°C 552-02SCMGI Tubes 16-pin VFQFN -40°C to +105°C 552-02SCMGI8 Tape and Reel 16-pin VFQFN -40°C to +105°C Rev. Date Originator Description of Change B 04/18/17 C.P. 1. Replaced package outline drawi ngs with latest CMG16 and PGG16 versions. 2. Updated legal disclaimer. A 07/11/16 H.G. Release to final. 02SI Y** 16-pin QFN IDT552-0 2SPGGI YYWW$ 16-pin TSSOP LOT

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of Corporate Headquarters

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San Jose, CA 95138 USA www.IDT.com Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Tech Support www.idt.com/go/support 552-02S APRIL 18, 2017 12 ©2017 Integrated Device Technology, Inc.

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