Download PDF54VHC373 SS
Document overview
- PDF pages: 7
Technical content
Page 1
Rev 1.0
8-bit transparent D-Type Latch with 3-State Outputs in bare die form
Description
The 54VHC373 consists of eight D-type transparent latches fabricated using a 1.5µm 5V advanced CMOS process to combine high speed performance LSTTL performance with CMOS low power consumption. Each latch is equipped with separate D-Type inputs and 3-State outputs for bus oriented applications. Data output changes asynchronously and data may be latched even when the outputs are not enabled. Device inputs accept standard CMOS outputs or LSTTL outputs using pull-up resistors. All inputs are equipped with protection circuits against static discharge and transient excess voltage.
Ordering Information
The following part suffixes apply:
No suffix - MIL-STD-883 /2010B Visual Inspection
“H” - MIL-STD-883 /2010B Visual Inspection
+ MIL-PRF-38534 Class H LAT
“K” - MIL-STD-883 /2010A Visual Inspection (Space)
+ MIL-PRF-38534 Class K LAT
LAT = Lot Acceptance Test.
For further information on LAT process flows see below.
www.siliconsupplies.com\quality\bare-die-lot-qualification
Supply Formats:
Default – Die in Waffle Pack (100 per tray capacity)
Sawn Wafer on Tape – On request
Unsawn Wafer – On request
Die Thickness <> 350µm(14 Mils) – On request
Assembled into Ceramic Package – On request
Page 1 of 7
26/09/20
Features:
High Speed: tPD = 7.2ns (MAX) VCC = 5V
Outputs Sink/Source 8mA
Outputs directly interface CMOS, NMOS and TTL
Low Input Current: 1µA
Operating Voltage Range: 2V to 5.5V
Replacement for 54HC373, 54AC373, 54AHC373
Full Military Temperature Range.
Die Dimensions in µm (mils)
1630 (64)
Mechanical Specification
| Die Size (Unsawn) | 1630 x 1630 64 x 64 | µm mils |
| Minimum Bond Pad Size | 108 x 108 4.25 x 4.25 | µm mils |
| Die Thickness | 350 (±20) 13.78 (±0.79) | µm mils |
| Top Metal Composition | Al 1%Si 1.1µm | |
| Back Metal Composition | N/A – Bare Si | |
Page 2
Rev 1.0
Pad Layout and Functions
26/09/20
| 1630µm (64.17 mils) | 18 17 16 15 14 13 19 DIE ID 12 20 11 21 10 1 2 9 3 4 5 6 7 8 |
| 0,0 | 1630µm (64.17 mils) |
| PAD | FUNCTION | COORDINATES (mm) | |
| X | Y | ||
| 1 | OE | 0.149 | 0.489 |
| 2 | 1Q | 0.149 | 0.319 |
| 3 | 1D | 0.182 | 0.149 |
| 4 | 2D | 0.498 | 0.149 |
| 5 | 2Q | 0.674 | 0.149 |
| 6 | 3Q | 0.855 | 0.149 |
| 7 | 3D | 1.025 | 0.149 |
| 8 | 4D | 1.341 | 0.149 |
| 9 | 4Q | 1.379 | 0.319 |
| 10 | GND | 1.379 | 0.499 |
| 11 | LE | 1.379 | 1.0275 |
| 12 | 5Q | 1.379 | 1.2085 |
| 13 | 5D | 1.341 | 1.3785 |
| 14 | 6D | 1.025 | 1.3785 |
| 15 | 6Q | 0.855 | 1.3785 |
| 16 | 7Q | 0.674 | 1.3785 |
| 17 | 7D | 0.498 | 1.3785 |
| 18 | 8D | 0.182 | 1.3785 |
| 19 | 8Q | 0.149 | 1.2085 |
| 20 | V CC | 0.149 | 1.0385 |
| 21 | V CC | 0.149 | 0.722 |
| CONNECT CHIP BACK TO V OR FLOAT CC | |||
Logic Diagram
Truth Table
| INPUTS | OUTPUT | ||
| OE | LE | D | Q |
| L L L H | H H L X | H L X X | H L No Change Z |
| H = High level (steady state) L = Low level (steady state) Z = High Impedance X = Don’t care | |||
Pad 10 = GND, Pad 20 & 21 = VCC
Page 2 of 7
Page 3
Rev 1.0
Absolute Maximum Ratings1
26/09/20
| PARAMETER | SYMBOL | VALUE | UNIT |
|---|---|---|---|
| DC Supply Voltage (Referenced to GND) | V CC | -0.5 to +7.0 | V |
| DC Input Voltage (Referenced to GND) | V IN | -0.5 to +7.0 | V |
| DC Output Voltage (Referenced to GND) | V OUT | -0.5 to V +0.5 CC | V |
| DC Input Current, per pad | I IN | ±20 | mA |
| DC Output Current, per pad | I OUT | ±25 | mA |
| DC Supply Current, V or GND CC | I CC | ±75 | mA |
| Power Dissipation in Still Air2 | P D | 180 | mW |
| Storage Temperature Range | T STG | -65 to 150 | °C |
- Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method.
Recommended Operating Conditions3 (Voltages referenced to GND)
| PARAMETER | SYMBOL | MIN | MAX | UNITS | |
|---|---|---|---|---|---|
| DC Supply Voltage | V CC | 2 | 5.5 | V | |
| DC Input or Output Voltage | V ,V IN OUT | 0 | V CC | V | |
| Operating Temperature Range | T J | -55 | +125 | °C | |
| Output Current | I OUT | - | ±8 | mA | |
| Input Rise and Fall Time | V = 3.3V CC V = 5.5V CC | t, t r f | 0 | 100 | ns/V |
| 0 | 20 | ||||
- This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND ≤ (VIN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
DC Electrical Characteristics (Voltages Referenced to GND)
| PARAMETER | SYMBOL | V CC | CONDITIONS | LIMITS | UNITS | ||
|---|---|---|---|---|---|---|---|
| 25°C | 85°C | FULL RANGE4 | |||||
| Minimum High-Level Input Voltage | V IH | 2.0V | V = 0.1V or OUT V -0.1V CC │I │≤ 20µA OUT | 1.50 | 1.50 | 1.50 | V |
| 3.0V | 2.10 | 2.10 | 2.10 | ||||
| 5.5V | 3.85 | 3.85 | 3.85 | ||||
| Maximum Low-Level Input Volt age | V IL | 2.0V | V = 0.1V or OUT V -0.1V CC │I │≤ 20µA OUT | 0.50 | 0.50 | 0.50 | V |
| 3.0V | 0.90 | 0.90 | 0.90 | ||||
| 5.5V | 1.65 | 1.65 | 1.65 | ||||
| Minimum High-Level Output Voltage | V OH | 2.0V | V = V or V IN IH IL │I │-50µA OUT | 1.92 | 1.90 | 1.90 | V |
| 3.0V | 2.92 | 2.90 | 2.90 | ||||
| 4.5V | 4.42 | 4.40 | 4.40 | ||||
| 5.5V | 5.52 | 5.40 | 5.40 | ||||
| 3.0V | V = V or V IN IH IL │I │-4mA OUT | 2.58 | 2.48 | 2.40 | |||
| 4.5V | V = V or V IN IH IL │I │-8mA OUT | 3.94 | 3.80 | 3.70 | |||
Page 3 of 7
Page 4
Rev 1.0
DC Electrical Characteristics Continued (Voltages Referenced to GND)
26/09/20
| PARAMETER | SYMBOL | V CC | CONDITIONS | LIMITS | UNITS | ||
|---|---|---|---|---|---|---|---|
| 25°C | 85°C | FULL RANGE4 | |||||
| Maximum Low-Level Output Voltage | V OL | 2.0V | V = V or V IN IH IL │I │= 50µA OUT | 0.09 | 0.10 | 0.10 | V |
| 3.0V | 0.09 | 0.10 | 0.10 | ||||
| 4.5V | 0.09 | 0.10 | 0.10 | ||||
| 5.5V | 0.09 | 0.10 | 0.10 | ||||
| 3.0V | V = V or V IN IH IL │I │= 4mA OUT | 0.36 | 0.44 | 0.50 | |||
| 4.5V | V = V or V IN IH IL │I │= 8mA OUT | 0.36 | 0.44 | 0.50 | |||
| Maximum Input Leakage Current | I IN | 5.5V | V = V or GND IN CC | ±0.1 | ±1.0 | ±2.0 | µA |
| Maximum 3-State Leakage C urrent | I OZ | 5.5V | High Z Output, V = V or V , IN IL IH V =V or GND OUT CC | ±0.25 | ±2.5 | ±10 | µA |
| Maximum Quiescent Supply Leakage Current4 | I CC | 5.5V | V = V or GND IN CC │I │≤ 0µA OUT | 4 | 40 | 80 | µA |
- -55˚C ≤ TJ ≤ +125˚C
AC Electrical Characteristics5 VCC = 5.0V ±0.5V, Input tr = tf = 3ns, RL = 1kΩ
| PARA METER | SYMBOL | V CC | CONDITIONS | LIMITS | UNITS | ||
|---|---|---|---|---|---|---|---|
| 25°C | 85°C | FULL RANGE4 | |||||
| Maximum Propagation Delay, D to Q, (Figure 1,5) | t t PLH, PHL | 3.3V ±10% | C = 15pF L | 11.4 | 13.5 | 14.5 | ns |
| C = 50pF L | 14.9 | 17.0 | 19.0 | ||||
| 5V ±10% | C = 15pF L | 7.2 | 8.5 | 9.0 | |||
| C = 50pF L | 9.2 | 10.5 | 11.5 | ||||
| Max imum Propagation Delay, LE to Q, (Figure 2,5) | t t PLH, PHL | 3.3V ±10% | C = 15pF L | 11.0 | 13.0 | 14.0 | ns |
| C = 50pF L | 14.5 | 16.5 | 18.5 | ||||
| 5V ±10% | C = 15pF L | 7.2 | 8.5 | 9.0 | |||
| C = 50pF L | 9.2 | 10.5 | 11.5 | ||||
| Maximum Propagation Delay, OE to Q, (Figure 3,6) | t t PLZ, PHZ | 3.3V ±10% | C = 50pF L | 13.2 | 15.0 | 17.0 | ns |
| 5V ±10% | 9.2 | 10.5 | 11.5 | ||||
| Maximum Propagation Delay, OE to Q, (Figure 3,6) | t t PZL, PZH | 3.3V ±10% | C = 15pF L | 11.4 | 13.5 | 14.5 | ns |
| C = 50pF L | 14.9 | 17.0 | 19.0 | ||||
| 5V ±10% | C = 15pF L | 8.1 | 9.5 | 10.5 | |||
| C = 50pF L | 10.1 | 11.5 | 13.0 | ||||
- Not production tested in die form, characterized by chip design.
Page 4 of 7
Page 5
Rev 1.0
26/09/20
AC Electrical Characteristics continued6 VCC = 5.0V ±0.5V, RL = 1kΩ, Input tr = tf = 3ns
| PARAMETER | SYMBOL | V CC | CONDITIONS | LIMITS | UNITS | ||
|---|---|---|---|---|---|---|---|
| 25°C | 85°C | FULL RANGE4 | |||||
| Maximum Input Capac itance | C IN | 5V ±10% | C = 50pF L | 10 | 10 | 10 | pF |
| Maximum 3-State Output Capacitance | C OUT | 5V ±10% | C = 50pF L | 12 | 12 | 12 | pF |
| Power Dissipation Capacitance7 | C PD | - | T = 25°C, J V =5.0V CC | LIMITS | pF | ||
| 54 | |||||||
- Not production tested in die form, characterized by chip design. 7. Used to determine the no-load dynamic power consumption: PD = CPD VCC2f + ICC VCC.
Timing Requirements6
| PARAMETER | SYMBOL | V CC | CONDITIONS | LIMITS | UNITS | ||
|---|---|---|---|---|---|---|---|
| 25°C | 85°C | FULL RANGE4 | |||||
| Minimum Setup Time, D to LE (Figure 4) | t SU | 3.3V ±10% | C = 15pF L | 4.0 | 4.0 | 4.0 | ns |
| C = 50pF L | 4.0 | 4.0 | 4.0 | ||||
| 5V ±10% | C = 15pF L | 4.0 | 4.0 | 4.0 | |||
| C = 50pF L | 4.0 | 4.0 | 4.0 | ||||
| Minimum Hold Time, LE to D (Figure 4) | t h | 3.3V ±10% | C = 15pF L | 1.0 | 1.0 | 1.0 | ns |
| C = 50pF L | 1.0 | 1.0 | 1.0 | ||||
| 5V ±10% | C = 15pF L | 1.0 | 1.0 | 1.0 | |||
| C = 50pF L | 1.0 | 1.0 | 1.0 | ||||
| Minimum Pulse Width, LE (Figure 4) | t w | 3.3V ±10% | C = 15pF L | 5.0 | 5.0 | 5.0 | ns |
| C = 50pF L | 5.0 | 5.0 | 5.0 | ||||
| 5V ±10% | C = 15pF L | 5.0 | 5.0 | 5.0 | |||
| C = 50pF L | 5.0 | 5.0 | 5.0 | ||||
| Propagation delay difference between outputs | t ,t OSLH OSHL | 3.3V ±10% | C = 50pF L | 1.5 | 1.5 | 1.5 | ns |
| 5V ±10% | 1.0 | 1.0 | 1.0 | ||||
Page 5 of 7
Page 6
Rev 1.0
26/09/20
Noise Characteristics6
| PARAMETER | SYMBOL | V CC | CONDITIONS | LIMITS | UNITS | ||
|---|---|---|---|---|---|---|---|
| 25°C | 85°C | FULL RANGE4 | |||||
| Positive noise of low output voltage | V OLP | 5.0 | - | 0.9 | 0.9 | 0.9 | V |
| Negative noise of low output voltage | V OLV | 5.0 | - | -0.9 | -0.9 | -0.9 | V |
| Input dynamic high voltage | V IHD | 5.0 | - | 3.5 | 3.5 | 3.5 | V |
| Input dynamic low voltage | V ILD | 5.0 | - | 1.5 | 1.5 | 1.5 | V |
Switching Waveforms
Figure 1 – Propagation Delay & Output Transition Time
Figure 3 – Propagation Delay - Output Enable to Q
Page 6 of 7
Figure 2 – Propagation Delay – Latch Enable to Q
Figure 4 – Timing Requirements
Page 7
Rev 1.0
26/09/20
Test Circuits
TEST POINT
\* Includes all probe and jig capacitance
Figure 5
TEST POINT
CONNECT TO VCC WHEN
TESTING tPLZ,& tPZL.
CONNECT TO GND WHEN
TESTING tPHZ,& tPZH
\* Includes all probe and jig capacitance
Figure 6
